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40#include <linux/async.h>
41#include <linux/devfreq.h>
42#include <linux/nls.h>
43#include <linux/of.h>
44#include <linux/bitfield.h>
45#include "ufshcd.h"
46#include "ufs_quirks.h"
47#include "unipro.h"
48#include "ufs-sysfs.h"
49#include "ufs_bsg.h"
50
51#define CREATE_TRACE_POINTS
52#include <trace/events/ufs.h>
53
54#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
55 UTP_TASK_REQ_COMPL |\
56 UFSHCD_ERROR_MASK)
57
58#define UIC_CMD_TIMEOUT 500
59
60
61#define NOP_OUT_RETRIES 10
62
63#define NOP_OUT_TIMEOUT 30
64
65
66#define QUERY_REQ_RETRIES 3
67
68#define QUERY_REQ_TIMEOUT 1500
69
70
71#define TM_CMD_TIMEOUT 100
72
73
74#define UFS_UIC_COMMAND_RETRIES 3
75
76
77#define DME_LINKSTARTUP_RETRIES 3
78
79
80#define UIC_HIBERN8_ENTER_RETRIES 3
81
82
83#define MAX_HOST_RESET_RETRIES 5
84
85
86#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
87
88
89#define INT_AGGR_DEF_TO 0x02
90
91#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
92 ({ \
93 int _ret; \
94 if (_on) \
95 _ret = ufshcd_enable_vreg(_dev, _vreg); \
96 else \
97 _ret = ufshcd_disable_vreg(_dev, _vreg); \
98 _ret; \
99 })
100
101#define ufshcd_hex_dump(prefix_str, buf, len) do { \
102 size_t __len = (len); \
103 print_hex_dump(KERN_ERR, prefix_str, \
104 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
105 16, 4, buf, __len, false); \
106} while (0)
107
108int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
109 const char *prefix)
110{
111 u32 *regs;
112 size_t pos;
113
114 if (offset % 4 != 0 || len % 4 != 0)
115 return -EINVAL;
116
117 regs = kzalloc(len, GFP_KERNEL);
118 if (!regs)
119 return -ENOMEM;
120
121 for (pos = 0; pos < len; pos += 4)
122 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
123
124 ufshcd_hex_dump(prefix, regs, len);
125 kfree(regs);
126
127 return 0;
128}
129EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
130
131enum {
132 UFSHCD_MAX_CHANNEL = 0,
133 UFSHCD_MAX_ID = 1,
134 UFSHCD_CMD_PER_LUN = 32,
135 UFSHCD_CAN_QUEUE = 32,
136};
137
138
139enum {
140 UFSHCD_STATE_RESET,
141 UFSHCD_STATE_ERROR,
142 UFSHCD_STATE_OPERATIONAL,
143 UFSHCD_STATE_EH_SCHEDULED,
144};
145
146
147enum {
148 UFSHCD_EH_IN_PROGRESS = (1 << 0),
149};
150
151
152enum {
153 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0),
154 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1),
155 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2),
156 UFSHCD_UIC_NL_ERROR = (1 << 3),
157 UFSHCD_UIC_TL_ERROR = (1 << 4),
158 UFSHCD_UIC_DME_ERROR = (1 << 5),
159};
160
161#define ufshcd_set_eh_in_progress(h) \
162 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
163#define ufshcd_eh_in_progress(h) \
164 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
165#define ufshcd_clear_eh_in_progress(h) \
166 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
167
168#define ufshcd_set_ufs_dev_active(h) \
169 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
170#define ufshcd_set_ufs_dev_sleep(h) \
171 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
172#define ufshcd_set_ufs_dev_poweroff(h) \
173 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
174#define ufshcd_is_ufs_dev_active(h) \
175 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
176#define ufshcd_is_ufs_dev_sleep(h) \
177 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
178#define ufshcd_is_ufs_dev_poweroff(h) \
179 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
180
181struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
182 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
183 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
184 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
185 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
186 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
187 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
188};
189
190static inline enum ufs_dev_pwr_mode
191ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
192{
193 return ufs_pm_lvl_states[lvl].dev_state;
194}
195
196static inline enum uic_link_state
197ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
198{
199 return ufs_pm_lvl_states[lvl].link_state;
200}
201
202static inline enum ufs_pm_level
203ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
204 enum uic_link_state link_state)
205{
206 enum ufs_pm_level lvl;
207
208 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
209 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
210 (ufs_pm_lvl_states[lvl].link_state == link_state))
211 return lvl;
212 }
213
214
215 return UFS_PM_LVL_0;
216}
217
218static struct ufs_dev_fix ufs_fixups[] = {
219
220 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
221 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
222 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
223 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
224 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
225 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
226 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
227 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
228 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
229 UFS_DEVICE_QUIRK_PA_TACTIVATE),
230 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
231 UFS_DEVICE_QUIRK_PA_TACTIVATE),
232 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
233 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
234 UFS_FIX(UFS_VENDOR_SKHYNIX, "hB8aL1" ,
235 UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME),
236
237 END_FIX
238};
239
240static void ufshcd_tmc_handler(struct ufs_hba *hba);
241static void ufshcd_async_scan(void *data, async_cookie_t cookie);
242static int ufshcd_reset_and_restore(struct ufs_hba *hba);
243static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
244static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
245static void ufshcd_hba_exit(struct ufs_hba *hba);
246static int ufshcd_probe_hba(struct ufs_hba *hba);
247static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
248 bool skip_ref_clk);
249static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
250static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
251static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
252static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
253static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
254static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
255static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
256static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
257static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
258static irqreturn_t ufshcd_intr(int irq, void *__hba);
259static int ufshcd_change_power_mode(struct ufs_hba *hba,
260 struct ufs_pa_layer_attr *pwr_mode);
261static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
262{
263 return tag >= 0 && tag < hba->nutrs;
264}
265
266static inline int ufshcd_enable_irq(struct ufs_hba *hba)
267{
268 int ret = 0;
269
270 if (!hba->is_irq_enabled) {
271 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
272 hba);
273 if (ret)
274 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
275 __func__, ret);
276 hba->is_irq_enabled = true;
277 }
278
279 return ret;
280}
281
282static inline void ufshcd_disable_irq(struct ufs_hba *hba)
283{
284 if (hba->is_irq_enabled) {
285 free_irq(hba->irq, hba);
286 hba->is_irq_enabled = false;
287 }
288}
289
290static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
291{
292 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
293 scsi_unblock_requests(hba->host);
294}
295
296static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
297{
298 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
299 scsi_block_requests(hba->host);
300}
301
302
303static inline void ufshcd_remove_non_printable(char *val)
304{
305 if (!val)
306 return;
307
308 if (*val < 0x20 || *val > 0x7e)
309 *val = ' ';
310}
311
312static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
313 const char *str)
314{
315 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
316
317 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->sc.cdb);
318}
319
320static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, unsigned int tag,
321 const char *str)
322{
323 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
324
325 trace_ufshcd_upiu(dev_name(hba->dev), str, &rq->header, &rq->qr);
326}
327
328static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
329 const char *str)
330{
331 int off = (int)tag - hba->nutrs;
332 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[off];
333
334 trace_ufshcd_upiu(dev_name(hba->dev), str, &descp->req_header,
335 &descp->input_param1);
336}
337
338static void ufshcd_add_command_trace(struct ufs_hba *hba,
339 unsigned int tag, const char *str)
340{
341 sector_t lba = -1;
342 u8 opcode = 0;
343 u32 intr, doorbell;
344 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
345 int transfer_len = -1;
346
347 if (!trace_ufshcd_command_enabled()) {
348
349 if (lrbp->cmd)
350 ufshcd_add_cmd_upiu_trace(hba, tag, str);
351 return;
352 }
353
354 if (lrbp->cmd) {
355
356 ufshcd_add_cmd_upiu_trace(hba, tag, str);
357 opcode = (u8)(*lrbp->cmd->cmnd);
358 if ((opcode == READ_10) || (opcode == WRITE_10)) {
359
360
361
362
363 if (lrbp->cmd->request && lrbp->cmd->request->bio)
364 lba =
365 lrbp->cmd->request->bio->bi_iter.bi_sector;
366 transfer_len = be32_to_cpu(
367 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
368 }
369 }
370
371 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
372 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
373 trace_ufshcd_command(dev_name(hba->dev), str, tag,
374 doorbell, transfer_len, intr, lba, opcode);
375}
376
377static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
378{
379 struct ufs_clk_info *clki;
380 struct list_head *head = &hba->clk_list_head;
381
382 if (list_empty(head))
383 return;
384
385 list_for_each_entry(clki, head, list) {
386 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
387 clki->max_freq)
388 dev_err(hba->dev, "clk: %s, rate: %u\n",
389 clki->name, clki->curr_freq);
390 }
391}
392
393static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
394 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
395{
396 int i;
397 bool found = false;
398
399 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
400 int p = (i + err_hist->pos) % UIC_ERR_REG_HIST_LENGTH;
401
402 if (err_hist->reg[p] == 0)
403 continue;
404 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
405 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
406 found = true;
407 }
408
409 if (!found)
410 dev_err(hba->dev, "No record of %s uic errors\n", err_name);
411}
412
413static void ufshcd_print_host_regs(struct ufs_hba *hba)
414{
415 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
416 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
417 hba->ufs_version, hba->capabilities);
418 dev_err(hba->dev,
419 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
420 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
421 dev_err(hba->dev,
422 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
423 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
424 hba->ufs_stats.hibern8_exit_cnt);
425
426 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
427 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
428 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
429 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
430 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
431
432 ufshcd_print_clk_freqs(hba);
433
434 if (hba->vops && hba->vops->dbg_register_dump)
435 hba->vops->dbg_register_dump(hba);
436}
437
438static
439void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
440{
441 struct ufshcd_lrb *lrbp;
442 int prdt_length;
443 int tag;
444
445 for_each_set_bit(tag, &bitmap, hba->nutrs) {
446 lrbp = &hba->lrb[tag];
447
448 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
449 tag, ktime_to_us(lrbp->issue_time_stamp));
450 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
451 tag, ktime_to_us(lrbp->compl_time_stamp));
452 dev_err(hba->dev,
453 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
454 tag, (u64)lrbp->utrd_dma_addr);
455
456 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
457 sizeof(struct utp_transfer_req_desc));
458 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
459 (u64)lrbp->ucd_req_dma_addr);
460 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
461 sizeof(struct utp_upiu_req));
462 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
463 (u64)lrbp->ucd_rsp_dma_addr);
464 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
465 sizeof(struct utp_upiu_rsp));
466
467 prdt_length = le16_to_cpu(
468 lrbp->utr_descriptor_ptr->prd_table_length);
469 dev_err(hba->dev,
470 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
471 tag, prdt_length,
472 (u64)lrbp->ucd_prdt_dma_addr);
473
474 if (pr_prdt)
475 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
476 sizeof(struct ufshcd_sg_entry) * prdt_length);
477 }
478}
479
480static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
481{
482 int tag;
483
484 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
485 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
486
487 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
488 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
489 }
490}
491
492static void ufshcd_print_host_state(struct ufs_hba *hba)
493{
494 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
495 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
496 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
497 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
498 hba->saved_err, hba->saved_uic_err);
499 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
500 hba->curr_dev_pwr_mode, hba->uic_link_state);
501 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
502 hba->pm_op_in_progress, hba->is_sys_suspended);
503 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
504 hba->auto_bkops_enabled, hba->host->host_self_blocked);
505 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
506 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
507 hba->eh_flags, hba->req_abort_count);
508 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
509 hba->capabilities, hba->caps);
510 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
511 hba->dev_quirks);
512}
513
514
515
516
517
518
519static void ufshcd_print_pwr_info(struct ufs_hba *hba)
520{
521 static const char * const names[] = {
522 "INVALID MODE",
523 "FAST MODE",
524 "SLOW_MODE",
525 "INVALID MODE",
526 "FASTAUTO_MODE",
527 "SLOWAUTO_MODE",
528 "INVALID MODE",
529 };
530
531 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
532 __func__,
533 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
534 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
535 names[hba->pwr_info.pwr_rx],
536 names[hba->pwr_info.pwr_tx],
537 hba->pwr_info.hs_rate);
538}
539
540
541
542
543
544
545
546
547
548
549
550
551
552int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
553 u32 val, unsigned long interval_us,
554 unsigned long timeout_ms, bool can_sleep)
555{
556 int err = 0;
557 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
558
559
560 val = val & mask;
561
562 while ((ufshcd_readl(hba, reg) & mask) != val) {
563 if (can_sleep)
564 usleep_range(interval_us, interval_us + 50);
565 else
566 udelay(interval_us);
567 if (time_after(jiffies, timeout)) {
568 if ((ufshcd_readl(hba, reg) & mask) != val)
569 err = -ETIMEDOUT;
570 break;
571 }
572 }
573
574 return err;
575}
576
577
578
579
580
581
582
583static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
584{
585 u32 intr_mask = 0;
586
587 switch (hba->ufs_version) {
588 case UFSHCI_VERSION_10:
589 intr_mask = INTERRUPT_MASK_ALL_VER_10;
590 break;
591 case UFSHCI_VERSION_11:
592 case UFSHCI_VERSION_20:
593 intr_mask = INTERRUPT_MASK_ALL_VER_11;
594 break;
595 case UFSHCI_VERSION_21:
596 default:
597 intr_mask = INTERRUPT_MASK_ALL_VER_21;
598 break;
599 }
600
601 return intr_mask;
602}
603
604
605
606
607
608
609
610static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
611{
612 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
613 return ufshcd_vops_get_ufs_hci_version(hba);
614
615 return ufshcd_readl(hba, REG_UFS_VERSION);
616}
617
618
619
620
621
622
623
624
625static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
626{
627 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
628 DEVICE_PRESENT) ? true : false;
629}
630
631
632
633
634
635
636
637
638static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
639{
640 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
641}
642
643
644
645
646
647
648
649
650
651
652static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
653{
654 int tag;
655 bool ret = false;
656
657 if (!free_slot)
658 goto out;
659
660 do {
661 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
662 if (tag >= hba->nutmrs)
663 goto out;
664 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
665
666 *free_slot = tag;
667 ret = true;
668out:
669 return ret;
670}
671
672static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
673{
674 clear_bit_unlock(slot, &hba->tm_slots_in_use);
675}
676
677
678
679
680
681
682static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
683{
684 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
685 ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
686 else
687 ufshcd_writel(hba, ~(1 << pos),
688 REG_UTP_TRANSFER_REQ_LIST_CLEAR);
689}
690
691
692
693
694
695
696static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
697{
698 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
699 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
700 else
701 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
702}
703
704
705
706
707
708
709static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
710{
711 __clear_bit(tag, &hba->outstanding_reqs);
712}
713
714
715
716
717
718
719
720static inline int ufshcd_get_lists_status(u32 reg)
721{
722 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
723}
724
725
726
727
728
729
730
731
732static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
733{
734 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
735 MASK_UIC_COMMAND_RESULT;
736}
737
738
739
740
741
742
743
744
745static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
746{
747 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
748}
749
750
751
752
753
754static inline int
755ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
756{
757 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
758}
759
760
761
762
763
764
765
766
767static inline int
768ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
769{
770 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
771}
772
773
774
775
776
777
778
779
780static inline unsigned int
781ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
782{
783 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
784 MASK_RSP_UPIU_DATA_SEG_LEN;
785}
786
787
788
789
790
791
792
793
794
795
796static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
797{
798 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
799 MASK_RSP_EXCEPTION_EVENT ? true : false;
800}
801
802
803
804
805
806static inline void
807ufshcd_reset_intr_aggr(struct ufs_hba *hba)
808{
809 ufshcd_writel(hba, INT_AGGR_ENABLE |
810 INT_AGGR_COUNTER_AND_TIMER_RESET,
811 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
812}
813
814
815
816
817
818
819
820static inline void
821ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
822{
823 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
824 INT_AGGR_COUNTER_THLD_VAL(cnt) |
825 INT_AGGR_TIMEOUT_VAL(tmout),
826 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
827}
828
829
830
831
832
833static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
834{
835 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
836}
837
838
839
840
841
842
843
844static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
845{
846 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
847 REG_UTP_TASK_REQ_LIST_RUN_STOP);
848 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
849 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
850}
851
852
853
854
855
856static inline void ufshcd_hba_start(struct ufs_hba *hba)
857{
858 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
859}
860
861
862
863
864
865
866
867static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
868{
869 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
870 ? false : true;
871}
872
873u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
874{
875
876 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
877 (hba->ufs_version == UFSHCI_VERSION_11))
878 return UFS_UNIPRO_VER_1_41;
879 else
880 return UFS_UNIPRO_VER_1_6;
881}
882EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
883
884static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
885{
886
887
888
889
890
891
892
893
894
895 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
896 return true;
897 else
898 return false;
899}
900
901static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
902{
903 int ret = 0;
904 struct ufs_clk_info *clki;
905 struct list_head *head = &hba->clk_list_head;
906 ktime_t start = ktime_get();
907 bool clk_state_changed = false;
908
909 if (list_empty(head))
910 goto out;
911
912 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
913 if (ret)
914 return ret;
915
916 list_for_each_entry(clki, head, list) {
917 if (!IS_ERR_OR_NULL(clki->clk)) {
918 if (scale_up && clki->max_freq) {
919 if (clki->curr_freq == clki->max_freq)
920 continue;
921
922 clk_state_changed = true;
923 ret = clk_set_rate(clki->clk, clki->max_freq);
924 if (ret) {
925 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
926 __func__, clki->name,
927 clki->max_freq, ret);
928 break;
929 }
930 trace_ufshcd_clk_scaling(dev_name(hba->dev),
931 "scaled up", clki->name,
932 clki->curr_freq,
933 clki->max_freq);
934
935 clki->curr_freq = clki->max_freq;
936
937 } else if (!scale_up && clki->min_freq) {
938 if (clki->curr_freq == clki->min_freq)
939 continue;
940
941 clk_state_changed = true;
942 ret = clk_set_rate(clki->clk, clki->min_freq);
943 if (ret) {
944 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
945 __func__, clki->name,
946 clki->min_freq, ret);
947 break;
948 }
949 trace_ufshcd_clk_scaling(dev_name(hba->dev),
950 "scaled down", clki->name,
951 clki->curr_freq,
952 clki->min_freq);
953 clki->curr_freq = clki->min_freq;
954 }
955 }
956 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
957 clki->name, clk_get_rate(clki->clk));
958 }
959
960 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
961
962out:
963 if (clk_state_changed)
964 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
965 (scale_up ? "up" : "down"),
966 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
967 return ret;
968}
969
970
971
972
973
974
975
976
977static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
978 bool scale_up)
979{
980 struct ufs_clk_info *clki;
981 struct list_head *head = &hba->clk_list_head;
982
983 if (list_empty(head))
984 return false;
985
986 list_for_each_entry(clki, head, list) {
987 if (!IS_ERR_OR_NULL(clki->clk)) {
988 if (scale_up && clki->max_freq) {
989 if (clki->curr_freq == clki->max_freq)
990 continue;
991 return true;
992 } else if (!scale_up && clki->min_freq) {
993 if (clki->curr_freq == clki->min_freq)
994 continue;
995 return true;
996 }
997 }
998 }
999
1000 return false;
1001}
1002
1003static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1004 u64 wait_timeout_us)
1005{
1006 unsigned long flags;
1007 int ret = 0;
1008 u32 tm_doorbell;
1009 u32 tr_doorbell;
1010 bool timeout = false, do_last_check = false;
1011 ktime_t start;
1012
1013 ufshcd_hold(hba, false);
1014 spin_lock_irqsave(hba->host->host_lock, flags);
1015
1016
1017
1018
1019 start = ktime_get();
1020 do {
1021 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1022 ret = -EBUSY;
1023 goto out;
1024 }
1025
1026 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1027 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1028 if (!tm_doorbell && !tr_doorbell) {
1029 timeout = false;
1030 break;
1031 } else if (do_last_check) {
1032 break;
1033 }
1034
1035 spin_unlock_irqrestore(hba->host->host_lock, flags);
1036 schedule();
1037 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1038 wait_timeout_us) {
1039 timeout = true;
1040
1041
1042
1043
1044
1045 do_last_check = true;
1046 }
1047 spin_lock_irqsave(hba->host->host_lock, flags);
1048 } while (tm_doorbell || tr_doorbell);
1049
1050 if (timeout) {
1051 dev_err(hba->dev,
1052 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1053 __func__, tm_doorbell, tr_doorbell);
1054 ret = -EBUSY;
1055 }
1056out:
1057 spin_unlock_irqrestore(hba->host->host_lock, flags);
1058 ufshcd_release(hba);
1059 return ret;
1060}
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1072{
1073 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1074 int ret = 0;
1075 struct ufs_pa_layer_attr new_pwr_info;
1076
1077 if (scale_up) {
1078 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1079 sizeof(struct ufs_pa_layer_attr));
1080 } else {
1081 memcpy(&new_pwr_info, &hba->pwr_info,
1082 sizeof(struct ufs_pa_layer_attr));
1083
1084 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1085 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1086
1087 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1088 &hba->pwr_info,
1089 sizeof(struct ufs_pa_layer_attr));
1090
1091
1092 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1093 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1094 }
1095 }
1096
1097
1098 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1099
1100 if (ret)
1101 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1102 __func__, ret,
1103 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1104 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1105
1106 return ret;
1107}
1108
1109static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1110{
1111 #define DOORBELL_CLR_TOUT_US (1000 * 1000)
1112 int ret = 0;
1113
1114
1115
1116
1117 ufshcd_scsi_block_requests(hba);
1118 down_write(&hba->clk_scaling_lock);
1119 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1120 ret = -EBUSY;
1121 up_write(&hba->clk_scaling_lock);
1122 ufshcd_scsi_unblock_requests(hba);
1123 }
1124
1125 return ret;
1126}
1127
1128static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1129{
1130 up_write(&hba->clk_scaling_lock);
1131 ufshcd_scsi_unblock_requests(hba);
1132}
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1144{
1145 int ret = 0;
1146
1147
1148 ufshcd_hold(hba, false);
1149
1150 ret = ufshcd_clock_scaling_prepare(hba);
1151 if (ret)
1152 return ret;
1153
1154
1155 if (!scale_up) {
1156 ret = ufshcd_scale_gear(hba, false);
1157 if (ret)
1158 goto out;
1159 }
1160
1161 ret = ufshcd_scale_clks(hba, scale_up);
1162 if (ret) {
1163 if (!scale_up)
1164 ufshcd_scale_gear(hba, true);
1165 goto out;
1166 }
1167
1168
1169 if (scale_up) {
1170 ret = ufshcd_scale_gear(hba, true);
1171 if (ret) {
1172 ufshcd_scale_clks(hba, false);
1173 goto out;
1174 }
1175 }
1176
1177 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1178
1179out:
1180 ufshcd_clock_scaling_unprepare(hba);
1181 ufshcd_release(hba);
1182 return ret;
1183}
1184
1185static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1186{
1187 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1188 clk_scaling.suspend_work);
1189 unsigned long irq_flags;
1190
1191 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1192 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1193 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1194 return;
1195 }
1196 hba->clk_scaling.is_suspended = true;
1197 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1198
1199 __ufshcd_suspend_clkscaling(hba);
1200}
1201
1202static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1203{
1204 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1205 clk_scaling.resume_work);
1206 unsigned long irq_flags;
1207
1208 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1209 if (!hba->clk_scaling.is_suspended) {
1210 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1211 return;
1212 }
1213 hba->clk_scaling.is_suspended = false;
1214 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1215
1216 devfreq_resume_device(hba->devfreq);
1217}
1218
1219static int ufshcd_devfreq_target(struct device *dev,
1220 unsigned long *freq, u32 flags)
1221{
1222 int ret = 0;
1223 struct ufs_hba *hba = dev_get_drvdata(dev);
1224 ktime_t start;
1225 bool scale_up, sched_clk_scaling_suspend_work = false;
1226 struct list_head *clk_list = &hba->clk_list_head;
1227 struct ufs_clk_info *clki;
1228 unsigned long irq_flags;
1229
1230 if (!ufshcd_is_clkscaling_supported(hba))
1231 return -EINVAL;
1232
1233 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1234 if (ufshcd_eh_in_progress(hba)) {
1235 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1236 return 0;
1237 }
1238
1239 if (!hba->clk_scaling.active_reqs)
1240 sched_clk_scaling_suspend_work = true;
1241
1242 if (list_empty(clk_list)) {
1243 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1244 goto out;
1245 }
1246
1247 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1248 scale_up = (*freq == clki->max_freq) ? true : false;
1249 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1250 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1251 ret = 0;
1252 goto out;
1253 }
1254 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1255
1256 start = ktime_get();
1257 ret = ufshcd_devfreq_scale(hba, scale_up);
1258
1259 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1260 (scale_up ? "up" : "down"),
1261 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1262
1263out:
1264 if (sched_clk_scaling_suspend_work)
1265 queue_work(hba->clk_scaling.workq,
1266 &hba->clk_scaling.suspend_work);
1267
1268 return ret;
1269}
1270
1271
1272static int ufshcd_devfreq_get_dev_status(struct device *dev,
1273 struct devfreq_dev_status *stat)
1274{
1275 struct ufs_hba *hba = dev_get_drvdata(dev);
1276 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1277 unsigned long flags;
1278
1279 if (!ufshcd_is_clkscaling_supported(hba))
1280 return -EINVAL;
1281
1282 memset(stat, 0, sizeof(*stat));
1283
1284 spin_lock_irqsave(hba->host->host_lock, flags);
1285 if (!scaling->window_start_t)
1286 goto start_window;
1287
1288 if (scaling->is_busy_started)
1289 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1290 scaling->busy_start_t));
1291
1292 stat->total_time = jiffies_to_usecs((long)jiffies -
1293 (long)scaling->window_start_t);
1294 stat->busy_time = scaling->tot_busy_t;
1295start_window:
1296 scaling->window_start_t = jiffies;
1297 scaling->tot_busy_t = 0;
1298
1299 if (hba->outstanding_reqs) {
1300 scaling->busy_start_t = ktime_get();
1301 scaling->is_busy_started = true;
1302 } else {
1303 scaling->busy_start_t = 0;
1304 scaling->is_busy_started = false;
1305 }
1306 spin_unlock_irqrestore(hba->host->host_lock, flags);
1307 return 0;
1308}
1309
1310static struct devfreq_dev_profile ufs_devfreq_profile = {
1311 .polling_ms = 100,
1312 .target = ufshcd_devfreq_target,
1313 .get_dev_status = ufshcd_devfreq_get_dev_status,
1314};
1315
1316static int ufshcd_devfreq_init(struct ufs_hba *hba)
1317{
1318 struct list_head *clk_list = &hba->clk_list_head;
1319 struct ufs_clk_info *clki;
1320 struct devfreq *devfreq;
1321 int ret;
1322
1323
1324 if (list_empty(clk_list))
1325 return 0;
1326
1327 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1328 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1329 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1330
1331 devfreq = devfreq_add_device(hba->dev,
1332 &ufs_devfreq_profile,
1333 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1334 NULL);
1335 if (IS_ERR(devfreq)) {
1336 ret = PTR_ERR(devfreq);
1337 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1338
1339 dev_pm_opp_remove(hba->dev, clki->min_freq);
1340 dev_pm_opp_remove(hba->dev, clki->max_freq);
1341 return ret;
1342 }
1343
1344 hba->devfreq = devfreq;
1345
1346 return 0;
1347}
1348
1349static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1350{
1351 struct list_head *clk_list = &hba->clk_list_head;
1352 struct ufs_clk_info *clki;
1353
1354 if (!hba->devfreq)
1355 return;
1356
1357 devfreq_remove_device(hba->devfreq);
1358 hba->devfreq = NULL;
1359
1360 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1361 dev_pm_opp_remove(hba->dev, clki->min_freq);
1362 dev_pm_opp_remove(hba->dev, clki->max_freq);
1363}
1364
1365static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1366{
1367 unsigned long flags;
1368
1369 devfreq_suspend_device(hba->devfreq);
1370 spin_lock_irqsave(hba->host->host_lock, flags);
1371 hba->clk_scaling.window_start_t = 0;
1372 spin_unlock_irqrestore(hba->host->host_lock, flags);
1373}
1374
1375static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1376{
1377 unsigned long flags;
1378 bool suspend = false;
1379
1380 if (!ufshcd_is_clkscaling_supported(hba))
1381 return;
1382
1383 spin_lock_irqsave(hba->host->host_lock, flags);
1384 if (!hba->clk_scaling.is_suspended) {
1385 suspend = true;
1386 hba->clk_scaling.is_suspended = true;
1387 }
1388 spin_unlock_irqrestore(hba->host->host_lock, flags);
1389
1390 if (suspend)
1391 __ufshcd_suspend_clkscaling(hba);
1392}
1393
1394static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1395{
1396 unsigned long flags;
1397 bool resume = false;
1398
1399 if (!ufshcd_is_clkscaling_supported(hba))
1400 return;
1401
1402 spin_lock_irqsave(hba->host->host_lock, flags);
1403 if (hba->clk_scaling.is_suspended) {
1404 resume = true;
1405 hba->clk_scaling.is_suspended = false;
1406 }
1407 spin_unlock_irqrestore(hba->host->host_lock, flags);
1408
1409 if (resume)
1410 devfreq_resume_device(hba->devfreq);
1411}
1412
1413static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1414 struct device_attribute *attr, char *buf)
1415{
1416 struct ufs_hba *hba = dev_get_drvdata(dev);
1417
1418 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1419}
1420
1421static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1422 struct device_attribute *attr, const char *buf, size_t count)
1423{
1424 struct ufs_hba *hba = dev_get_drvdata(dev);
1425 u32 value;
1426 int err;
1427
1428 if (kstrtou32(buf, 0, &value))
1429 return -EINVAL;
1430
1431 value = !!value;
1432 if (value == hba->clk_scaling.is_allowed)
1433 goto out;
1434
1435 pm_runtime_get_sync(hba->dev);
1436 ufshcd_hold(hba, false);
1437
1438 cancel_work_sync(&hba->clk_scaling.suspend_work);
1439 cancel_work_sync(&hba->clk_scaling.resume_work);
1440
1441 hba->clk_scaling.is_allowed = value;
1442
1443 if (value) {
1444 ufshcd_resume_clkscaling(hba);
1445 } else {
1446 ufshcd_suspend_clkscaling(hba);
1447 err = ufshcd_devfreq_scale(hba, true);
1448 if (err)
1449 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1450 __func__, err);
1451 }
1452
1453 ufshcd_release(hba);
1454 pm_runtime_put_sync(hba->dev);
1455out:
1456 return count;
1457}
1458
1459static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1460{
1461 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1462 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1463 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1464 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1465 hba->clk_scaling.enable_attr.attr.mode = 0644;
1466 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1467 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1468}
1469
1470static void ufshcd_ungate_work(struct work_struct *work)
1471{
1472 int ret;
1473 unsigned long flags;
1474 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1475 clk_gating.ungate_work);
1476
1477 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1478
1479 spin_lock_irqsave(hba->host->host_lock, flags);
1480 if (hba->clk_gating.state == CLKS_ON) {
1481 spin_unlock_irqrestore(hba->host->host_lock, flags);
1482 goto unblock_reqs;
1483 }
1484
1485 spin_unlock_irqrestore(hba->host->host_lock, flags);
1486 ufshcd_setup_clocks(hba, true);
1487
1488
1489 if (ufshcd_can_hibern8_during_gating(hba)) {
1490
1491 hba->clk_gating.is_suspended = true;
1492 if (ufshcd_is_link_hibern8(hba)) {
1493 ret = ufshcd_uic_hibern8_exit(hba);
1494 if (ret)
1495 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1496 __func__, ret);
1497 else
1498 ufshcd_set_link_active(hba);
1499 }
1500 hba->clk_gating.is_suspended = false;
1501 }
1502unblock_reqs:
1503 ufshcd_scsi_unblock_requests(hba);
1504}
1505
1506
1507
1508
1509
1510
1511
1512int ufshcd_hold(struct ufs_hba *hba, bool async)
1513{
1514 int rc = 0;
1515 unsigned long flags;
1516
1517 if (!ufshcd_is_clkgating_allowed(hba))
1518 goto out;
1519 spin_lock_irqsave(hba->host->host_lock, flags);
1520 hba->clk_gating.active_reqs++;
1521
1522 if (ufshcd_eh_in_progress(hba)) {
1523 spin_unlock_irqrestore(hba->host->host_lock, flags);
1524 return 0;
1525 }
1526
1527start:
1528 switch (hba->clk_gating.state) {
1529 case CLKS_ON:
1530
1531
1532
1533
1534
1535
1536
1537
1538 if (ufshcd_can_hibern8_during_gating(hba) &&
1539 ufshcd_is_link_hibern8(hba)) {
1540 spin_unlock_irqrestore(hba->host->host_lock, flags);
1541 flush_work(&hba->clk_gating.ungate_work);
1542 spin_lock_irqsave(hba->host->host_lock, flags);
1543 goto start;
1544 }
1545 break;
1546 case REQ_CLKS_OFF:
1547 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1548 hba->clk_gating.state = CLKS_ON;
1549 trace_ufshcd_clk_gating(dev_name(hba->dev),
1550 hba->clk_gating.state);
1551 break;
1552 }
1553
1554
1555
1556
1557
1558
1559 case CLKS_OFF:
1560 ufshcd_scsi_block_requests(hba);
1561 hba->clk_gating.state = REQ_CLKS_ON;
1562 trace_ufshcd_clk_gating(dev_name(hba->dev),
1563 hba->clk_gating.state);
1564 queue_work(hba->clk_gating.clk_gating_workq,
1565 &hba->clk_gating.ungate_work);
1566
1567
1568
1569
1570
1571 case REQ_CLKS_ON:
1572 if (async) {
1573 rc = -EAGAIN;
1574 hba->clk_gating.active_reqs--;
1575 break;
1576 }
1577
1578 spin_unlock_irqrestore(hba->host->host_lock, flags);
1579 flush_work(&hba->clk_gating.ungate_work);
1580
1581 spin_lock_irqsave(hba->host->host_lock, flags);
1582 goto start;
1583 default:
1584 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1585 __func__, hba->clk_gating.state);
1586 break;
1587 }
1588 spin_unlock_irqrestore(hba->host->host_lock, flags);
1589out:
1590 return rc;
1591}
1592EXPORT_SYMBOL_GPL(ufshcd_hold);
1593
1594static void ufshcd_gate_work(struct work_struct *work)
1595{
1596 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1597 clk_gating.gate_work.work);
1598 unsigned long flags;
1599
1600 spin_lock_irqsave(hba->host->host_lock, flags);
1601
1602
1603
1604
1605
1606
1607 if (hba->clk_gating.is_suspended ||
1608 (hba->clk_gating.state == REQ_CLKS_ON)) {
1609 hba->clk_gating.state = CLKS_ON;
1610 trace_ufshcd_clk_gating(dev_name(hba->dev),
1611 hba->clk_gating.state);
1612 goto rel_lock;
1613 }
1614
1615 if (hba->clk_gating.active_reqs
1616 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1617 || hba->lrb_in_use || hba->outstanding_tasks
1618 || hba->active_uic_cmd || hba->uic_async_done)
1619 goto rel_lock;
1620
1621 spin_unlock_irqrestore(hba->host->host_lock, flags);
1622
1623
1624 if (ufshcd_can_hibern8_during_gating(hba)) {
1625 if (ufshcd_uic_hibern8_enter(hba)) {
1626 hba->clk_gating.state = CLKS_ON;
1627 trace_ufshcd_clk_gating(dev_name(hba->dev),
1628 hba->clk_gating.state);
1629 goto out;
1630 }
1631 ufshcd_set_link_hibern8(hba);
1632 }
1633
1634 if (!ufshcd_is_link_active(hba))
1635 ufshcd_setup_clocks(hba, false);
1636 else
1637
1638 __ufshcd_setup_clocks(hba, false, true);
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649 spin_lock_irqsave(hba->host->host_lock, flags);
1650 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1651 hba->clk_gating.state = CLKS_OFF;
1652 trace_ufshcd_clk_gating(dev_name(hba->dev),
1653 hba->clk_gating.state);
1654 }
1655rel_lock:
1656 spin_unlock_irqrestore(hba->host->host_lock, flags);
1657out:
1658 return;
1659}
1660
1661
1662static void __ufshcd_release(struct ufs_hba *hba)
1663{
1664 if (!ufshcd_is_clkgating_allowed(hba))
1665 return;
1666
1667 hba->clk_gating.active_reqs--;
1668
1669 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1670 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1671 || hba->lrb_in_use || hba->outstanding_tasks
1672 || hba->active_uic_cmd || hba->uic_async_done
1673 || ufshcd_eh_in_progress(hba))
1674 return;
1675
1676 hba->clk_gating.state = REQ_CLKS_OFF;
1677 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1678 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1679 &hba->clk_gating.gate_work,
1680 msecs_to_jiffies(hba->clk_gating.delay_ms));
1681}
1682
1683void ufshcd_release(struct ufs_hba *hba)
1684{
1685 unsigned long flags;
1686
1687 spin_lock_irqsave(hba->host->host_lock, flags);
1688 __ufshcd_release(hba);
1689 spin_unlock_irqrestore(hba->host->host_lock, flags);
1690}
1691EXPORT_SYMBOL_GPL(ufshcd_release);
1692
1693static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1694 struct device_attribute *attr, char *buf)
1695{
1696 struct ufs_hba *hba = dev_get_drvdata(dev);
1697
1698 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1699}
1700
1701static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1702 struct device_attribute *attr, const char *buf, size_t count)
1703{
1704 struct ufs_hba *hba = dev_get_drvdata(dev);
1705 unsigned long flags, value;
1706
1707 if (kstrtoul(buf, 0, &value))
1708 return -EINVAL;
1709
1710 spin_lock_irqsave(hba->host->host_lock, flags);
1711 hba->clk_gating.delay_ms = value;
1712 spin_unlock_irqrestore(hba->host->host_lock, flags);
1713 return count;
1714}
1715
1716static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1717 struct device_attribute *attr, char *buf)
1718{
1719 struct ufs_hba *hba = dev_get_drvdata(dev);
1720
1721 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1722}
1723
1724static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1725 struct device_attribute *attr, const char *buf, size_t count)
1726{
1727 struct ufs_hba *hba = dev_get_drvdata(dev);
1728 unsigned long flags;
1729 u32 value;
1730
1731 if (kstrtou32(buf, 0, &value))
1732 return -EINVAL;
1733
1734 value = !!value;
1735 if (value == hba->clk_gating.is_enabled)
1736 goto out;
1737
1738 if (value) {
1739 ufshcd_release(hba);
1740 } else {
1741 spin_lock_irqsave(hba->host->host_lock, flags);
1742 hba->clk_gating.active_reqs++;
1743 spin_unlock_irqrestore(hba->host->host_lock, flags);
1744 }
1745
1746 hba->clk_gating.is_enabled = value;
1747out:
1748 return count;
1749}
1750
1751static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1752{
1753 char wq_name[sizeof("ufs_clkscaling_00")];
1754
1755 if (!ufshcd_is_clkscaling_supported(hba))
1756 return;
1757
1758 INIT_WORK(&hba->clk_scaling.suspend_work,
1759 ufshcd_clk_scaling_suspend_work);
1760 INIT_WORK(&hba->clk_scaling.resume_work,
1761 ufshcd_clk_scaling_resume_work);
1762
1763 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1764 hba->host->host_no);
1765 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1766
1767 ufshcd_clkscaling_init_sysfs(hba);
1768}
1769
1770static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1771{
1772 if (!ufshcd_is_clkscaling_supported(hba))
1773 return;
1774
1775 destroy_workqueue(hba->clk_scaling.workq);
1776 ufshcd_devfreq_remove(hba);
1777}
1778
1779static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1780{
1781 char wq_name[sizeof("ufs_clk_gating_00")];
1782
1783 if (!ufshcd_is_clkgating_allowed(hba))
1784 return;
1785
1786 hba->clk_gating.delay_ms = 150;
1787 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1788 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1789
1790 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1791 hba->host->host_no);
1792 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1793 WQ_MEM_RECLAIM);
1794
1795 hba->clk_gating.is_enabled = true;
1796
1797 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1798 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1799 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1800 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1801 hba->clk_gating.delay_attr.attr.mode = 0644;
1802 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1803 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1804
1805 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1806 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1807 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1808 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1809 hba->clk_gating.enable_attr.attr.mode = 0644;
1810 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1811 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1812}
1813
1814static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1815{
1816 if (!ufshcd_is_clkgating_allowed(hba))
1817 return;
1818 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1819 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1820 cancel_work_sync(&hba->clk_gating.ungate_work);
1821 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1822 destroy_workqueue(hba->clk_gating.clk_gating_workq);
1823}
1824
1825
1826static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1827{
1828 bool queue_resume_work = false;
1829
1830 if (!ufshcd_is_clkscaling_supported(hba))
1831 return;
1832
1833 if (!hba->clk_scaling.active_reqs++)
1834 queue_resume_work = true;
1835
1836 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1837 return;
1838
1839 if (queue_resume_work)
1840 queue_work(hba->clk_scaling.workq,
1841 &hba->clk_scaling.resume_work);
1842
1843 if (!hba->clk_scaling.window_start_t) {
1844 hba->clk_scaling.window_start_t = jiffies;
1845 hba->clk_scaling.tot_busy_t = 0;
1846 hba->clk_scaling.is_busy_started = false;
1847 }
1848
1849 if (!hba->clk_scaling.is_busy_started) {
1850 hba->clk_scaling.busy_start_t = ktime_get();
1851 hba->clk_scaling.is_busy_started = true;
1852 }
1853}
1854
1855static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1856{
1857 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1858
1859 if (!ufshcd_is_clkscaling_supported(hba))
1860 return;
1861
1862 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1863 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1864 scaling->busy_start_t));
1865 scaling->busy_start_t = 0;
1866 scaling->is_busy_started = false;
1867 }
1868}
1869
1870
1871
1872
1873
1874static inline
1875void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1876{
1877 hba->lrb[task_tag].issue_time_stamp = ktime_get();
1878 hba->lrb[task_tag].compl_time_stamp = ktime_set(0, 0);
1879 ufshcd_clk_scaling_start_busy(hba);
1880 __set_bit(task_tag, &hba->outstanding_reqs);
1881 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1882
1883 wmb();
1884 ufshcd_add_command_trace(hba, task_tag, "send");
1885}
1886
1887
1888
1889
1890
1891static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1892{
1893 int len;
1894 if (lrbp->sense_buffer &&
1895 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
1896 int len_to_copy;
1897
1898 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
1899 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
1900
1901 memcpy(lrbp->sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
1902 len_to_copy);
1903 }
1904}
1905
1906
1907
1908
1909
1910
1911
1912static
1913int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1914{
1915 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1916
1917 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
1918
1919
1920 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
1921 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
1922 GENERAL_UPIU_REQUEST_SIZE;
1923 u16 resp_len;
1924 u16 buf_len;
1925
1926
1927 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
1928 MASK_QUERY_DATA_SEG_LEN;
1929 buf_len = be16_to_cpu(
1930 hba->dev_cmd.query.request.upiu_req.length);
1931 if (likely(buf_len >= resp_len)) {
1932 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1933 } else {
1934 dev_warn(hba->dev,
1935 "%s: Response size is bigger than buffer",
1936 __func__);
1937 return -EINVAL;
1938 }
1939 }
1940
1941 return 0;
1942}
1943
1944
1945
1946
1947
1948static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1949{
1950 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
1951
1952
1953 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1954 hba->nutmrs =
1955 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1956}
1957
1958
1959
1960
1961
1962
1963
1964static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1965{
1966 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1967 return true;
1968 else
1969 return false;
1970}
1971
1972
1973
1974
1975
1976
1977
1978
1979static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1980{
1981 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1982}
1983
1984
1985
1986
1987
1988
1989
1990
1991static inline void
1992ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1993{
1994 WARN_ON(hba->active_uic_cmd);
1995
1996 hba->active_uic_cmd = uic_cmd;
1997
1998
1999 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2000 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2001 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2002
2003
2004 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2005 REG_UIC_COMMAND);
2006}
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016static int
2017ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2018{
2019 int ret;
2020 unsigned long flags;
2021
2022 if (wait_for_completion_timeout(&uic_cmd->done,
2023 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
2024 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2025 else
2026 ret = -ETIMEDOUT;
2027
2028 spin_lock_irqsave(hba->host->host_lock, flags);
2029 hba->active_uic_cmd = NULL;
2030 spin_unlock_irqrestore(hba->host->host_lock, flags);
2031
2032 return ret;
2033}
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045static int
2046__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2047 bool completion)
2048{
2049 if (!ufshcd_ready_for_uic_cmd(hba)) {
2050 dev_err(hba->dev,
2051 "Controller not ready to accept UIC commands\n");
2052 return -EIO;
2053 }
2054
2055 if (completion)
2056 init_completion(&uic_cmd->done);
2057
2058 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2059
2060 return 0;
2061}
2062
2063
2064
2065
2066
2067
2068
2069
2070int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2071{
2072 int ret;
2073 unsigned long flags;
2074
2075 ufshcd_hold(hba, false);
2076 mutex_lock(&hba->uic_cmd_mutex);
2077 ufshcd_add_delay_before_dme_cmd(hba);
2078
2079 spin_lock_irqsave(hba->host->host_lock, flags);
2080 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2081 spin_unlock_irqrestore(hba->host->host_lock, flags);
2082 if (!ret)
2083 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2084
2085 mutex_unlock(&hba->uic_cmd_mutex);
2086
2087 ufshcd_release(hba);
2088 return ret;
2089}
2090
2091
2092
2093
2094
2095
2096
2097
2098static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2099{
2100 struct ufshcd_sg_entry *prd_table;
2101 struct scatterlist *sg;
2102 struct scsi_cmnd *cmd;
2103 int sg_segments;
2104 int i;
2105
2106 cmd = lrbp->cmd;
2107 sg_segments = scsi_dma_map(cmd);
2108 if (sg_segments < 0)
2109 return sg_segments;
2110
2111 if (sg_segments) {
2112 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2113 lrbp->utr_descriptor_ptr->prd_table_length =
2114 cpu_to_le16((u16)(sg_segments *
2115 sizeof(struct ufshcd_sg_entry)));
2116 else
2117 lrbp->utr_descriptor_ptr->prd_table_length =
2118 cpu_to_le16((u16) (sg_segments));
2119
2120 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2121
2122 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2123 prd_table[i].size =
2124 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2125 prd_table[i].base_addr =
2126 cpu_to_le32(lower_32_bits(sg->dma_address));
2127 prd_table[i].upper_addr =
2128 cpu_to_le32(upper_32_bits(sg->dma_address));
2129 prd_table[i].reserved = 0;
2130 }
2131 } else {
2132 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2133 }
2134
2135 return 0;
2136}
2137
2138
2139
2140
2141
2142
2143static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2144{
2145 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2146
2147 if (hba->ufs_version == UFSHCI_VERSION_10) {
2148 u32 rw;
2149 rw = set & INTERRUPT_MASK_RW_VER_10;
2150 set = rw | ((set ^ intrs) & intrs);
2151 } else {
2152 set |= intrs;
2153 }
2154
2155 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2156}
2157
2158
2159
2160
2161
2162
2163static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2164{
2165 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2166
2167 if (hba->ufs_version == UFSHCI_VERSION_10) {
2168 u32 rw;
2169 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2170 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2171 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2172
2173 } else {
2174 set &= ~intrs;
2175 }
2176
2177 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2178}
2179
2180
2181
2182
2183
2184
2185
2186
2187static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2188 u32 *upiu_flags, enum dma_data_direction cmd_dir)
2189{
2190 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2191 u32 data_direction;
2192 u32 dword_0;
2193
2194 if (cmd_dir == DMA_FROM_DEVICE) {
2195 data_direction = UTP_DEVICE_TO_HOST;
2196 *upiu_flags = UPIU_CMD_FLAGS_READ;
2197 } else if (cmd_dir == DMA_TO_DEVICE) {
2198 data_direction = UTP_HOST_TO_DEVICE;
2199 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2200 } else {
2201 data_direction = UTP_NO_DATA_TRANSFER;
2202 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2203 }
2204
2205 dword_0 = data_direction | (lrbp->command_type
2206 << UPIU_COMMAND_TYPE_OFFSET);
2207 if (lrbp->intr_cmd)
2208 dword_0 |= UTP_REQ_DESC_INT_CMD;
2209
2210
2211 req_desc->header.dword_0 = cpu_to_le32(dword_0);
2212
2213 req_desc->header.dword_1 = 0;
2214
2215
2216
2217
2218
2219 req_desc->header.dword_2 =
2220 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2221
2222 req_desc->header.dword_3 = 0;
2223
2224 req_desc->prd_table_length = 0;
2225}
2226
2227
2228
2229
2230
2231
2232
2233static
2234void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2235{
2236 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2237 unsigned short cdb_len;
2238
2239
2240 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2241 UPIU_TRANSACTION_COMMAND, upiu_flags,
2242 lrbp->lun, lrbp->task_tag);
2243 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2244 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2245
2246
2247 ucd_req_ptr->header.dword_2 = 0;
2248
2249 ucd_req_ptr->sc.exp_data_transfer_len =
2250 cpu_to_be32(lrbp->cmd->sdb.length);
2251
2252 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, UFS_CDB_SIZE);
2253 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2254 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2255
2256 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2257}
2258
2259
2260
2261
2262
2263
2264
2265
2266static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2267 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2268{
2269 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2270 struct ufs_query *query = &hba->dev_cmd.query;
2271 u16 len = be16_to_cpu(query->request.upiu_req.length);
2272
2273
2274 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2275 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2276 lrbp->lun, lrbp->task_tag);
2277 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2278 0, query->request.query_func, 0, 0);
2279
2280
2281 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2282 ucd_req_ptr->header.dword_2 =
2283 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2284 else
2285 ucd_req_ptr->header.dword_2 = 0;
2286
2287
2288 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2289 QUERY_OSF_SIZE);
2290
2291
2292 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2293 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2294
2295 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2296}
2297
2298static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2299{
2300 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2301
2302 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2303
2304
2305 ucd_req_ptr->header.dword_0 =
2306 UPIU_HEADER_DWORD(
2307 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2308
2309 ucd_req_ptr->header.dword_1 = 0;
2310 ucd_req_ptr->header.dword_2 = 0;
2311
2312 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2313}
2314
2315
2316
2317
2318
2319
2320
2321static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2322{
2323 u32 upiu_flags;
2324 int ret = 0;
2325
2326 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2327 (hba->ufs_version == UFSHCI_VERSION_11))
2328 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2329 else
2330 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2331
2332 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2333 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2334 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2335 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2336 ufshcd_prepare_utp_nop_upiu(lrbp);
2337 else
2338 ret = -EINVAL;
2339
2340 return ret;
2341}
2342
2343
2344
2345
2346
2347
2348
2349static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2350{
2351 u32 upiu_flags;
2352 int ret = 0;
2353
2354 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
2355 (hba->ufs_version == UFSHCI_VERSION_11))
2356 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2357 else
2358 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2359
2360 if (likely(lrbp->cmd)) {
2361 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2362 lrbp->cmd->sc_data_direction);
2363 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2364 } else {
2365 ret = -EINVAL;
2366 }
2367
2368 return ret;
2369}
2370
2371
2372
2373
2374
2375
2376
2377static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2378{
2379 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2380}
2381
2382
2383
2384
2385
2386
2387
2388
2389static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2390{
2391 struct ufshcd_lrb *lrbp;
2392 struct ufs_hba *hba;
2393 unsigned long flags;
2394 int tag;
2395 int err = 0;
2396
2397 hba = shost_priv(host);
2398
2399 tag = cmd->request->tag;
2400 if (!ufshcd_valid_tag(hba, tag)) {
2401 dev_err(hba->dev,
2402 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2403 __func__, tag, cmd, cmd->request);
2404 BUG();
2405 }
2406
2407 if (!down_read_trylock(&hba->clk_scaling_lock))
2408 return SCSI_MLQUEUE_HOST_BUSY;
2409
2410 spin_lock_irqsave(hba->host->host_lock, flags);
2411 switch (hba->ufshcd_state) {
2412 case UFSHCD_STATE_OPERATIONAL:
2413 break;
2414 case UFSHCD_STATE_EH_SCHEDULED:
2415 case UFSHCD_STATE_RESET:
2416 err = SCSI_MLQUEUE_HOST_BUSY;
2417 goto out_unlock;
2418 case UFSHCD_STATE_ERROR:
2419 set_host_byte(cmd, DID_ERROR);
2420 cmd->scsi_done(cmd);
2421 goto out_unlock;
2422 default:
2423 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2424 __func__, hba->ufshcd_state);
2425 set_host_byte(cmd, DID_BAD_TARGET);
2426 cmd->scsi_done(cmd);
2427 goto out_unlock;
2428 }
2429
2430
2431 if (ufshcd_eh_in_progress(hba)) {
2432 set_host_byte(cmd, DID_ERROR);
2433 cmd->scsi_done(cmd);
2434 goto out_unlock;
2435 }
2436 spin_unlock_irqrestore(hba->host->host_lock, flags);
2437
2438 hba->req_abort_count = 0;
2439
2440
2441 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2442
2443
2444
2445
2446
2447
2448 err = SCSI_MLQUEUE_HOST_BUSY;
2449 goto out;
2450 }
2451
2452 err = ufshcd_hold(hba, true);
2453 if (err) {
2454 err = SCSI_MLQUEUE_HOST_BUSY;
2455 clear_bit_unlock(tag, &hba->lrb_in_use);
2456 goto out;
2457 }
2458 WARN_ON(hba->clk_gating.state != CLKS_ON);
2459
2460 lrbp = &hba->lrb[tag];
2461
2462 WARN_ON(lrbp->cmd);
2463 lrbp->cmd = cmd;
2464 lrbp->sense_bufflen = UFS_SENSE_SIZE;
2465 lrbp->sense_buffer = cmd->sense_buffer;
2466 lrbp->task_tag = tag;
2467 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2468 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
2469 lrbp->req_abort_skip = false;
2470
2471 ufshcd_comp_scsi_upiu(hba, lrbp);
2472
2473 err = ufshcd_map_sg(hba, lrbp);
2474 if (err) {
2475 lrbp->cmd = NULL;
2476 clear_bit_unlock(tag, &hba->lrb_in_use);
2477 goto out;
2478 }
2479
2480 wmb();
2481
2482
2483 spin_lock_irqsave(hba->host->host_lock, flags);
2484 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
2485 ufshcd_send_command(hba, tag);
2486out_unlock:
2487 spin_unlock_irqrestore(hba->host->host_lock, flags);
2488out:
2489 up_read(&hba->clk_scaling_lock);
2490 return err;
2491}
2492
2493static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2494 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2495{
2496 lrbp->cmd = NULL;
2497 lrbp->sense_bufflen = 0;
2498 lrbp->sense_buffer = NULL;
2499 lrbp->task_tag = tag;
2500 lrbp->lun = 0;
2501 lrbp->intr_cmd = true;
2502 hba->dev_cmd.type = cmd_type;
2503
2504 return ufshcd_comp_devman_upiu(hba, lrbp);
2505}
2506
2507static int
2508ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2509{
2510 int err = 0;
2511 unsigned long flags;
2512 u32 mask = 1 << tag;
2513
2514
2515 spin_lock_irqsave(hba->host->host_lock, flags);
2516 ufshcd_utrl_clear(hba, tag);
2517 spin_unlock_irqrestore(hba->host->host_lock, flags);
2518
2519
2520
2521
2522
2523 err = ufshcd_wait_for_register(hba,
2524 REG_UTP_TRANSFER_REQ_DOOR_BELL,
2525 mask, ~mask, 1000, 1000, true);
2526
2527 return err;
2528}
2529
2530static int
2531ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2532{
2533 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2534
2535
2536 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2537 UPIU_RSP_CODE_OFFSET;
2538 return query_res->response;
2539}
2540
2541
2542
2543
2544
2545
2546static int
2547ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2548{
2549 int resp;
2550 int err = 0;
2551
2552 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2553 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2554
2555 switch (resp) {
2556 case UPIU_TRANSACTION_NOP_IN:
2557 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2558 err = -EINVAL;
2559 dev_err(hba->dev, "%s: unexpected response %x\n",
2560 __func__, resp);
2561 }
2562 break;
2563 case UPIU_TRANSACTION_QUERY_RSP:
2564 err = ufshcd_check_query_response(hba, lrbp);
2565 if (!err)
2566 err = ufshcd_copy_query_response(hba, lrbp);
2567 break;
2568 case UPIU_TRANSACTION_REJECT_UPIU:
2569
2570 err = -EPERM;
2571 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2572 __func__);
2573 break;
2574 default:
2575 err = -EINVAL;
2576 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2577 __func__, resp);
2578 break;
2579 }
2580
2581 return err;
2582}
2583
2584static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2585 struct ufshcd_lrb *lrbp, int max_timeout)
2586{
2587 int err = 0;
2588 unsigned long time_left;
2589 unsigned long flags;
2590
2591 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2592 msecs_to_jiffies(max_timeout));
2593
2594
2595 wmb();
2596 spin_lock_irqsave(hba->host->host_lock, flags);
2597 hba->dev_cmd.complete = NULL;
2598 if (likely(time_left)) {
2599 err = ufshcd_get_tr_ocs(lrbp);
2600 if (!err)
2601 err = ufshcd_dev_cmd_completion(hba, lrbp);
2602 }
2603 spin_unlock_irqrestore(hba->host->host_lock, flags);
2604
2605 if (!time_left) {
2606 err = -ETIMEDOUT;
2607 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2608 __func__, lrbp->task_tag);
2609 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
2610
2611 err = -EAGAIN;
2612
2613
2614
2615
2616
2617 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
2618 }
2619
2620 return err;
2621}
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2635{
2636 int tag;
2637 bool ret = false;
2638 unsigned long tmp;
2639
2640 if (!tag_out)
2641 goto out;
2642
2643 do {
2644 tmp = ~hba->lrb_in_use;
2645 tag = find_last_bit(&tmp, hba->nutrs);
2646 if (tag >= hba->nutrs)
2647 goto out;
2648 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2649
2650 *tag_out = tag;
2651 ret = true;
2652out:
2653 return ret;
2654}
2655
2656static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2657{
2658 clear_bit_unlock(tag, &hba->lrb_in_use);
2659}
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2671 enum dev_cmd_type cmd_type, int timeout)
2672{
2673 struct ufshcd_lrb *lrbp;
2674 int err;
2675 int tag;
2676 struct completion wait;
2677 unsigned long flags;
2678
2679 down_read(&hba->clk_scaling_lock);
2680
2681
2682
2683
2684
2685
2686 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2687
2688 init_completion(&wait);
2689 lrbp = &hba->lrb[tag];
2690 WARN_ON(lrbp->cmd);
2691 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2692 if (unlikely(err))
2693 goto out_put_tag;
2694
2695 hba->dev_cmd.complete = &wait;
2696
2697 ufshcd_add_query_upiu_trace(hba, tag, "query_send");
2698
2699 wmb();
2700 spin_lock_irqsave(hba->host->host_lock, flags);
2701 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
2702 ufshcd_send_command(hba, tag);
2703 spin_unlock_irqrestore(hba->host->host_lock, flags);
2704
2705 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2706
2707 ufshcd_add_query_upiu_trace(hba, tag,
2708 err ? "query_complete_err" : "query_complete");
2709
2710out_put_tag:
2711 ufshcd_put_dev_cmd_tag(hba, tag);
2712 wake_up(&hba->dev_cmd.tag_wq);
2713 up_read(&hba->clk_scaling_lock);
2714 return err;
2715}
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727static inline void ufshcd_init_query(struct ufs_hba *hba,
2728 struct ufs_query_req **request, struct ufs_query_res **response,
2729 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2730{
2731 *request = &hba->dev_cmd.query.request;
2732 *response = &hba->dev_cmd.query.response;
2733 memset(*request, 0, sizeof(struct ufs_query_req));
2734 memset(*response, 0, sizeof(struct ufs_query_res));
2735 (*request)->upiu_req.opcode = opcode;
2736 (*request)->upiu_req.idn = idn;
2737 (*request)->upiu_req.index = index;
2738 (*request)->upiu_req.selector = selector;
2739}
2740
2741static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2742 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2743{
2744 int ret;
2745 int retries;
2746
2747 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2748 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2749 if (ret)
2750 dev_dbg(hba->dev,
2751 "%s: failed with error %d, retries %d\n",
2752 __func__, ret, retries);
2753 else
2754 break;
2755 }
2756
2757 if (ret)
2758 dev_err(hba->dev,
2759 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2760 __func__, opcode, idn, ret, retries);
2761 return ret;
2762}
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
2774 enum flag_idn idn, bool *flag_res)
2775{
2776 struct ufs_query_req *request = NULL;
2777 struct ufs_query_res *response = NULL;
2778 int err, index = 0, selector = 0;
2779 int timeout = QUERY_REQ_TIMEOUT;
2780
2781 BUG_ON(!hba);
2782
2783 ufshcd_hold(hba, false);
2784 mutex_lock(&hba->dev_cmd.lock);
2785 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2786 selector);
2787
2788 switch (opcode) {
2789 case UPIU_QUERY_OPCODE_SET_FLAG:
2790 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2791 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2792 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2793 break;
2794 case UPIU_QUERY_OPCODE_READ_FLAG:
2795 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2796 if (!flag_res) {
2797
2798 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2799 __func__);
2800 err = -EINVAL;
2801 goto out_unlock;
2802 }
2803 break;
2804 default:
2805 dev_err(hba->dev,
2806 "%s: Expected query flag opcode but got = %d\n",
2807 __func__, opcode);
2808 err = -EINVAL;
2809 goto out_unlock;
2810 }
2811
2812 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
2813
2814 if (err) {
2815 dev_err(hba->dev,
2816 "%s: Sending flag query for idn %d failed, err = %d\n",
2817 __func__, idn, err);
2818 goto out_unlock;
2819 }
2820
2821 if (flag_res)
2822 *flag_res = (be32_to_cpu(response->upiu_res.value) &
2823 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2824
2825out_unlock:
2826 mutex_unlock(&hba->dev_cmd.lock);
2827 ufshcd_release(hba);
2828 return err;
2829}
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
2843 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2844{
2845 struct ufs_query_req *request = NULL;
2846 struct ufs_query_res *response = NULL;
2847 int err;
2848
2849 BUG_ON(!hba);
2850
2851 ufshcd_hold(hba, false);
2852 if (!attr_val) {
2853 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2854 __func__, opcode);
2855 err = -EINVAL;
2856 goto out;
2857 }
2858
2859 mutex_lock(&hba->dev_cmd.lock);
2860 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2861 selector);
2862
2863 switch (opcode) {
2864 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2865 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2866 request->upiu_req.value = cpu_to_be32(*attr_val);
2867 break;
2868 case UPIU_QUERY_OPCODE_READ_ATTR:
2869 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2870 break;
2871 default:
2872 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2873 __func__, opcode);
2874 err = -EINVAL;
2875 goto out_unlock;
2876 }
2877
2878 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2879
2880 if (err) {
2881 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2882 __func__, opcode, idn, index, err);
2883 goto out_unlock;
2884 }
2885
2886 *attr_val = be32_to_cpu(response->upiu_res.value);
2887
2888out_unlock:
2889 mutex_unlock(&hba->dev_cmd.lock);
2890out:
2891 ufshcd_release(hba);
2892 return err;
2893}
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2909 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2910 u32 *attr_val)
2911{
2912 int ret = 0;
2913 u32 retries;
2914
2915 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2916 ret = ufshcd_query_attr(hba, opcode, idn, index,
2917 selector, attr_val);
2918 if (ret)
2919 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2920 __func__, ret, retries);
2921 else
2922 break;
2923 }
2924
2925 if (ret)
2926 dev_err(hba->dev,
2927 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2928 __func__, idn, ret, QUERY_REQ_RETRIES);
2929 return ret;
2930}
2931
2932static int __ufshcd_query_descriptor(struct ufs_hba *hba,
2933 enum query_opcode opcode, enum desc_idn idn, u8 index,
2934 u8 selector, u8 *desc_buf, int *buf_len)
2935{
2936 struct ufs_query_req *request = NULL;
2937 struct ufs_query_res *response = NULL;
2938 int err;
2939
2940 BUG_ON(!hba);
2941
2942 ufshcd_hold(hba, false);
2943 if (!desc_buf) {
2944 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2945 __func__, opcode);
2946 err = -EINVAL;
2947 goto out;
2948 }
2949
2950 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
2951 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2952 __func__, *buf_len);
2953 err = -EINVAL;
2954 goto out;
2955 }
2956
2957 mutex_lock(&hba->dev_cmd.lock);
2958 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2959 selector);
2960 hba->dev_cmd.query.descriptor = desc_buf;
2961 request->upiu_req.length = cpu_to_be16(*buf_len);
2962
2963 switch (opcode) {
2964 case UPIU_QUERY_OPCODE_WRITE_DESC:
2965 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2966 break;
2967 case UPIU_QUERY_OPCODE_READ_DESC:
2968 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2969 break;
2970 default:
2971 dev_err(hba->dev,
2972 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2973 __func__, opcode);
2974 err = -EINVAL;
2975 goto out_unlock;
2976 }
2977
2978 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2979
2980 if (err) {
2981 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2982 __func__, opcode, idn, index, err);
2983 goto out_unlock;
2984 }
2985
2986 hba->dev_cmd.query.descriptor = NULL;
2987 *buf_len = be16_to_cpu(response->upiu_res.length);
2988
2989out_unlock:
2990 mutex_unlock(&hba->dev_cmd.lock);
2991out:
2992 ufshcd_release(hba);
2993 return err;
2994}
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3011 enum query_opcode opcode,
3012 enum desc_idn idn, u8 index,
3013 u8 selector,
3014 u8 *desc_buf, int *buf_len)
3015{
3016 int err;
3017 int retries;
3018
3019 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3020 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3021 selector, desc_buf, buf_len);
3022 if (!err || err == -EINVAL)
3023 break;
3024 }
3025
3026 return err;
3027}
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038static int ufshcd_read_desc_length(struct ufs_hba *hba,
3039 enum desc_idn desc_id,
3040 int desc_index,
3041 int *desc_length)
3042{
3043 int ret;
3044 u8 header[QUERY_DESC_HDR_SIZE];
3045 int header_len = QUERY_DESC_HDR_SIZE;
3046
3047 if (desc_id >= QUERY_DESC_IDN_MAX)
3048 return -EINVAL;
3049
3050 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3051 desc_id, desc_index, 0, header,
3052 &header_len);
3053
3054 if (ret) {
3055 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3056 __func__, desc_id);
3057 return ret;
3058 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3059 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3060 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3061 desc_id);
3062 ret = -EINVAL;
3063 }
3064
3065 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3066 return ret;
3067
3068}
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3079 enum desc_idn desc_id, int *desc_len)
3080{
3081 switch (desc_id) {
3082 case QUERY_DESC_IDN_DEVICE:
3083 *desc_len = hba->desc_size.dev_desc;
3084 break;
3085 case QUERY_DESC_IDN_POWER:
3086 *desc_len = hba->desc_size.pwr_desc;
3087 break;
3088 case QUERY_DESC_IDN_GEOMETRY:
3089 *desc_len = hba->desc_size.geom_desc;
3090 break;
3091 case QUERY_DESC_IDN_CONFIGURATION:
3092 *desc_len = hba->desc_size.conf_desc;
3093 break;
3094 case QUERY_DESC_IDN_UNIT:
3095 *desc_len = hba->desc_size.unit_desc;
3096 break;
3097 case QUERY_DESC_IDN_INTERCONNECT:
3098 *desc_len = hba->desc_size.interc_desc;
3099 break;
3100 case QUERY_DESC_IDN_STRING:
3101 *desc_len = QUERY_DESC_MAX_SIZE;
3102 break;
3103 case QUERY_DESC_IDN_HEALTH:
3104 *desc_len = hba->desc_size.hlth_desc;
3105 break;
3106 case QUERY_DESC_IDN_RFU_0:
3107 case QUERY_DESC_IDN_RFU_1:
3108 *desc_len = 0;
3109 break;
3110 default:
3111 *desc_len = 0;
3112 return -EINVAL;
3113 }
3114 return 0;
3115}
3116EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129int ufshcd_read_desc_param(struct ufs_hba *hba,
3130 enum desc_idn desc_id,
3131 int desc_index,
3132 u8 param_offset,
3133 u8 *param_read_buf,
3134 u8 param_size)
3135{
3136 int ret;
3137 u8 *desc_buf;
3138 int buff_len;
3139 bool is_kmalloc = true;
3140
3141
3142 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3143 return -EINVAL;
3144
3145
3146
3147
3148 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3149
3150
3151 if (ret || !buff_len) {
3152 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3153 __func__);
3154 return ret;
3155 }
3156
3157
3158 if (param_offset != 0 || param_size < buff_len) {
3159 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3160 if (!desc_buf)
3161 return -ENOMEM;
3162 } else {
3163 desc_buf = param_read_buf;
3164 is_kmalloc = false;
3165 }
3166
3167
3168 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3169 desc_id, desc_index, 0,
3170 desc_buf, &buff_len);
3171
3172 if (ret) {
3173 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3174 __func__, desc_id, desc_index, param_offset, ret);
3175 goto out;
3176 }
3177
3178
3179 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3180 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3181 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3182 ret = -EINVAL;
3183 goto out;
3184 }
3185
3186
3187 if (is_kmalloc && param_size > buff_len)
3188 param_size = buff_len;
3189
3190 if (is_kmalloc)
3191 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3192out:
3193 if (is_kmalloc)
3194 kfree(desc_buf);
3195 return ret;
3196}
3197
3198static inline int ufshcd_read_desc(struct ufs_hba *hba,
3199 enum desc_idn desc_id,
3200 int desc_index,
3201 u8 *buf,
3202 u32 size)
3203{
3204 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3205}
3206
3207static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3208 u8 *buf,
3209 u32 size)
3210{
3211 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
3212}
3213
3214static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
3215{
3216 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3217}
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3230 u8 *buf, u32 size, bool ascii)
3231{
3232 int err = 0;
3233
3234 err = ufshcd_read_desc(hba,
3235 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3236
3237 if (err) {
3238 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3239 __func__, QUERY_REQ_RETRIES, err);
3240 goto out;
3241 }
3242
3243 if (ascii) {
3244 int desc_len;
3245 int ascii_len;
3246 int i;
3247 char *buff_ascii;
3248
3249 desc_len = buf[0];
3250
3251 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3252 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3253 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3254 __func__);
3255 err = -ENOMEM;
3256 goto out;
3257 }
3258
3259 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3260 if (!buff_ascii) {
3261 err = -ENOMEM;
3262 goto out;
3263 }
3264
3265
3266
3267
3268
3269 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3270 desc_len - QUERY_DESC_HDR_SIZE,
3271 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3272
3273
3274 for (i = 0; i < ascii_len; i++)
3275 ufshcd_remove_non_printable(&buff_ascii[i]);
3276
3277 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3278 size - QUERY_DESC_HDR_SIZE);
3279 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3280 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
3281 kfree(buff_ascii);
3282 }
3283out:
3284 return err;
3285}
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3298 int lun,
3299 enum unit_desc_param param_offset,
3300 u8 *param_read_buf,
3301 u32 param_size)
3302{
3303
3304
3305
3306
3307 if (!ufs_is_valid_unit_desc_lun(lun))
3308 return -EOPNOTSUPP;
3309
3310 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3311 param_offset, param_read_buf, param_size);
3312}
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327static int ufshcd_memory_alloc(struct ufs_hba *hba)
3328{
3329 size_t utmrdl_size, utrdl_size, ucdl_size;
3330
3331
3332 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3333 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3334 ucdl_size,
3335 &hba->ucdl_dma_addr,
3336 GFP_KERNEL);
3337
3338
3339
3340
3341
3342
3343
3344 if (!hba->ucdl_base_addr ||
3345 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3346 dev_err(hba->dev,
3347 "Command Descriptor Memory allocation failed\n");
3348 goto out;
3349 }
3350
3351
3352
3353
3354
3355 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3356 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3357 utrdl_size,
3358 &hba->utrdl_dma_addr,
3359 GFP_KERNEL);
3360 if (!hba->utrdl_base_addr ||
3361 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3362 dev_err(hba->dev,
3363 "Transfer Descriptor Memory allocation failed\n");
3364 goto out;
3365 }
3366
3367
3368
3369
3370
3371 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3372 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3373 utmrdl_size,
3374 &hba->utmrdl_dma_addr,
3375 GFP_KERNEL);
3376 if (!hba->utmrdl_base_addr ||
3377 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3378 dev_err(hba->dev,
3379 "Task Management Descriptor Memory allocation failed\n");
3380 goto out;
3381 }
3382
3383
3384 hba->lrb = devm_kcalloc(hba->dev,
3385 hba->nutrs, sizeof(struct ufshcd_lrb),
3386 GFP_KERNEL);
3387 if (!hba->lrb) {
3388 dev_err(hba->dev, "LRB Memory allocation failed\n");
3389 goto out;
3390 }
3391 return 0;
3392out:
3393 return -ENOMEM;
3394}
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3410{
3411 struct utp_transfer_cmd_desc *cmd_descp;
3412 struct utp_transfer_req_desc *utrdlp;
3413 dma_addr_t cmd_desc_dma_addr;
3414 dma_addr_t cmd_desc_element_addr;
3415 u16 response_offset;
3416 u16 prdt_offset;
3417 int cmd_desc_size;
3418 int i;
3419
3420 utrdlp = hba->utrdl_base_addr;
3421 cmd_descp = hba->ucdl_base_addr;
3422
3423 response_offset =
3424 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3425 prdt_offset =
3426 offsetof(struct utp_transfer_cmd_desc, prd_table);
3427
3428 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3429 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3430
3431 for (i = 0; i < hba->nutrs; i++) {
3432
3433 cmd_desc_element_addr =
3434 (cmd_desc_dma_addr + (cmd_desc_size * i));
3435 utrdlp[i].command_desc_base_addr_lo =
3436 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3437 utrdlp[i].command_desc_base_addr_hi =
3438 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3439
3440
3441 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3442 utrdlp[i].response_upiu_offset =
3443 cpu_to_le16(response_offset);
3444 utrdlp[i].prd_table_offset =
3445 cpu_to_le16(prdt_offset);
3446 utrdlp[i].response_upiu_length =
3447 cpu_to_le16(ALIGNED_UPIU_SIZE);
3448 } else {
3449 utrdlp[i].response_upiu_offset =
3450 cpu_to_le16((response_offset >> 2));
3451 utrdlp[i].prd_table_offset =
3452 cpu_to_le16((prdt_offset >> 2));
3453 utrdlp[i].response_upiu_length =
3454 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3455 }
3456
3457 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
3458 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3459 (i * sizeof(struct utp_transfer_req_desc));
3460 hba->lrb[i].ucd_req_ptr =
3461 (struct utp_upiu_req *)(cmd_descp + i);
3462 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
3463 hba->lrb[i].ucd_rsp_ptr =
3464 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
3465 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3466 response_offset;
3467 hba->lrb[i].ucd_prdt_ptr =
3468 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
3469 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3470 prdt_offset;
3471 }
3472}
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3486{
3487 struct uic_command uic_cmd = {0};
3488 int ret;
3489
3490 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3491
3492 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3493 if (ret)
3494 dev_dbg(hba->dev,
3495 "dme-link-startup: error code %d\n", ret);
3496 return ret;
3497}
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507static int ufshcd_dme_reset(struct ufs_hba *hba)
3508{
3509 struct uic_command uic_cmd = {0};
3510 int ret;
3511
3512 uic_cmd.command = UIC_CMD_DME_RESET;
3513
3514 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3515 if (ret)
3516 dev_err(hba->dev,
3517 "dme-reset: error code %d\n", ret);
3518
3519 return ret;
3520}
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530static int ufshcd_dme_enable(struct ufs_hba *hba)
3531{
3532 struct uic_command uic_cmd = {0};
3533 int ret;
3534
3535 uic_cmd.command = UIC_CMD_DME_ENABLE;
3536
3537 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3538 if (ret)
3539 dev_err(hba->dev,
3540 "dme-reset: error code %d\n", ret);
3541
3542 return ret;
3543}
3544
3545static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3546{
3547 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3548 unsigned long min_sleep_time_us;
3549
3550 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3551 return;
3552
3553
3554
3555
3556
3557 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3558 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3559 } else {
3560 unsigned long delta =
3561 (unsigned long) ktime_to_us(
3562 ktime_sub(ktime_get(),
3563 hba->last_dme_cmd_tstamp));
3564
3565 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3566 min_sleep_time_us =
3567 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3568 else
3569 return;
3570 }
3571
3572
3573 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3574}
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3587 u8 attr_set, u32 mib_val, u8 peer)
3588{
3589 struct uic_command uic_cmd = {0};
3590 static const char *const action[] = {
3591 "dme-set",
3592 "dme-peer-set"
3593 };
3594 const char *set = action[!!peer];
3595 int ret;
3596 int retries = UFS_UIC_COMMAND_RETRIES;
3597
3598 uic_cmd.command = peer ?
3599 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3600 uic_cmd.argument1 = attr_sel;
3601 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3602 uic_cmd.argument3 = mib_val;
3603
3604 do {
3605
3606 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3607 if (ret)
3608 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3609 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3610 } while (ret && peer && --retries);
3611
3612 if (ret)
3613 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3614 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3615 UFS_UIC_COMMAND_RETRIES - retries);
3616
3617 return ret;
3618}
3619EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3631 u32 *mib_val, u8 peer)
3632{
3633 struct uic_command uic_cmd = {0};
3634 static const char *const action[] = {
3635 "dme-get",
3636 "dme-peer-get"
3637 };
3638 const char *get = action[!!peer];
3639 int ret;
3640 int retries = UFS_UIC_COMMAND_RETRIES;
3641 struct ufs_pa_layer_attr orig_pwr_info;
3642 struct ufs_pa_layer_attr temp_pwr_info;
3643 bool pwr_mode_change = false;
3644
3645 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3646 orig_pwr_info = hba->pwr_info;
3647 temp_pwr_info = orig_pwr_info;
3648
3649 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3650 orig_pwr_info.pwr_rx == FAST_MODE) {
3651 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3652 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3653 pwr_mode_change = true;
3654 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3655 orig_pwr_info.pwr_rx == SLOW_MODE) {
3656 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3657 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3658 pwr_mode_change = true;
3659 }
3660 if (pwr_mode_change) {
3661 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3662 if (ret)
3663 goto out;
3664 }
3665 }
3666
3667 uic_cmd.command = peer ?
3668 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3669 uic_cmd.argument1 = attr_sel;
3670
3671 do {
3672
3673 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3674 if (ret)
3675 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3676 get, UIC_GET_ATTR_ID(attr_sel), ret);
3677 } while (ret && peer && --retries);
3678
3679 if (ret)
3680 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
3681 get, UIC_GET_ATTR_ID(attr_sel),
3682 UFS_UIC_COMMAND_RETRIES - retries);
3683
3684 if (mib_val && !ret)
3685 *mib_val = uic_cmd.argument3;
3686
3687 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3688 && pwr_mode_change)
3689 ufshcd_change_power_mode(hba, &orig_pwr_info);
3690out:
3691 return ret;
3692}
3693EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
3712{
3713 struct completion uic_async_done;
3714 unsigned long flags;
3715 u8 status;
3716 int ret;
3717 bool reenable_intr = false;
3718
3719 mutex_lock(&hba->uic_cmd_mutex);
3720 init_completion(&uic_async_done);
3721 ufshcd_add_delay_before_dme_cmd(hba);
3722
3723 spin_lock_irqsave(hba->host->host_lock, flags);
3724 hba->uic_async_done = &uic_async_done;
3725 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3726 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3727
3728
3729
3730
3731 wmb();
3732 reenable_intr = true;
3733 }
3734 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3735 spin_unlock_irqrestore(hba->host->host_lock, flags);
3736 if (ret) {
3737 dev_err(hba->dev,
3738 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3739 cmd->command, cmd->argument3, ret);
3740 goto out;
3741 }
3742
3743 if (!wait_for_completion_timeout(hba->uic_async_done,
3744 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3745 dev_err(hba->dev,
3746 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3747 cmd->command, cmd->argument3);
3748 ret = -ETIMEDOUT;
3749 goto out;
3750 }
3751
3752 status = ufshcd_get_upmcrs(hba);
3753 if (status != PWR_LOCAL) {
3754 dev_err(hba->dev,
3755 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
3756 cmd->command, status);
3757 ret = (status != PWR_OK) ? status : -1;
3758 }
3759out:
3760 if (ret) {
3761 ufshcd_print_host_state(hba);
3762 ufshcd_print_pwr_info(hba);
3763 ufshcd_print_host_regs(hba);
3764 }
3765
3766 spin_lock_irqsave(hba->host->host_lock, flags);
3767 hba->active_uic_cmd = NULL;
3768 hba->uic_async_done = NULL;
3769 if (reenable_intr)
3770 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
3771 spin_unlock_irqrestore(hba->host->host_lock, flags);
3772 mutex_unlock(&hba->uic_cmd_mutex);
3773
3774 return ret;
3775}
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3786{
3787 struct uic_command uic_cmd = {0};
3788 int ret;
3789
3790 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3791 ret = ufshcd_dme_set(hba,
3792 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3793 if (ret) {
3794 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3795 __func__, ret);
3796 goto out;
3797 }
3798 }
3799
3800 uic_cmd.command = UIC_CMD_DME_SET;
3801 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3802 uic_cmd.argument3 = mode;
3803 ufshcd_hold(hba, false);
3804 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3805 ufshcd_release(hba);
3806
3807out:
3808 return ret;
3809}
3810
3811static int ufshcd_link_recovery(struct ufs_hba *hba)
3812{
3813 int ret;
3814 unsigned long flags;
3815
3816 spin_lock_irqsave(hba->host->host_lock, flags);
3817 hba->ufshcd_state = UFSHCD_STATE_RESET;
3818 ufshcd_set_eh_in_progress(hba);
3819 spin_unlock_irqrestore(hba->host->host_lock, flags);
3820
3821 ret = ufshcd_host_reset_and_restore(hba);
3822
3823 spin_lock_irqsave(hba->host->host_lock, flags);
3824 if (ret)
3825 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3826 ufshcd_clear_eh_in_progress(hba);
3827 spin_unlock_irqrestore(hba->host->host_lock, flags);
3828
3829 if (ret)
3830 dev_err(hba->dev, "%s: link recovery failed, err %d",
3831 __func__, ret);
3832
3833 return ret;
3834}
3835
3836static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3837{
3838 int ret;
3839 struct uic_command uic_cmd = {0};
3840 ktime_t start = ktime_get();
3841
3842 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3843
3844 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
3845 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3846 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3847 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3848
3849 if (ret) {
3850 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3851 __func__, ret);
3852
3853
3854
3855
3856
3857 if (ufshcd_link_recovery(hba))
3858 ret = -ENOLINK;
3859 } else
3860 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3861 POST_CHANGE);
3862
3863 return ret;
3864}
3865
3866static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3867{
3868 int ret = 0, retries;
3869
3870 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3871 ret = __ufshcd_uic_hibern8_enter(hba);
3872 if (!ret || ret == -ENOLINK)
3873 goto out;
3874 }
3875out:
3876 return ret;
3877}
3878
3879static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3880{
3881 struct uic_command uic_cmd = {0};
3882 int ret;
3883 ktime_t start = ktime_get();
3884
3885 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3886
3887 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3888 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3889 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3890 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3891
3892 if (ret) {
3893 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3894 __func__, ret);
3895 ret = ufshcd_link_recovery(hba);
3896 } else {
3897 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3898 POST_CHANGE);
3899 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3900 hba->ufs_stats.hibern8_exit_cnt++;
3901 }
3902
3903 return ret;
3904}
3905
3906static void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
3907{
3908 unsigned long flags;
3909
3910 if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) || !hba->ahit)
3911 return;
3912
3913 spin_lock_irqsave(hba->host->host_lock, flags);
3914 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
3915 spin_unlock_irqrestore(hba->host->host_lock, flags);
3916}
3917
3918
3919
3920
3921
3922
3923static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3924{
3925 hba->pwr_info.gear_rx = UFS_PWM_G1;
3926 hba->pwr_info.gear_tx = UFS_PWM_G1;
3927 hba->pwr_info.lane_rx = 1;
3928 hba->pwr_info.lane_tx = 1;
3929 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3930 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3931 hba->pwr_info.hs_rate = 0;
3932}
3933
3934
3935
3936
3937
3938static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
3939{
3940 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3941
3942 if (hba->max_pwr_info.is_valid)
3943 return 0;
3944
3945 pwr_info->pwr_tx = FAST_MODE;
3946 pwr_info->pwr_rx = FAST_MODE;
3947 pwr_info->hs_rate = PA_HS_MODE_B;
3948
3949
3950 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3951 &pwr_info->lane_rx);
3952 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3953 &pwr_info->lane_tx);
3954
3955 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3956 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3957 __func__,
3958 pwr_info->lane_rx,
3959 pwr_info->lane_tx);
3960 return -EINVAL;
3961 }
3962
3963
3964
3965
3966
3967
3968 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3969 if (!pwr_info->gear_rx) {
3970 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3971 &pwr_info->gear_rx);
3972 if (!pwr_info->gear_rx) {
3973 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3974 __func__, pwr_info->gear_rx);
3975 return -EINVAL;
3976 }
3977 pwr_info->pwr_rx = SLOW_MODE;
3978 }
3979
3980 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3981 &pwr_info->gear_tx);
3982 if (!pwr_info->gear_tx) {
3983 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3984 &pwr_info->gear_tx);
3985 if (!pwr_info->gear_tx) {
3986 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3987 __func__, pwr_info->gear_tx);
3988 return -EINVAL;
3989 }
3990 pwr_info->pwr_tx = SLOW_MODE;
3991 }
3992
3993 hba->max_pwr_info.is_valid = true;
3994 return 0;
3995}
3996
3997static int ufshcd_change_power_mode(struct ufs_hba *hba,
3998 struct ufs_pa_layer_attr *pwr_mode)
3999{
4000 int ret;
4001
4002
4003 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4004 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4005 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4006 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4007 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4008 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4009 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4010 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4011 return 0;
4012 }
4013
4014
4015
4016
4017
4018
4019
4020 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4021 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4022 pwr_mode->lane_rx);
4023 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4024 pwr_mode->pwr_rx == FAST_MODE)
4025 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
4026 else
4027 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
4028
4029 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4030 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4031 pwr_mode->lane_tx);
4032 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4033 pwr_mode->pwr_tx == FAST_MODE)
4034 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
4035 else
4036 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
4037
4038 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4039 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4040 pwr_mode->pwr_rx == FAST_MODE ||
4041 pwr_mode->pwr_tx == FAST_MODE)
4042 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4043 pwr_mode->hs_rate);
4044
4045 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4046 | pwr_mode->pwr_tx);
4047
4048 if (ret) {
4049 dev_err(hba->dev,
4050 "%s: power mode change failed %d\n", __func__, ret);
4051 } else {
4052 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4053 pwr_mode);
4054
4055 memcpy(&hba->pwr_info, pwr_mode,
4056 sizeof(struct ufs_pa_layer_attr));
4057 }
4058
4059 return ret;
4060}
4061
4062
4063
4064
4065
4066
4067int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4068 struct ufs_pa_layer_attr *desired_pwr_mode)
4069{
4070 struct ufs_pa_layer_attr final_params = { 0 };
4071 int ret;
4072
4073 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4074 desired_pwr_mode, &final_params);
4075
4076 if (ret)
4077 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4078
4079 ret = ufshcd_change_power_mode(hba, &final_params);
4080 if (!ret)
4081 ufshcd_print_pwr_info(hba);
4082
4083 return ret;
4084}
4085EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4086
4087
4088
4089
4090
4091
4092
4093static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4094{
4095 int i;
4096 int err;
4097 bool flag_res = 1;
4098
4099 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4100 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
4101 if (err) {
4102 dev_err(hba->dev,
4103 "%s setting fDeviceInit flag failed with error %d\n",
4104 __func__, err);
4105 goto out;
4106 }
4107
4108
4109 for (i = 0; i < 1000 && !err && flag_res; i++)
4110 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4111 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4112
4113 if (err)
4114 dev_err(hba->dev,
4115 "%s reading fDeviceInit flag failed with error %d\n",
4116 __func__, err);
4117 else if (flag_res)
4118 dev_err(hba->dev,
4119 "%s fDeviceInit was not cleared by the device\n",
4120 __func__);
4121
4122out:
4123 return err;
4124}
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4139{
4140 int err = 0;
4141 u32 reg;
4142
4143
4144 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4145
4146
4147 if (ufshcd_is_intr_aggr_allowed(hba))
4148 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4149 else
4150 ufshcd_disable_intr_aggr(hba);
4151
4152
4153 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4154 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4155 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4156 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4157 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4158 REG_UTP_TASK_REQ_LIST_BASE_L);
4159 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4160 REG_UTP_TASK_REQ_LIST_BASE_H);
4161
4162
4163
4164
4165
4166 wmb();
4167
4168
4169
4170
4171 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4172 if (!(ufshcd_get_lists_status(reg))) {
4173 ufshcd_enable_run_stop_reg(hba);
4174 } else {
4175 dev_err(hba->dev,
4176 "Host controller not ready to process requests");
4177 err = -EIO;
4178 goto out;
4179 }
4180
4181out:
4182 return err;
4183}
4184
4185
4186
4187
4188
4189
4190static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4191{
4192 int err;
4193
4194 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4195 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4196 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4197 10, 1, can_sleep);
4198 if (err)
4199 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4200}
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4213{
4214 int retry;
4215
4216
4217
4218
4219
4220
4221
4222 if (!ufshcd_is_hba_active(hba))
4223
4224 ufshcd_hba_stop(hba, true);
4225
4226
4227 ufshcd_set_link_off(hba);
4228
4229 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4230
4231
4232 ufshcd_hba_start(hba);
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244 msleep(1);
4245
4246
4247 retry = 10;
4248 while (ufshcd_is_hba_active(hba)) {
4249 if (retry) {
4250 retry--;
4251 } else {
4252 dev_err(hba->dev,
4253 "Controller enable failed\n");
4254 return -EIO;
4255 }
4256 msleep(5);
4257 }
4258
4259
4260 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4261
4262 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4263
4264 return 0;
4265}
4266
4267static int ufshcd_hba_enable(struct ufs_hba *hba)
4268{
4269 int ret;
4270
4271 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4272 ufshcd_set_link_off(hba);
4273 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4274
4275
4276 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4277 ret = ufshcd_dme_reset(hba);
4278 if (!ret) {
4279 ret = ufshcd_dme_enable(hba);
4280 if (!ret)
4281 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4282 if (ret)
4283 dev_err(hba->dev,
4284 "Host controller enable failed with non-hce\n");
4285 }
4286 } else {
4287 ret = ufshcd_hba_execute_hce(hba);
4288 }
4289
4290 return ret;
4291}
4292static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4293{
4294 int tx_lanes, i, err = 0;
4295
4296 if (!peer)
4297 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4298 &tx_lanes);
4299 else
4300 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4301 &tx_lanes);
4302 for (i = 0; i < tx_lanes; i++) {
4303 if (!peer)
4304 err = ufshcd_dme_set(hba,
4305 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4306 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4307 0);
4308 else
4309 err = ufshcd_dme_peer_set(hba,
4310 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4311 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4312 0);
4313 if (err) {
4314 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4315 __func__, peer, i, err);
4316 break;
4317 }
4318 }
4319
4320 return err;
4321}
4322
4323static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4324{
4325 return ufshcd_disable_tx_lcc(hba, true);
4326}
4327
4328
4329
4330
4331
4332
4333
4334static int ufshcd_link_startup(struct ufs_hba *hba)
4335{
4336 int ret;
4337 int retries = DME_LINKSTARTUP_RETRIES;
4338 bool link_startup_again = false;
4339
4340
4341
4342
4343
4344 if (!ufshcd_is_ufs_dev_active(hba))
4345 link_startup_again = true;
4346
4347link_startup:
4348 do {
4349 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4350
4351 ret = ufshcd_dme_link_startup(hba);
4352
4353
4354 if (!ret && !ufshcd_is_device_present(hba)) {
4355 dev_err(hba->dev, "%s: Device not present\n", __func__);
4356 ret = -ENXIO;
4357 goto out;
4358 }
4359
4360
4361
4362
4363
4364
4365 if (ret && ufshcd_hba_enable(hba))
4366 goto out;
4367 } while (ret && retries--);
4368
4369 if (ret)
4370
4371 goto out;
4372
4373 if (link_startup_again) {
4374 link_startup_again = false;
4375 retries = DME_LINKSTARTUP_RETRIES;
4376 goto link_startup;
4377 }
4378
4379
4380 ufshcd_init_pwr_info(hba);
4381 ufshcd_print_pwr_info(hba);
4382
4383 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4384 ret = ufshcd_disable_device_tx_lcc(hba);
4385 if (ret)
4386 goto out;
4387 }
4388
4389
4390 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4391 if (ret)
4392 goto out;
4393
4394 ret = ufshcd_make_hba_operational(hba);
4395out:
4396 if (ret) {
4397 dev_err(hba->dev, "link startup failed %d\n", ret);
4398 ufshcd_print_host_state(hba);
4399 ufshcd_print_pwr_info(hba);
4400 ufshcd_print_host_regs(hba);
4401 }
4402 return ret;
4403}
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4416{
4417 int err = 0;
4418 int retries;
4419
4420 ufshcd_hold(hba, false);
4421 mutex_lock(&hba->dev_cmd.lock);
4422 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4423 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4424 NOP_OUT_TIMEOUT);
4425
4426 if (!err || err == -ETIMEDOUT)
4427 break;
4428
4429 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4430 }
4431 mutex_unlock(&hba->dev_cmd.lock);
4432 ufshcd_release(hba);
4433
4434 if (err)
4435 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4436 return err;
4437}
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4449{
4450 int ret = 0;
4451 u8 lun_qdepth;
4452 struct ufs_hba *hba;
4453
4454 hba = shost_priv(sdev->host);
4455
4456 lun_qdepth = hba->nutrs;
4457 ret = ufshcd_read_unit_desc_param(hba,
4458 ufshcd_scsi_to_upiu_lun(sdev->lun),
4459 UNIT_DESC_PARAM_LU_Q_DEPTH,
4460 &lun_qdepth,
4461 sizeof(lun_qdepth));
4462
4463
4464 if (ret == -EOPNOTSUPP)
4465 lun_qdepth = 1;
4466 else if (!lun_qdepth)
4467
4468 lun_qdepth = hba->nutrs;
4469 else
4470 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4471
4472 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4473 __func__, lun_qdepth);
4474 scsi_change_queue_depth(sdev, lun_qdepth);
4475}
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4489 u8 lun,
4490 u8 *b_lu_write_protect)
4491{
4492 int ret;
4493
4494 if (!b_lu_write_protect)
4495 ret = -EINVAL;
4496
4497
4498
4499
4500
4501 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4502 ret = -ENOTSUPP;
4503 else
4504 ret = ufshcd_read_unit_desc_param(hba,
4505 lun,
4506 UNIT_DESC_PARAM_LU_WR_PROTECT,
4507 b_lu_write_protect,
4508 sizeof(*b_lu_write_protect));
4509 return ret;
4510}
4511
4512
4513
4514
4515
4516
4517
4518
4519static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4520 struct scsi_device *sdev)
4521{
4522 if (hba->dev_info.f_power_on_wp_en &&
4523 !hba->dev_info.is_lu_power_on_wp) {
4524 u8 b_lu_write_protect;
4525
4526 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4527 &b_lu_write_protect) &&
4528 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4529 hba->dev_info.is_lu_power_on_wp = true;
4530 }
4531}
4532
4533
4534
4535
4536
4537
4538
4539static int ufshcd_slave_alloc(struct scsi_device *sdev)
4540{
4541 struct ufs_hba *hba;
4542
4543 hba = shost_priv(sdev->host);
4544
4545
4546 sdev->use_10_for_ms = 1;
4547
4548
4549 sdev->allow_restart = 1;
4550
4551
4552 sdev->no_report_opcodes = 1;
4553
4554
4555 sdev->no_write_same = 1;
4556
4557 ufshcd_set_queue_depth(sdev);
4558
4559 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4560
4561 return 0;
4562}
4563
4564
4565
4566
4567
4568
4569
4570
4571static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4572{
4573 struct ufs_hba *hba = shost_priv(sdev->host);
4574
4575 if (depth > hba->nutrs)
4576 depth = hba->nutrs;
4577 return scsi_change_queue_depth(sdev, depth);
4578}
4579
4580
4581
4582
4583
4584static int ufshcd_slave_configure(struct scsi_device *sdev)
4585{
4586 struct request_queue *q = sdev->request_queue;
4587
4588 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4589 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4590
4591 return 0;
4592}
4593
4594
4595
4596
4597
4598static void ufshcd_slave_destroy(struct scsi_device *sdev)
4599{
4600 struct ufs_hba *hba;
4601
4602 hba = shost_priv(sdev->host);
4603
4604 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4605 unsigned long flags;
4606
4607 spin_lock_irqsave(hba->host->host_lock, flags);
4608 hba->sdev_ufs_device = NULL;
4609 spin_unlock_irqrestore(hba->host->host_lock, flags);
4610 }
4611}
4612
4613
4614
4615
4616
4617
4618
4619
4620static inline int
4621ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4622{
4623 int result = 0;
4624
4625 switch (scsi_status) {
4626 case SAM_STAT_CHECK_CONDITION:
4627 ufshcd_copy_sense_data(lrbp);
4628
4629 case SAM_STAT_GOOD:
4630 result |= DID_OK << 16 |
4631 COMMAND_COMPLETE << 8 |
4632 scsi_status;
4633 break;
4634 case SAM_STAT_TASK_SET_FULL:
4635 case SAM_STAT_BUSY:
4636 case SAM_STAT_TASK_ABORTED:
4637 ufshcd_copy_sense_data(lrbp);
4638 result |= scsi_status;
4639 break;
4640 default:
4641 result |= DID_ERROR << 16;
4642 break;
4643 }
4644
4645 return result;
4646}
4647
4648
4649
4650
4651
4652
4653
4654
4655static inline int
4656ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4657{
4658 int result = 0;
4659 int scsi_status;
4660 int ocs;
4661
4662
4663 ocs = ufshcd_get_tr_ocs(lrbp);
4664
4665 switch (ocs) {
4666 case OCS_SUCCESS:
4667 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
4668 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
4669 switch (result) {
4670 case UPIU_TRANSACTION_RESPONSE:
4671
4672
4673
4674
4675 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4676
4677
4678
4679
4680
4681 scsi_status = result & MASK_SCSI_STATUS;
4682 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696 if (!hba->pm_op_in_progress &&
4697 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
4698 schedule_work(&hba->eeh_work);
4699 break;
4700 case UPIU_TRANSACTION_REJECT_UPIU:
4701
4702 result = DID_ERROR << 16;
4703 dev_err(hba->dev,
4704 "Reject UPIU not fully implemented\n");
4705 break;
4706 default:
4707 result = DID_ERROR << 16;
4708 dev_err(hba->dev,
4709 "Unexpected request response code = %x\n",
4710 result);
4711 break;
4712 }
4713 break;
4714 case OCS_ABORTED:
4715 result |= DID_ABORT << 16;
4716 break;
4717 case OCS_INVALID_COMMAND_STATUS:
4718 result |= DID_REQUEUE << 16;
4719 break;
4720 case OCS_INVALID_CMD_TABLE_ATTR:
4721 case OCS_INVALID_PRDT_ATTR:
4722 case OCS_MISMATCH_DATA_BUF_SIZE:
4723 case OCS_MISMATCH_RESP_UPIU_SIZE:
4724 case OCS_PEER_COMM_FAILURE:
4725 case OCS_FATAL_ERROR:
4726 default:
4727 result |= DID_ERROR << 16;
4728 dev_err(hba->dev,
4729 "OCS error from controller = %x for tag %d\n",
4730 ocs, lrbp->task_tag);
4731 ufshcd_print_host_regs(hba);
4732 ufshcd_print_host_state(hba);
4733 break;
4734 }
4735
4736 if (host_byte(result) != DID_OK)
4737 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
4738 return result;
4739}
4740
4741
4742
4743
4744
4745
4746static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
4747{
4748 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
4749 hba->active_uic_cmd->argument2 |=
4750 ufshcd_get_uic_cmd_result(hba);
4751 hba->active_uic_cmd->argument3 =
4752 ufshcd_get_dme_attr_val(hba);
4753 complete(&hba->active_uic_cmd->done);
4754 }
4755
4756 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4757 complete(hba->uic_async_done);
4758}
4759
4760
4761
4762
4763
4764
4765static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4766 unsigned long completed_reqs)
4767{
4768 struct ufshcd_lrb *lrbp;
4769 struct scsi_cmnd *cmd;
4770 int result;
4771 int index;
4772
4773 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4774 lrbp = &hba->lrb[index];
4775 cmd = lrbp->cmd;
4776 if (cmd) {
4777 ufshcd_add_command_trace(hba, index, "complete");
4778 result = ufshcd_transfer_rsp_status(hba, lrbp);
4779 scsi_dma_unmap(cmd);
4780 cmd->result = result;
4781
4782 lrbp->cmd = NULL;
4783 clear_bit_unlock(index, &hba->lrb_in_use);
4784
4785 cmd->scsi_done(cmd);
4786 __ufshcd_release(hba);
4787 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4788 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
4789 if (hba->dev_cmd.complete) {
4790 ufshcd_add_command_trace(hba, index,
4791 "dev_complete");
4792 complete(hba->dev_cmd.complete);
4793 }
4794 }
4795 if (ufshcd_is_clkscaling_supported(hba))
4796 hba->clk_scaling.active_reqs--;
4797
4798 lrbp->compl_time_stamp = ktime_get();
4799 }
4800
4801
4802 hba->outstanding_reqs ^= completed_reqs;
4803
4804 ufshcd_clk_scaling_update_busy(hba);
4805
4806
4807 wake_up(&hba->dev_cmd.tag_wq);
4808}
4809
4810
4811
4812
4813
4814static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4815{
4816 unsigned long completed_reqs;
4817 u32 tr_doorbell;
4818
4819
4820
4821
4822
4823
4824
4825
4826 if (ufshcd_is_intr_aggr_allowed(hba) &&
4827 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
4828 ufshcd_reset_intr_aggr(hba);
4829
4830 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4831 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4832
4833 __ufshcd_transfer_req_compl(hba, completed_reqs);
4834}
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4847{
4848 int err = 0;
4849 u32 val;
4850
4851 if (!(hba->ee_ctrl_mask & mask))
4852 goto out;
4853
4854 val = hba->ee_ctrl_mask & ~mask;
4855 val &= MASK_EE_STATUS;
4856 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4857 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4858 if (!err)
4859 hba->ee_ctrl_mask &= ~mask;
4860out:
4861 return err;
4862}
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4875{
4876 int err = 0;
4877 u32 val;
4878
4879 if (hba->ee_ctrl_mask & mask)
4880 goto out;
4881
4882 val = hba->ee_ctrl_mask | mask;
4883 val &= MASK_EE_STATUS;
4884 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4885 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4886 if (!err)
4887 hba->ee_ctrl_mask |= mask;
4888out:
4889 return err;
4890}
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4904{
4905 int err = 0;
4906
4907 if (hba->auto_bkops_enabled)
4908 goto out;
4909
4910 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4911 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4912 if (err) {
4913 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4914 __func__, err);
4915 goto out;
4916 }
4917
4918 hba->auto_bkops_enabled = true;
4919 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
4920
4921
4922 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4923 if (err)
4924 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4925 __func__, err);
4926out:
4927 return err;
4928}
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4943{
4944 int err = 0;
4945
4946 if (!hba->auto_bkops_enabled)
4947 goto out;
4948
4949
4950
4951
4952
4953 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4954 if (err) {
4955 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4956 __func__, err);
4957 goto out;
4958 }
4959
4960 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
4961 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4962 if (err) {
4963 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4964 __func__, err);
4965 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4966 goto out;
4967 }
4968
4969 hba->auto_bkops_enabled = false;
4970 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
4971out:
4972 return err;
4973}
4974
4975
4976
4977
4978
4979
4980
4981
4982
4983
4984static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
4985{
4986 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4987 hba->auto_bkops_enabled = false;
4988 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4989 ufshcd_enable_auto_bkops(hba);
4990 } else {
4991 hba->auto_bkops_enabled = true;
4992 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4993 ufshcd_disable_auto_bkops(hba);
4994 }
4995}
4996
4997static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4998{
4999 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5000 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5001}
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5020 enum bkops_status status)
5021{
5022 int err;
5023 u32 curr_status = 0;
5024
5025 err = ufshcd_get_bkops_status(hba, &curr_status);
5026 if (err) {
5027 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5028 __func__, err);
5029 goto out;
5030 } else if (curr_status > BKOPS_STATUS_MAX) {
5031 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5032 __func__, curr_status);
5033 err = -EINVAL;
5034 goto out;
5035 }
5036
5037 if (curr_status >= status)
5038 err = ufshcd_enable_auto_bkops(hba);
5039 else
5040 err = ufshcd_disable_auto_bkops(hba);
5041out:
5042 return err;
5043}
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5056{
5057 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5058}
5059
5060static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5061{
5062 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5063 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5064}
5065
5066static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5067{
5068 int err;
5069 u32 curr_status = 0;
5070
5071 if (hba->is_urgent_bkops_lvl_checked)
5072 goto enable_auto_bkops;
5073
5074 err = ufshcd_get_bkops_status(hba, &curr_status);
5075 if (err) {
5076 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5077 __func__, err);
5078 goto out;
5079 }
5080
5081
5082
5083
5084
5085
5086
5087 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5088 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5089 __func__, curr_status);
5090
5091 hba->urgent_bkops_lvl = curr_status;
5092 hba->is_urgent_bkops_lvl_checked = true;
5093 }
5094
5095enable_auto_bkops:
5096 err = ufshcd_enable_auto_bkops(hba);
5097out:
5098 if (err < 0)
5099 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5100 __func__, err);
5101}
5102
5103
5104
5105
5106
5107
5108
5109
5110static void ufshcd_exception_event_handler(struct work_struct *work)
5111{
5112 struct ufs_hba *hba;
5113 int err;
5114 u32 status = 0;
5115 hba = container_of(work, struct ufs_hba, eeh_work);
5116
5117 pm_runtime_get_sync(hba->dev);
5118 scsi_block_requests(hba->host);
5119 err = ufshcd_get_ee_status(hba, &status);
5120 if (err) {
5121 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5122 __func__, err);
5123 goto out;
5124 }
5125
5126 status &= hba->ee_ctrl_mask;
5127
5128 if (status & MASK_EE_URGENT_BKOPS)
5129 ufshcd_bkops_exception_event_handler(hba);
5130
5131out:
5132 scsi_unblock_requests(hba->host);
5133 pm_runtime_put_sync(hba->dev);
5134 return;
5135}
5136
5137
5138static void ufshcd_complete_requests(struct ufs_hba *hba)
5139{
5140 ufshcd_transfer_req_compl(hba);
5141 ufshcd_tmc_handler(hba);
5142}
5143
5144
5145
5146
5147
5148
5149
5150
5151static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5152{
5153 unsigned long flags;
5154 bool err_handling = true;
5155
5156 spin_lock_irqsave(hba->host->host_lock, flags);
5157
5158
5159
5160
5161 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5162 goto out;
5163
5164 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5165 ((hba->saved_err & UIC_ERROR) &&
5166 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5167 goto out;
5168
5169 if ((hba->saved_err & UIC_ERROR) &&
5170 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5171 int err;
5172
5173
5174
5175 spin_unlock_irqrestore(hba->host->host_lock, flags);
5176 msleep(50);
5177 spin_lock_irqsave(hba->host->host_lock, flags);
5178
5179
5180
5181
5182
5183 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5184 ((hba->saved_err & UIC_ERROR) &&
5185 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5186 goto out;
5187
5188
5189
5190
5191
5192
5193
5194
5195 spin_unlock_irqrestore(hba->host->host_lock, flags);
5196 err = ufshcd_verify_dev_init(hba);
5197 spin_lock_irqsave(hba->host->host_lock, flags);
5198
5199 if (err)
5200 goto out;
5201
5202
5203 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5204 hba->saved_err &= ~UIC_ERROR;
5205
5206 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5207 if (!hba->saved_uic_err) {
5208 err_handling = false;
5209 goto out;
5210 }
5211 }
5212out:
5213 spin_unlock_irqrestore(hba->host->host_lock, flags);
5214 return err_handling;
5215}
5216
5217
5218
5219
5220
5221static void ufshcd_err_handler(struct work_struct *work)
5222{
5223 struct ufs_hba *hba;
5224 unsigned long flags;
5225 u32 err_xfer = 0;
5226 u32 err_tm = 0;
5227 int err = 0;
5228 int tag;
5229 bool needs_reset = false;
5230
5231 hba = container_of(work, struct ufs_hba, eh_work);
5232
5233 pm_runtime_get_sync(hba->dev);
5234 ufshcd_hold(hba, false);
5235
5236 spin_lock_irqsave(hba->host->host_lock, flags);
5237 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
5238 goto out;
5239
5240 hba->ufshcd_state = UFSHCD_STATE_RESET;
5241 ufshcd_set_eh_in_progress(hba);
5242
5243
5244 ufshcd_complete_requests(hba);
5245
5246 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5247 bool ret;
5248
5249 spin_unlock_irqrestore(hba->host->host_lock, flags);
5250
5251 ret = ufshcd_quirk_dl_nac_errors(hba);
5252 spin_lock_irqsave(hba->host->host_lock, flags);
5253 if (!ret)
5254 goto skip_err_handling;
5255 }
5256 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5257 ((hba->saved_err & UIC_ERROR) &&
5258 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5259 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5260 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5261 needs_reset = true;
5262
5263
5264
5265
5266
5267
5268 if (needs_reset)
5269 goto skip_pending_xfer_clear;
5270
5271
5272 spin_unlock_irqrestore(hba->host->host_lock, flags);
5273
5274 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5275 if (ufshcd_clear_cmd(hba, tag)) {
5276 err_xfer = true;
5277 goto lock_skip_pending_xfer_clear;
5278 }
5279 }
5280
5281
5282 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5283 if (ufshcd_clear_tm_cmd(hba, tag)) {
5284 err_tm = true;
5285 goto lock_skip_pending_xfer_clear;
5286 }
5287 }
5288
5289lock_skip_pending_xfer_clear:
5290 spin_lock_irqsave(hba->host->host_lock, flags);
5291
5292
5293 ufshcd_complete_requests(hba);
5294
5295 if (err_xfer || err_tm)
5296 needs_reset = true;
5297
5298skip_pending_xfer_clear:
5299
5300 if (needs_reset) {
5301 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5302
5303
5304
5305
5306
5307
5308
5309
5310 if (hba->outstanding_reqs == max_doorbells)
5311 __ufshcd_transfer_req_compl(hba,
5312 (1UL << (hba->nutrs - 1)));
5313
5314 spin_unlock_irqrestore(hba->host->host_lock, flags);
5315 err = ufshcd_reset_and_restore(hba);
5316 spin_lock_irqsave(hba->host->host_lock, flags);
5317 if (err) {
5318 dev_err(hba->dev, "%s: reset and restore failed\n",
5319 __func__);
5320 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5321 }
5322
5323
5324
5325
5326 scsi_report_bus_reset(hba->host, 0);
5327 hba->saved_err = 0;
5328 hba->saved_uic_err = 0;
5329 }
5330
5331skip_err_handling:
5332 if (!needs_reset) {
5333 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5334 if (hba->saved_err || hba->saved_uic_err)
5335 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5336 __func__, hba->saved_err, hba->saved_uic_err);
5337 }
5338
5339 ufshcd_clear_eh_in_progress(hba);
5340
5341out:
5342 spin_unlock_irqrestore(hba->host->host_lock, flags);
5343 ufshcd_scsi_unblock_requests(hba);
5344 ufshcd_release(hba);
5345 pm_runtime_put_sync(hba->dev);
5346}
5347
5348static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5349 u32 reg)
5350{
5351 reg_hist->reg[reg_hist->pos] = reg;
5352 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5353 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5354}
5355
5356
5357
5358
5359
5360static void ufshcd_update_uic_error(struct ufs_hba *hba)
5361{
5362 u32 reg;
5363
5364
5365 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5366
5367 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
5368 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
5369
5370
5371
5372
5373 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
5374 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5375 }
5376
5377
5378 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
5379 if (reg)
5380 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5381
5382 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5383 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
5384 else if (hba->dev_quirks &
5385 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5386 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5387 hba->uic_error |=
5388 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5389 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5390 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5391 }
5392
5393
5394 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
5395 if (reg) {
5396 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
5397 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
5398 }
5399
5400 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
5401 if (reg) {
5402 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
5403 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
5404 }
5405
5406 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
5407 if (reg) {
5408 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
5409 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
5410 }
5411
5412 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5413 __func__, hba->uic_error);
5414}
5415
5416
5417
5418
5419
5420static void ufshcd_check_errors(struct ufs_hba *hba)
5421{
5422 bool queue_eh_work = false;
5423
5424 if (hba->errors & INT_FATAL_ERRORS)
5425 queue_eh_work = true;
5426
5427 if (hba->errors & UIC_ERROR) {
5428 hba->uic_error = 0;
5429 ufshcd_update_uic_error(hba);
5430 if (hba->uic_error)
5431 queue_eh_work = true;
5432 }
5433
5434 if (queue_eh_work) {
5435
5436
5437
5438
5439 hba->saved_err |= hba->errors;
5440 hba->saved_uic_err |= hba->uic_error;
5441
5442
5443 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5444
5445 ufshcd_scsi_block_requests(hba);
5446
5447 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
5448
5449
5450 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5451 bool pr_prdt = !!(hba->saved_err &
5452 SYSTEM_BUS_FATAL_ERROR);
5453
5454 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5455 __func__, hba->saved_err,
5456 hba->saved_uic_err);
5457
5458 ufshcd_print_host_regs(hba);
5459 ufshcd_print_pwr_info(hba);
5460 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5461 ufshcd_print_trs(hba, hba->outstanding_reqs,
5462 pr_prdt);
5463 }
5464 schedule_work(&hba->eh_work);
5465 }
5466 }
5467
5468
5469
5470
5471
5472
5473}
5474
5475
5476
5477
5478
5479static void ufshcd_tmc_handler(struct ufs_hba *hba)
5480{
5481 u32 tm_doorbell;
5482
5483 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
5484 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
5485 wake_up(&hba->tm_wq);
5486}
5487
5488
5489
5490
5491
5492
5493static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5494{
5495 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5496 if (hba->errors)
5497 ufshcd_check_errors(hba);
5498
5499 if (intr_status & UFSHCD_UIC_MASK)
5500 ufshcd_uic_cmd_compl(hba, intr_status);
5501
5502 if (intr_status & UTP_TASK_REQ_COMPL)
5503 ufshcd_tmc_handler(hba);
5504
5505 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5506 ufshcd_transfer_req_compl(hba);
5507}
5508
5509
5510
5511
5512
5513
5514
5515
5516
5517static irqreturn_t ufshcd_intr(int irq, void *__hba)
5518{
5519 u32 intr_status, enabled_intr_status;
5520 irqreturn_t retval = IRQ_NONE;
5521 struct ufs_hba *hba = __hba;
5522 int retries = hba->nutrs;
5523
5524 spin_lock(hba->host->host_lock);
5525 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5526
5527
5528
5529
5530
5531
5532
5533 do {
5534 enabled_intr_status =
5535 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
5536 if (intr_status)
5537 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
5538 if (enabled_intr_status) {
5539 ufshcd_sl_intr(hba, enabled_intr_status);
5540 retval = IRQ_HANDLED;
5541 }
5542
5543 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
5544 } while (intr_status && --retries);
5545
5546 spin_unlock(hba->host->host_lock);
5547 return retval;
5548}
5549
5550static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5551{
5552 int err = 0;
5553 u32 mask = 1 << tag;
5554 unsigned long flags;
5555
5556 if (!test_bit(tag, &hba->outstanding_tasks))
5557 goto out;
5558
5559 spin_lock_irqsave(hba->host->host_lock, flags);
5560 ufshcd_utmrl_clear(hba, tag);
5561 spin_unlock_irqrestore(hba->host->host_lock, flags);
5562
5563
5564 err = ufshcd_wait_for_register(hba,
5565 REG_UTP_TASK_REQ_DOOR_BELL,
5566 mask, 0, 1000, 1000, true);
5567out:
5568 return err;
5569}
5570
5571static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
5572 struct utp_task_req_desc *treq, u8 tm_function)
5573{
5574 struct Scsi_Host *host = hba->host;
5575 unsigned long flags;
5576 int free_slot, task_tag, err;
5577
5578
5579
5580
5581
5582
5583 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
5584 ufshcd_hold(hba, false);
5585
5586 spin_lock_irqsave(host->host_lock, flags);
5587 task_tag = hba->nutrs + free_slot;
5588
5589 treq->req_header.dword_0 |= cpu_to_be32(task_tag);
5590
5591 memcpy(hba->utmrdl_base_addr + free_slot, treq, sizeof(*treq));
5592 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5593
5594
5595 __set_bit(free_slot, &hba->outstanding_tasks);
5596
5597
5598 wmb();
5599
5600 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
5601
5602 wmb();
5603
5604 spin_unlock_irqrestore(host->host_lock, flags);
5605
5606 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_send");
5607
5608
5609 err = wait_event_timeout(hba->tm_wq,
5610 test_bit(free_slot, &hba->tm_condition),
5611 msecs_to_jiffies(TM_CMD_TIMEOUT));
5612 if (!err) {
5613 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete_err");
5614 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5615 __func__, tm_function);
5616 if (ufshcd_clear_tm_cmd(hba, free_slot))
5617 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5618 __func__, free_slot);
5619 err = -ETIMEDOUT;
5620 } else {
5621 err = 0;
5622 memcpy(treq, hba->utmrdl_base_addr + free_slot, sizeof(*treq));
5623
5624 ufshcd_add_tm_upiu_trace(hba, task_tag, "tm_complete");
5625
5626 spin_lock_irqsave(hba->host->host_lock, flags);
5627 __clear_bit(free_slot, &hba->outstanding_tasks);
5628 spin_unlock_irqrestore(hba->host->host_lock, flags);
5629
5630 }
5631
5632 clear_bit(free_slot, &hba->tm_condition);
5633 ufshcd_put_tm_slot(hba, free_slot);
5634 wake_up(&hba->tm_tag_wq);
5635
5636 ufshcd_release(hba);
5637 return err;
5638}
5639
5640
5641
5642
5643
5644
5645
5646
5647
5648
5649
5650static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5651 u8 tm_function, u8 *tm_response)
5652{
5653 struct utp_task_req_desc treq = { { 0 }, };
5654 int ocs_value, err;
5655
5656
5657 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5658 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5659
5660
5661 treq.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
5662 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
5663 treq.req_header.dword_1 = cpu_to_be32(tm_function << 16);
5664
5665
5666
5667
5668
5669 treq.input_param1 = cpu_to_be32(lun_id);
5670 treq.input_param2 = cpu_to_be32(task_id);
5671
5672 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
5673 if (err == -ETIMEDOUT)
5674 return err;
5675
5676 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5677 if (ocs_value != OCS_SUCCESS)
5678 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
5679 __func__, ocs_value);
5680 else if (tm_response)
5681 *tm_response = be32_to_cpu(treq.output_param1) &
5682 MASK_TM_SERVICE_RESP;
5683 return err;
5684}
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
5704 struct utp_upiu_req *req_upiu,
5705 struct utp_upiu_req *rsp_upiu,
5706 u8 *desc_buff, int *buff_len,
5707 int cmd_type,
5708 enum query_opcode desc_op)
5709{
5710 struct ufshcd_lrb *lrbp;
5711 int err = 0;
5712 int tag;
5713 struct completion wait;
5714 unsigned long flags;
5715 u32 upiu_flags;
5716
5717 down_read(&hba->clk_scaling_lock);
5718
5719 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
5720
5721 init_completion(&wait);
5722 lrbp = &hba->lrb[tag];
5723 WARN_ON(lrbp->cmd);
5724
5725 lrbp->cmd = NULL;
5726 lrbp->sense_bufflen = 0;
5727 lrbp->sense_buffer = NULL;
5728 lrbp->task_tag = tag;
5729 lrbp->lun = 0;
5730 lrbp->intr_cmd = true;
5731 hba->dev_cmd.type = cmd_type;
5732
5733 switch (hba->ufs_version) {
5734 case UFSHCI_VERSION_10:
5735 case UFSHCI_VERSION_11:
5736 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
5737 break;
5738 default:
5739 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
5740 break;
5741 }
5742
5743
5744 req_upiu->header.dword_0 |= cpu_to_be32(tag);
5745
5746 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
5747
5748
5749 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
5750 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
5751
5752
5753
5754
5755 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
5756 *buff_len = 0;
5757 }
5758
5759 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5760
5761 hba->dev_cmd.complete = &wait;
5762
5763
5764 wmb();
5765 spin_lock_irqsave(hba->host->host_lock, flags);
5766 ufshcd_send_command(hba, tag);
5767 spin_unlock_irqrestore(hba->host->host_lock, flags);
5768
5769
5770
5771
5772
5773
5774 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
5775
5776
5777 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
5778 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
5779 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
5780 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
5781 MASK_QUERY_DATA_SEG_LEN;
5782
5783 if (*buff_len >= resp_len) {
5784 memcpy(desc_buff, descp, resp_len);
5785 *buff_len = resp_len;
5786 } else {
5787 dev_warn(hba->dev, "rsp size is bigger than buffer");
5788 *buff_len = 0;
5789 err = -EINVAL;
5790 }
5791 }
5792
5793 ufshcd_put_dev_cmd_tag(hba, tag);
5794 wake_up(&hba->dev_cmd.tag_wq);
5795 up_read(&hba->clk_scaling_lock);
5796 return err;
5797}
5798
5799
5800
5801
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
5815 struct utp_upiu_req *req_upiu,
5816 struct utp_upiu_req *rsp_upiu,
5817 int msgcode,
5818 u8 *desc_buff, int *buff_len,
5819 enum query_opcode desc_op)
5820{
5821 int err;
5822 int cmd_type = DEV_CMD_TYPE_QUERY;
5823 struct utp_task_req_desc treq = { { 0 }, };
5824 int ocs_value;
5825 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
5826
5827 switch (msgcode) {
5828 case UPIU_TRANSACTION_NOP_OUT:
5829 cmd_type = DEV_CMD_TYPE_NOP;
5830
5831 case UPIU_TRANSACTION_QUERY_REQ:
5832 ufshcd_hold(hba, false);
5833 mutex_lock(&hba->dev_cmd.lock);
5834 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
5835 desc_buff, buff_len,
5836 cmd_type, desc_op);
5837 mutex_unlock(&hba->dev_cmd.lock);
5838 ufshcd_release(hba);
5839
5840 break;
5841 case UPIU_TRANSACTION_TASK_REQ:
5842 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5843 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5844
5845 memcpy(&treq.req_header, req_upiu, sizeof(*req_upiu));
5846
5847 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
5848 if (err == -ETIMEDOUT)
5849 break;
5850
5851 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
5852 if (ocs_value != OCS_SUCCESS) {
5853 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
5854 ocs_value);
5855 break;
5856 }
5857
5858 memcpy(rsp_upiu, &treq.rsp_header, sizeof(*rsp_upiu));
5859
5860 break;
5861 default:
5862 err = -EINVAL;
5863
5864 break;
5865 }
5866
5867 return err;
5868}
5869
5870
5871
5872
5873
5874
5875
5876
5877static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
5878{
5879 struct Scsi_Host *host;
5880 struct ufs_hba *hba;
5881 unsigned int tag;
5882 u32 pos;
5883 int err;
5884 u8 resp = 0xF;
5885 struct ufshcd_lrb *lrbp;
5886 unsigned long flags;
5887
5888 host = cmd->device->host;
5889 hba = shost_priv(host);
5890 tag = cmd->request->tag;
5891
5892 lrbp = &hba->lrb[tag];
5893 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5894 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
5895 if (!err)
5896 err = resp;
5897 goto out;
5898 }
5899
5900
5901 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5902 if (hba->lrb[pos].lun == lrbp->lun) {
5903 err = ufshcd_clear_cmd(hba, pos);
5904 if (err)
5905 break;
5906 }
5907 }
5908 spin_lock_irqsave(host->host_lock, flags);
5909 ufshcd_transfer_req_compl(hba);
5910 spin_unlock_irqrestore(host->host_lock, flags);
5911
5912out:
5913 hba->req_abort_count = 0;
5914 if (!err) {
5915 err = SUCCESS;
5916 } else {
5917 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5918 err = FAILED;
5919 }
5920 return err;
5921}
5922
5923static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5924{
5925 struct ufshcd_lrb *lrbp;
5926 int tag;
5927
5928 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5929 lrbp = &hba->lrb[tag];
5930 lrbp->req_abort_skip = true;
5931 }
5932}
5933
5934
5935
5936
5937
5938
5939
5940
5941
5942
5943
5944
5945
5946static int ufshcd_abort(struct scsi_cmnd *cmd)
5947{
5948 struct Scsi_Host *host;
5949 struct ufs_hba *hba;
5950 unsigned long flags;
5951 unsigned int tag;
5952 int err = 0;
5953 int poll_cnt;
5954 u8 resp = 0xF;
5955 struct ufshcd_lrb *lrbp;
5956 u32 reg;
5957
5958 host = cmd->device->host;
5959 hba = shost_priv(host);
5960 tag = cmd->request->tag;
5961 lrbp = &hba->lrb[tag];
5962 if (!ufshcd_valid_tag(hba, tag)) {
5963 dev_err(hba->dev,
5964 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5965 __func__, tag, cmd, cmd->request);
5966 BUG();
5967 }
5968
5969
5970
5971
5972
5973
5974
5975
5976 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5977 return ufshcd_eh_host_reset_handler(cmd);
5978
5979 ufshcd_hold(hba, false);
5980 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5981
5982 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5983 dev_err(hba->dev,
5984 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5985 __func__, tag, hba->outstanding_reqs, reg);
5986 goto out;
5987 }
5988
5989 if (!(reg & (1 << tag))) {
5990 dev_err(hba->dev,
5991 "%s: cmd was completed, but without a notifying intr, tag = %d",
5992 __func__, tag);
5993 }
5994
5995
5996 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
5997
5998
5999
6000
6001
6002
6003
6004
6005 scsi_print_command(hba->lrb[tag].cmd);
6006 if (!hba->req_abort_count) {
6007 ufshcd_print_host_regs(hba);
6008 ufshcd_print_host_state(hba);
6009 ufshcd_print_pwr_info(hba);
6010 ufshcd_print_trs(hba, 1 << tag, true);
6011 } else {
6012 ufshcd_print_trs(hba, 1 << tag, false);
6013 }
6014 hba->req_abort_count++;
6015
6016
6017 if (lrbp->req_abort_skip) {
6018 err = -EIO;
6019 goto out;
6020 }
6021
6022 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6023 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6024 UFS_QUERY_TASK, &resp);
6025 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6026
6027 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6028 __func__, tag);
6029 break;
6030 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6031
6032
6033
6034
6035 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6036 __func__, tag);
6037 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6038 if (reg & (1 << tag)) {
6039
6040 usleep_range(100, 200);
6041 continue;
6042 }
6043
6044 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6045 __func__, tag);
6046 goto out;
6047 } else {
6048 dev_err(hba->dev,
6049 "%s: no response from device. tag = %d, err %d\n",
6050 __func__, tag, err);
6051 if (!err)
6052 err = resp;
6053 goto out;
6054 }
6055 }
6056
6057 if (!poll_cnt) {
6058 err = -EBUSY;
6059 goto out;
6060 }
6061
6062 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6063 UFS_ABORT_TASK, &resp);
6064 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6065 if (!err) {
6066 err = resp;
6067 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6068 __func__, tag, err);
6069 }
6070 goto out;
6071 }
6072
6073 err = ufshcd_clear_cmd(hba, tag);
6074 if (err) {
6075 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6076 __func__, tag, err);
6077 goto out;
6078 }
6079
6080 scsi_dma_unmap(cmd);
6081
6082 spin_lock_irqsave(host->host_lock, flags);
6083 ufshcd_outstanding_req_clear(hba, tag);
6084 hba->lrb[tag].cmd = NULL;
6085 spin_unlock_irqrestore(host->host_lock, flags);
6086
6087 clear_bit_unlock(tag, &hba->lrb_in_use);
6088 wake_up(&hba->dev_cmd.tag_wq);
6089
6090out:
6091 if (!err) {
6092 err = SUCCESS;
6093 } else {
6094 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
6095 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
6096 err = FAILED;
6097 }
6098
6099
6100
6101
6102
6103 ufshcd_release(hba);
6104 return err;
6105}
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6118{
6119 int err;
6120 unsigned long flags;
6121
6122
6123 spin_lock_irqsave(hba->host->host_lock, flags);
6124 ufshcd_hba_stop(hba, false);
6125 spin_unlock_irqrestore(hba->host->host_lock, flags);
6126
6127
6128 ufshcd_scale_clks(hba, true);
6129
6130 err = ufshcd_hba_enable(hba);
6131 if (err)
6132 goto out;
6133
6134
6135 err = ufshcd_probe_hba(hba);
6136
6137 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
6138 err = -EIO;
6139out:
6140 if (err)
6141 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
6142
6143 return err;
6144}
6145
6146
6147
6148
6149
6150
6151
6152
6153
6154
6155static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6156{
6157 int err = 0;
6158 unsigned long flags;
6159 int retries = MAX_HOST_RESET_RETRIES;
6160
6161 do {
6162 err = ufshcd_host_reset_and_restore(hba);
6163 } while (err && --retries);
6164
6165
6166
6167
6168
6169 spin_lock_irqsave(hba->host->host_lock, flags);
6170 ufshcd_transfer_req_compl(hba);
6171 ufshcd_tmc_handler(hba);
6172 spin_unlock_irqrestore(hba->host->host_lock, flags);
6173
6174 return err;
6175}
6176
6177
6178
6179
6180
6181
6182
6183static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6184{
6185 int err;
6186 unsigned long flags;
6187 struct ufs_hba *hba;
6188
6189 hba = shost_priv(cmd->device->host);
6190
6191 ufshcd_hold(hba, false);
6192
6193
6194
6195
6196
6197
6198 do {
6199 spin_lock_irqsave(hba->host->host_lock, flags);
6200 if (!(work_pending(&hba->eh_work) ||
6201 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6202 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
6203 break;
6204 spin_unlock_irqrestore(hba->host->host_lock, flags);
6205 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
6206 flush_work(&hba->eh_work);
6207 } while (1);
6208
6209 hba->ufshcd_state = UFSHCD_STATE_RESET;
6210 ufshcd_set_eh_in_progress(hba);
6211 spin_unlock_irqrestore(hba->host->host_lock, flags);
6212
6213 err = ufshcd_reset_and_restore(hba);
6214
6215 spin_lock_irqsave(hba->host->host_lock, flags);
6216 if (!err) {
6217 err = SUCCESS;
6218 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6219 } else {
6220 err = FAILED;
6221 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6222 }
6223 ufshcd_clear_eh_in_progress(hba);
6224 spin_unlock_irqrestore(hba->host->host_lock, flags);
6225
6226 ufshcd_release(hba);
6227 return err;
6228}
6229
6230
6231
6232
6233
6234
6235
6236
6237
6238static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6239{
6240 int i;
6241 int curr_uA;
6242 u16 data;
6243 u16 unit;
6244
6245 for (i = start_scan; i >= 0; i--) {
6246 data = be16_to_cpup((__be16 *)&buff[2 * i]);
6247 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6248 ATTR_ICC_LVL_UNIT_OFFSET;
6249 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6250 switch (unit) {
6251 case UFSHCD_NANO_AMP:
6252 curr_uA = curr_uA / 1000;
6253 break;
6254 case UFSHCD_MILI_AMP:
6255 curr_uA = curr_uA * 1000;
6256 break;
6257 case UFSHCD_AMP:
6258 curr_uA = curr_uA * 1000 * 1000;
6259 break;
6260 case UFSHCD_MICRO_AMP:
6261 default:
6262 break;
6263 }
6264 if (sup_curr_uA >= curr_uA)
6265 break;
6266 }
6267 if (i < 0) {
6268 i = 0;
6269 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6270 }
6271
6272 return (u32)i;
6273}
6274
6275
6276
6277
6278
6279
6280
6281
6282
6283
6284static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6285 u8 *desc_buf, int len)
6286{
6287 u32 icc_level = 0;
6288
6289 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6290 !hba->vreg_info.vccq2) {
6291 dev_err(hba->dev,
6292 "%s: Regulator capability was not set, actvIccLevel=%d",
6293 __func__, icc_level);
6294 goto out;
6295 }
6296
6297 if (hba->vreg_info.vcc)
6298 icc_level = ufshcd_get_max_icc_level(
6299 hba->vreg_info.vcc->max_uA,
6300 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6301 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6302
6303 if (hba->vreg_info.vccq)
6304 icc_level = ufshcd_get_max_icc_level(
6305 hba->vreg_info.vccq->max_uA,
6306 icc_level,
6307 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6308
6309 if (hba->vreg_info.vccq2)
6310 icc_level = ufshcd_get_max_icc_level(
6311 hba->vreg_info.vccq2->max_uA,
6312 icc_level,
6313 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6314out:
6315 return icc_level;
6316}
6317
6318static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6319{
6320 int ret;
6321 int buff_len = hba->desc_size.pwr_desc;
6322 u8 *desc_buf;
6323
6324 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6325 if (!desc_buf)
6326 return;
6327
6328 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6329 if (ret) {
6330 dev_err(hba->dev,
6331 "%s: Failed reading power descriptor.len = %d ret = %d",
6332 __func__, buff_len, ret);
6333 goto out;
6334 }
6335
6336 hba->init_prefetch_data.icc_level =
6337 ufshcd_find_max_sup_active_icc_level(hba,
6338 desc_buf, buff_len);
6339 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6340 __func__, hba->init_prefetch_data.icc_level);
6341
6342 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6343 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6344 &hba->init_prefetch_data.icc_level);
6345
6346 if (ret)
6347 dev_err(hba->dev,
6348 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6349 __func__, hba->init_prefetch_data.icc_level , ret);
6350
6351out:
6352 kfree(desc_buf);
6353}
6354
6355
6356
6357
6358
6359
6360
6361
6362
6363
6364
6365
6366
6367
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380
6381static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6382{
6383 int ret = 0;
6384 struct scsi_device *sdev_rpmb;
6385 struct scsi_device *sdev_boot;
6386
6387 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6388 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6389 if (IS_ERR(hba->sdev_ufs_device)) {
6390 ret = PTR_ERR(hba->sdev_ufs_device);
6391 hba->sdev_ufs_device = NULL;
6392 goto out;
6393 }
6394 scsi_device_put(hba->sdev_ufs_device);
6395
6396 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
6397 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
6398 if (IS_ERR(sdev_rpmb)) {
6399 ret = PTR_ERR(sdev_rpmb);
6400 goto remove_sdev_ufs_device;
6401 }
6402 scsi_device_put(sdev_rpmb);
6403
6404 sdev_boot = __scsi_add_device(hba->host, 0, 0,
6405 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
6406 if (IS_ERR(sdev_boot))
6407 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
6408 else
6409 scsi_device_put(sdev_boot);
6410 goto out;
6411
6412remove_sdev_ufs_device:
6413 scsi_remove_device(hba->sdev_ufs_device);
6414out:
6415 return ret;
6416}
6417
6418static int ufs_get_device_desc(struct ufs_hba *hba,
6419 struct ufs_dev_desc *dev_desc)
6420{
6421 int err;
6422 size_t buff_len;
6423 u8 model_index;
6424 u8 *desc_buf;
6425
6426 buff_len = max_t(size_t, hba->desc_size.dev_desc,
6427 QUERY_DESC_MAX_SIZE + 1);
6428 desc_buf = kmalloc(buff_len, GFP_KERNEL);
6429 if (!desc_buf) {
6430 err = -ENOMEM;
6431 goto out;
6432 }
6433
6434 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
6435 if (err) {
6436 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6437 __func__, err);
6438 goto out;
6439 }
6440
6441
6442
6443
6444
6445 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
6446 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6447
6448 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6449
6450
6451 memset(desc_buf, 0, buff_len);
6452
6453 err = ufshcd_read_string_desc(hba, model_index, desc_buf,
6454 QUERY_DESC_MAX_SIZE, true);
6455 if (err) {
6456 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6457 __func__, err);
6458 goto out;
6459 }
6460
6461 desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
6462 strlcpy(dev_desc->model, (desc_buf + QUERY_DESC_HDR_SIZE),
6463 min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
6464 MAX_MODEL_LEN));
6465
6466
6467 dev_desc->model[MAX_MODEL_LEN] = '\0';
6468
6469out:
6470 kfree(desc_buf);
6471 return err;
6472}
6473
6474static void ufs_fixup_device_setup(struct ufs_hba *hba,
6475 struct ufs_dev_desc *dev_desc)
6476{
6477 struct ufs_dev_fix *f;
6478
6479 for (f = ufs_fixups; f->quirk; f++) {
6480 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6481 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6482 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
6483 !strcmp(f->card.model, UFS_ANY_MODEL)))
6484 hba->dev_quirks |= f->quirk;
6485 }
6486}
6487
6488
6489
6490
6491
6492
6493
6494
6495
6496
6497
6498
6499static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6500{
6501 int ret = 0;
6502 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6503
6504 ret = ufshcd_dme_peer_get(hba,
6505 UIC_ARG_MIB_SEL(
6506 RX_MIN_ACTIVATETIME_CAPABILITY,
6507 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6508 &peer_rx_min_activatetime);
6509 if (ret)
6510 goto out;
6511
6512
6513 tuned_pa_tactivate =
6514 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6515 / PA_TACTIVATE_TIME_UNIT_US);
6516 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6517 tuned_pa_tactivate);
6518
6519out:
6520 return ret;
6521}
6522
6523
6524
6525
6526
6527
6528
6529
6530
6531
6532
6533
6534static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6535{
6536 int ret = 0;
6537 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6538 u32 max_hibern8_time, tuned_pa_hibern8time;
6539
6540 ret = ufshcd_dme_get(hba,
6541 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6542 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6543 &local_tx_hibern8_time_cap);
6544 if (ret)
6545 goto out;
6546
6547 ret = ufshcd_dme_peer_get(hba,
6548 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6549 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6550 &peer_rx_hibern8_time_cap);
6551 if (ret)
6552 goto out;
6553
6554 max_hibern8_time = max(local_tx_hibern8_time_cap,
6555 peer_rx_hibern8_time_cap);
6556
6557 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6558 / PA_HIBERN8_TIME_UNIT_US);
6559 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6560 tuned_pa_hibern8time);
6561out:
6562 return ret;
6563}
6564
6565
6566
6567
6568
6569
6570
6571
6572
6573
6574
6575
6576static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6577{
6578 int ret = 0;
6579 u32 granularity, peer_granularity;
6580 u32 pa_tactivate, peer_pa_tactivate;
6581 u32 pa_tactivate_us, peer_pa_tactivate_us;
6582 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6583
6584 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6585 &granularity);
6586 if (ret)
6587 goto out;
6588
6589 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6590 &peer_granularity);
6591 if (ret)
6592 goto out;
6593
6594 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6595 (granularity > PA_GRANULARITY_MAX_VAL)) {
6596 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6597 __func__, granularity);
6598 return -EINVAL;
6599 }
6600
6601 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6602 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6603 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6604 __func__, peer_granularity);
6605 return -EINVAL;
6606 }
6607
6608 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6609 if (ret)
6610 goto out;
6611
6612 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6613 &peer_pa_tactivate);
6614 if (ret)
6615 goto out;
6616
6617 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6618 peer_pa_tactivate_us = peer_pa_tactivate *
6619 gran_to_us_table[peer_granularity - 1];
6620
6621 if (pa_tactivate_us > peer_pa_tactivate_us) {
6622 u32 new_peer_pa_tactivate;
6623
6624 new_peer_pa_tactivate = pa_tactivate_us /
6625 gran_to_us_table[peer_granularity - 1];
6626 new_peer_pa_tactivate++;
6627 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6628 new_peer_pa_tactivate);
6629 }
6630
6631out:
6632 return ret;
6633}
6634
6635static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6636{
6637 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6638 ufshcd_tune_pa_tactivate(hba);
6639 ufshcd_tune_pa_hibern8time(hba);
6640 }
6641
6642 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6643
6644 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
6645
6646 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6647 ufshcd_quirk_tune_host_pa_tactivate(hba);
6648
6649 ufshcd_vops_apply_dev_quirks(hba);
6650}
6651
6652static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6653{
6654 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6655
6656 hba->ufs_stats.hibern8_exit_cnt = 0;
6657 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6658
6659 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6660 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6661 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6662 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6663 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
6664
6665 hba->req_abort_count = 0;
6666}
6667
6668static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6669{
6670 int err;
6671
6672 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6673 &hba->desc_size.dev_desc);
6674 if (err)
6675 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6676
6677 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6678 &hba->desc_size.pwr_desc);
6679 if (err)
6680 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6681
6682 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6683 &hba->desc_size.interc_desc);
6684 if (err)
6685 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6686
6687 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6688 &hba->desc_size.conf_desc);
6689 if (err)
6690 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6691
6692 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6693 &hba->desc_size.unit_desc);
6694 if (err)
6695 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6696
6697 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6698 &hba->desc_size.geom_desc);
6699 if (err)
6700 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6701 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
6702 &hba->desc_size.hlth_desc);
6703 if (err)
6704 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
6705}
6706
6707static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6708{
6709 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6710 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6711 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6712 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6713 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6714 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6715 hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
6716}
6717
6718static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
6719 {19200000, REF_CLK_FREQ_19_2_MHZ},
6720 {26000000, REF_CLK_FREQ_26_MHZ},
6721 {38400000, REF_CLK_FREQ_38_4_MHZ},
6722 {52000000, REF_CLK_FREQ_52_MHZ},
6723 {0, REF_CLK_FREQ_INVAL},
6724};
6725
6726static enum ufs_ref_clk_freq
6727ufs_get_bref_clk_from_hz(unsigned long freq)
6728{
6729 int i;
6730
6731 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
6732 if (ufs_ref_clk_freqs[i].freq_hz == freq)
6733 return ufs_ref_clk_freqs[i].val;
6734
6735 return REF_CLK_FREQ_INVAL;
6736}
6737
6738void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
6739{
6740 unsigned long freq;
6741
6742 freq = clk_get_rate(refclk);
6743
6744 hba->dev_ref_clk_freq =
6745 ufs_get_bref_clk_from_hz(freq);
6746
6747 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
6748 dev_err(hba->dev,
6749 "invalid ref_clk setting = %ld\n", freq);
6750}
6751
6752static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
6753{
6754 int err;
6755 u32 ref_clk;
6756 u32 freq = hba->dev_ref_clk_freq;
6757
6758 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6759 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
6760
6761 if (err) {
6762 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
6763 err);
6764 goto out;
6765 }
6766
6767 if (ref_clk == freq)
6768 goto out;
6769
6770 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6771 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
6772
6773 if (err) {
6774 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
6775 ufs_ref_clk_freqs[freq].freq_hz);
6776 goto out;
6777 }
6778
6779 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
6780 ufs_ref_clk_freqs[freq].freq_hz);
6781
6782out:
6783 return err;
6784}
6785
6786
6787
6788
6789
6790
6791
6792static int ufshcd_probe_hba(struct ufs_hba *hba)
6793{
6794 struct ufs_dev_desc card = {0};
6795 int ret;
6796 ktime_t start = ktime_get();
6797
6798 ret = ufshcd_link_startup(hba);
6799 if (ret)
6800 goto out;
6801
6802
6803 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6804 hba->is_urgent_bkops_lvl_checked = false;
6805
6806
6807 ufshcd_clear_dbg_ufs_stats(hba);
6808
6809
6810 ufshcd_set_link_active(hba);
6811
6812
6813 ufshcd_auto_hibern8_enable(hba);
6814
6815 ret = ufshcd_verify_dev_init(hba);
6816 if (ret)
6817 goto out;
6818
6819 ret = ufshcd_complete_dev_init(hba);
6820 if (ret)
6821 goto out;
6822
6823
6824 ufshcd_init_desc_sizes(hba);
6825
6826 ret = ufs_get_device_desc(hba, &card);
6827 if (ret) {
6828 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6829 __func__, ret);
6830 goto out;
6831 }
6832
6833 ufs_fixup_device_setup(hba, &card);
6834 ufshcd_tune_unipro_params(hba);
6835
6836
6837 ufshcd_set_ufs_dev_active(hba);
6838 ufshcd_force_reset_auto_bkops(hba);
6839 hba->wlun_dev_clr_ua = true;
6840
6841 if (ufshcd_get_max_pwr_mode(hba)) {
6842 dev_err(hba->dev,
6843 "%s: Failed getting max supported power mode\n",
6844 __func__);
6845 } else {
6846
6847
6848
6849
6850 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
6851 ufshcd_set_dev_ref_clk(hba);
6852 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
6853 if (ret) {
6854 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6855 __func__, ret);
6856 goto out;
6857 }
6858 }
6859
6860
6861 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6862
6863
6864
6865
6866
6867 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6868 bool flag;
6869
6870
6871 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
6872 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6873 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
6874 hba->dev_info.f_power_on_wp_en = flag;
6875
6876 if (!hba->is_init_prefetch)
6877 ufshcd_init_icc_levels(hba);
6878
6879
6880 if (ufshcd_scsi_add_wlus(hba))
6881 goto out;
6882
6883
6884 if (ufshcd_is_clkscaling_supported(hba)) {
6885 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6886 &hba->pwr_info,
6887 sizeof(struct ufs_pa_layer_attr));
6888 hba->clk_scaling.saved_pwr_info.is_valid = true;
6889 if (!hba->devfreq) {
6890 ret = ufshcd_devfreq_init(hba);
6891 if (ret)
6892 goto out;
6893 }
6894 hba->clk_scaling.is_allowed = true;
6895 }
6896
6897 ufs_bsg_probe(hba);
6898
6899 scsi_scan_host(hba->host);
6900 pm_runtime_put_sync(hba->dev);
6901 }
6902
6903 if (!hba->is_init_prefetch)
6904 hba->is_init_prefetch = true;
6905
6906out:
6907
6908
6909
6910
6911 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6912 pm_runtime_put_sync(hba->dev);
6913 ufshcd_exit_clk_scaling(hba);
6914 ufshcd_hba_exit(hba);
6915 }
6916
6917 trace_ufshcd_init(dev_name(hba->dev), ret,
6918 ktime_to_us(ktime_sub(ktime_get(), start)),
6919 hba->curr_dev_pwr_mode, hba->uic_link_state);
6920 return ret;
6921}
6922
6923
6924
6925
6926
6927
6928static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6929{
6930 struct ufs_hba *hba = (struct ufs_hba *)data;
6931
6932 ufshcd_probe_hba(hba);
6933}
6934
6935static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6936{
6937 unsigned long flags;
6938 struct Scsi_Host *host;
6939 struct ufs_hba *hba;
6940 int index;
6941 bool found = false;
6942
6943 if (!scmd || !scmd->device || !scmd->device->host)
6944 return BLK_EH_DONE;
6945
6946 host = scmd->device->host;
6947 hba = shost_priv(host);
6948 if (!hba)
6949 return BLK_EH_DONE;
6950
6951 spin_lock_irqsave(host->host_lock, flags);
6952
6953 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6954 if (hba->lrb[index].cmd == scmd) {
6955 found = true;
6956 break;
6957 }
6958 }
6959
6960 spin_unlock_irqrestore(host->host_lock, flags);
6961
6962
6963
6964
6965
6966
6967 return found ? BLK_EH_DONE : BLK_EH_RESET_TIMER;
6968}
6969
6970static const struct attribute_group *ufshcd_driver_groups[] = {
6971 &ufs_sysfs_unit_descriptor_group,
6972 &ufs_sysfs_lun_attributes_group,
6973 NULL,
6974};
6975
6976static struct scsi_host_template ufshcd_driver_template = {
6977 .module = THIS_MODULE,
6978 .name = UFSHCD,
6979 .proc_name = UFSHCD,
6980 .queuecommand = ufshcd_queuecommand,
6981 .slave_alloc = ufshcd_slave_alloc,
6982 .slave_configure = ufshcd_slave_configure,
6983 .slave_destroy = ufshcd_slave_destroy,
6984 .change_queue_depth = ufshcd_change_queue_depth,
6985 .eh_abort_handler = ufshcd_abort,
6986 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6987 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
6988 .eh_timed_out = ufshcd_eh_timed_out,
6989 .this_id = -1,
6990 .sg_tablesize = SG_ALL,
6991 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6992 .can_queue = UFSHCD_CAN_QUEUE,
6993 .max_host_blocked = 1,
6994 .track_queue_depth = 1,
6995 .sdev_groups = ufshcd_driver_groups,
6996 .dma_boundary = PAGE_SIZE - 1,
6997};
6998
6999static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7000 int ua)
7001{
7002 int ret;
7003
7004 if (!vreg)
7005 return 0;
7006
7007 ret = regulator_set_load(vreg->reg, ua);
7008 if (ret < 0) {
7009 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7010 __func__, vreg->name, ua, ret);
7011 }
7012
7013 return ret;
7014}
7015
7016static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7017 struct ufs_vreg *vreg)
7018{
7019 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
7020}
7021
7022static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7023 struct ufs_vreg *vreg)
7024{
7025 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
7026}
7027
7028static int ufshcd_config_vreg(struct device *dev,
7029 struct ufs_vreg *vreg, bool on)
7030{
7031 int ret = 0;
7032 struct regulator *reg;
7033 const char *name;
7034 int min_uV, uA_load;
7035
7036 BUG_ON(!vreg);
7037
7038 reg = vreg->reg;
7039 name = vreg->name;
7040
7041 if (regulator_count_voltages(reg) > 0) {
7042 min_uV = on ? vreg->min_uV : 0;
7043 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7044 if (ret) {
7045 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
7046 __func__, name, ret);
7047 goto out;
7048 }
7049
7050 uA_load = on ? vreg->max_uA : 0;
7051 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7052 if (ret)
7053 goto out;
7054 }
7055out:
7056 return ret;
7057}
7058
7059static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7060{
7061 int ret = 0;
7062
7063 if (!vreg || vreg->enabled)
7064 goto out;
7065
7066 ret = ufshcd_config_vreg(dev, vreg, true);
7067 if (!ret)
7068 ret = regulator_enable(vreg->reg);
7069
7070 if (!ret)
7071 vreg->enabled = true;
7072 else
7073 dev_err(dev, "%s: %s enable failed, err=%d\n",
7074 __func__, vreg->name, ret);
7075out:
7076 return ret;
7077}
7078
7079static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7080{
7081 int ret = 0;
7082
7083 if (!vreg || !vreg->enabled)
7084 goto out;
7085
7086 ret = regulator_disable(vreg->reg);
7087
7088 if (!ret) {
7089
7090 ufshcd_config_vreg(dev, vreg, false);
7091 vreg->enabled = false;
7092 } else {
7093 dev_err(dev, "%s: %s disable failed, err=%d\n",
7094 __func__, vreg->name, ret);
7095 }
7096out:
7097 return ret;
7098}
7099
7100static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7101{
7102 int ret = 0;
7103 struct device *dev = hba->dev;
7104 struct ufs_vreg_info *info = &hba->vreg_info;
7105
7106 if (!info)
7107 goto out;
7108
7109 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7110 if (ret)
7111 goto out;
7112
7113 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7114 if (ret)
7115 goto out;
7116
7117 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7118 if (ret)
7119 goto out;
7120
7121out:
7122 if (ret) {
7123 ufshcd_toggle_vreg(dev, info->vccq2, false);
7124 ufshcd_toggle_vreg(dev, info->vccq, false);
7125 ufshcd_toggle_vreg(dev, info->vcc, false);
7126 }
7127 return ret;
7128}
7129
7130static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7131{
7132 struct ufs_vreg_info *info = &hba->vreg_info;
7133
7134 if (info)
7135 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
7136
7137 return 0;
7138}
7139
7140static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7141{
7142 int ret = 0;
7143
7144 if (!vreg)
7145 goto out;
7146
7147 vreg->reg = devm_regulator_get(dev, vreg->name);
7148 if (IS_ERR(vreg->reg)) {
7149 ret = PTR_ERR(vreg->reg);
7150 dev_err(dev, "%s: %s get failed, err=%d\n",
7151 __func__, vreg->name, ret);
7152 }
7153out:
7154 return ret;
7155}
7156
7157static int ufshcd_init_vreg(struct ufs_hba *hba)
7158{
7159 int ret = 0;
7160 struct device *dev = hba->dev;
7161 struct ufs_vreg_info *info = &hba->vreg_info;
7162
7163 if (!info)
7164 goto out;
7165
7166 ret = ufshcd_get_vreg(dev, info->vcc);
7167 if (ret)
7168 goto out;
7169
7170 ret = ufshcd_get_vreg(dev, info->vccq);
7171 if (ret)
7172 goto out;
7173
7174 ret = ufshcd_get_vreg(dev, info->vccq2);
7175out:
7176 return ret;
7177}
7178
7179static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7180{
7181 struct ufs_vreg_info *info = &hba->vreg_info;
7182
7183 if (info)
7184 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7185
7186 return 0;
7187}
7188
7189static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7190 bool skip_ref_clk)
7191{
7192 int ret = 0;
7193 struct ufs_clk_info *clki;
7194 struct list_head *head = &hba->clk_list_head;
7195 unsigned long flags;
7196 ktime_t start = ktime_get();
7197 bool clk_state_changed = false;
7198
7199 if (list_empty(head))
7200 goto out;
7201
7202
7203
7204
7205
7206
7207 if (!on) {
7208 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7209 if (ret)
7210 return ret;
7211 }
7212
7213 list_for_each_entry(clki, head, list) {
7214 if (!IS_ERR_OR_NULL(clki->clk)) {
7215 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
7216 continue;
7217
7218 clk_state_changed = on ^ clki->enabled;
7219 if (on && !clki->enabled) {
7220 ret = clk_prepare_enable(clki->clk);
7221 if (ret) {
7222 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7223 __func__, clki->name, ret);
7224 goto out;
7225 }
7226 } else if (!on && clki->enabled) {
7227 clk_disable_unprepare(clki->clk);
7228 }
7229 clki->enabled = on;
7230 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7231 clki->name, on ? "en" : "dis");
7232 }
7233 }
7234
7235
7236
7237
7238
7239
7240 if (on) {
7241 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7242 if (ret)
7243 return ret;
7244 }
7245
7246out:
7247 if (ret) {
7248 list_for_each_entry(clki, head, list) {
7249 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7250 clk_disable_unprepare(clki->clk);
7251 }
7252 } else if (!ret && on) {
7253 spin_lock_irqsave(hba->host->host_lock, flags);
7254 hba->clk_gating.state = CLKS_ON;
7255 trace_ufshcd_clk_gating(dev_name(hba->dev),
7256 hba->clk_gating.state);
7257 spin_unlock_irqrestore(hba->host->host_lock, flags);
7258 }
7259
7260 if (clk_state_changed)
7261 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7262 (on ? "on" : "off"),
7263 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
7264 return ret;
7265}
7266
7267static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7268{
7269 return __ufshcd_setup_clocks(hba, on, false);
7270}
7271
7272static int ufshcd_init_clocks(struct ufs_hba *hba)
7273{
7274 int ret = 0;
7275 struct ufs_clk_info *clki;
7276 struct device *dev = hba->dev;
7277 struct list_head *head = &hba->clk_list_head;
7278
7279 if (list_empty(head))
7280 goto out;
7281
7282 list_for_each_entry(clki, head, list) {
7283 if (!clki->name)
7284 continue;
7285
7286 clki->clk = devm_clk_get(dev, clki->name);
7287 if (IS_ERR(clki->clk)) {
7288 ret = PTR_ERR(clki->clk);
7289 dev_err(dev, "%s: %s clk get failed, %d\n",
7290 __func__, clki->name, ret);
7291 goto out;
7292 }
7293
7294
7295
7296
7297
7298
7299 if (!strcmp(clki->name, "ref_clk"))
7300 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
7301
7302 if (clki->max_freq) {
7303 ret = clk_set_rate(clki->clk, clki->max_freq);
7304 if (ret) {
7305 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7306 __func__, clki->name,
7307 clki->max_freq, ret);
7308 goto out;
7309 }
7310 clki->curr_freq = clki->max_freq;
7311 }
7312 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7313 clki->name, clk_get_rate(clki->clk));
7314 }
7315out:
7316 return ret;
7317}
7318
7319static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7320{
7321 int err = 0;
7322
7323 if (!hba->vops)
7324 goto out;
7325
7326 err = ufshcd_vops_init(hba);
7327 if (err)
7328 goto out;
7329
7330 err = ufshcd_vops_setup_regulators(hba, true);
7331 if (err)
7332 goto out_exit;
7333
7334 goto out;
7335
7336out_exit:
7337 ufshcd_vops_exit(hba);
7338out:
7339 if (err)
7340 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
7341 __func__, ufshcd_get_var_name(hba), err);
7342 return err;
7343}
7344
7345static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7346{
7347 if (!hba->vops)
7348 return;
7349
7350 ufshcd_vops_setup_regulators(hba, false);
7351
7352 ufshcd_vops_exit(hba);
7353}
7354
7355static int ufshcd_hba_init(struct ufs_hba *hba)
7356{
7357 int err;
7358
7359
7360
7361
7362
7363
7364
7365
7366 err = ufshcd_init_hba_vreg(hba);
7367 if (err)
7368 goto out;
7369
7370 err = ufshcd_setup_hba_vreg(hba, true);
7371 if (err)
7372 goto out;
7373
7374 err = ufshcd_init_clocks(hba);
7375 if (err)
7376 goto out_disable_hba_vreg;
7377
7378 err = ufshcd_setup_clocks(hba, true);
7379 if (err)
7380 goto out_disable_hba_vreg;
7381
7382 err = ufshcd_init_vreg(hba);
7383 if (err)
7384 goto out_disable_clks;
7385
7386 err = ufshcd_setup_vreg(hba, true);
7387 if (err)
7388 goto out_disable_clks;
7389
7390 err = ufshcd_variant_hba_init(hba);
7391 if (err)
7392 goto out_disable_vreg;
7393
7394 hba->is_powered = true;
7395 goto out;
7396
7397out_disable_vreg:
7398 ufshcd_setup_vreg(hba, false);
7399out_disable_clks:
7400 ufshcd_setup_clocks(hba, false);
7401out_disable_hba_vreg:
7402 ufshcd_setup_hba_vreg(hba, false);
7403out:
7404 return err;
7405}
7406
7407static void ufshcd_hba_exit(struct ufs_hba *hba)
7408{
7409 if (hba->is_powered) {
7410 ufshcd_variant_hba_exit(hba);
7411 ufshcd_setup_vreg(hba, false);
7412 ufshcd_suspend_clkscaling(hba);
7413 if (ufshcd_is_clkscaling_supported(hba))
7414 if (hba->devfreq)
7415 ufshcd_suspend_clkscaling(hba);
7416 ufshcd_setup_clocks(hba, false);
7417 ufshcd_setup_hba_vreg(hba, false);
7418 hba->is_powered = false;
7419 }
7420}
7421
7422static int
7423ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7424{
7425 unsigned char cmd[6] = {REQUEST_SENSE,
7426 0,
7427 0,
7428 0,
7429 UFS_SENSE_SIZE,
7430 0};
7431 char *buffer;
7432 int ret;
7433
7434 buffer = kzalloc(UFS_SENSE_SIZE, GFP_KERNEL);
7435 if (!buffer) {
7436 ret = -ENOMEM;
7437 goto out;
7438 }
7439
7440 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
7441 UFS_SENSE_SIZE, NULL, NULL,
7442 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
7443 if (ret)
7444 pr_err("%s: failed with err %d\n", __func__, ret);
7445
7446 kfree(buffer);
7447out:
7448 return ret;
7449}
7450
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7461 enum ufs_dev_pwr_mode pwr_mode)
7462{
7463 unsigned char cmd[6] = { START_STOP };
7464 struct scsi_sense_hdr sshdr;
7465 struct scsi_device *sdp;
7466 unsigned long flags;
7467 int ret;
7468
7469 spin_lock_irqsave(hba->host->host_lock, flags);
7470 sdp = hba->sdev_ufs_device;
7471 if (sdp) {
7472 ret = scsi_device_get(sdp);
7473 if (!ret && !scsi_device_online(sdp)) {
7474 ret = -ENODEV;
7475 scsi_device_put(sdp);
7476 }
7477 } else {
7478 ret = -ENODEV;
7479 }
7480 spin_unlock_irqrestore(hba->host->host_lock, flags);
7481
7482 if (ret)
7483 return ret;
7484
7485
7486
7487
7488
7489
7490
7491 hba->host->eh_noresume = 1;
7492 if (hba->wlun_dev_clr_ua) {
7493 ret = ufshcd_send_request_sense(hba, sdp);
7494 if (ret)
7495 goto out;
7496
7497 hba->wlun_dev_clr_ua = false;
7498 }
7499
7500 cmd[4] = pwr_mode << 4;
7501
7502
7503
7504
7505
7506
7507 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7508 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
7509 if (ret) {
7510 sdev_printk(KERN_WARNING, sdp,
7511 "START_STOP failed for power mode: %d, result %x\n",
7512 pwr_mode, ret);
7513 if (driver_byte(ret) == DRIVER_SENSE)
7514 scsi_print_sense_hdr(sdp, NULL, &sshdr);
7515 }
7516
7517 if (!ret)
7518 hba->curr_dev_pwr_mode = pwr_mode;
7519out:
7520 scsi_device_put(sdp);
7521 hba->host->eh_noresume = 0;
7522 return ret;
7523}
7524
7525static int ufshcd_link_state_transition(struct ufs_hba *hba,
7526 enum uic_link_state req_link_state,
7527 int check_for_bkops)
7528{
7529 int ret = 0;
7530
7531 if (req_link_state == hba->uic_link_state)
7532 return 0;
7533
7534 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7535 ret = ufshcd_uic_hibern8_enter(hba);
7536 if (!ret)
7537 ufshcd_set_link_hibern8(hba);
7538 else
7539 goto out;
7540 }
7541
7542
7543
7544
7545 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7546 (!check_for_bkops || (check_for_bkops &&
7547 !hba->auto_bkops_enabled))) {
7548
7549
7550
7551
7552
7553
7554
7555 ret = ufshcd_uic_hibern8_enter(hba);
7556 if (ret)
7557 goto out;
7558
7559
7560
7561
7562 ufshcd_hba_stop(hba, true);
7563
7564
7565
7566
7567 ufshcd_set_link_off(hba);
7568 }
7569
7570out:
7571 return ret;
7572}
7573
7574static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7575{
7576
7577
7578
7579
7580
7581
7582 if (!ufshcd_is_link_active(hba) &&
7583 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7584 usleep_range(2000, 2100);
7585
7586
7587
7588
7589
7590
7591
7592
7593
7594
7595
7596
7597
7598 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7599 !hba->dev_info.is_lu_power_on_wp) {
7600 ufshcd_setup_vreg(hba, false);
7601 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7602 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7603 if (!ufshcd_is_link_active(hba)) {
7604 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7605 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7606 }
7607 }
7608}
7609
7610static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7611{
7612 int ret = 0;
7613
7614 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7615 !hba->dev_info.is_lu_power_on_wp) {
7616 ret = ufshcd_setup_vreg(hba, true);
7617 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7618 if (!ret && !ufshcd_is_link_active(hba)) {
7619 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7620 if (ret)
7621 goto vcc_disable;
7622 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7623 if (ret)
7624 goto vccq_lpm;
7625 }
7626 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
7627 }
7628 goto out;
7629
7630vccq_lpm:
7631 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7632vcc_disable:
7633 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7634out:
7635 return ret;
7636}
7637
7638static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7639{
7640 if (ufshcd_is_link_off(hba))
7641 ufshcd_setup_hba_vreg(hba, false);
7642}
7643
7644static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7645{
7646 if (ufshcd_is_link_off(hba))
7647 ufshcd_setup_hba_vreg(hba, true);
7648}
7649
7650
7651
7652
7653
7654
7655
7656
7657
7658
7659
7660
7661
7662
7663
7664
7665
7666static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7667{
7668 int ret = 0;
7669 enum ufs_pm_level pm_lvl;
7670 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7671 enum uic_link_state req_link_state;
7672
7673 hba->pm_op_in_progress = 1;
7674 if (!ufshcd_is_shutdown_pm(pm_op)) {
7675 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7676 hba->rpm_lvl : hba->spm_lvl;
7677 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7678 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7679 } else {
7680 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7681 req_link_state = UIC_LINK_OFF_STATE;
7682 }
7683
7684
7685
7686
7687
7688 ufshcd_hold(hba, false);
7689 hba->clk_gating.is_suspended = true;
7690
7691 if (hba->clk_scaling.is_allowed) {
7692 cancel_work_sync(&hba->clk_scaling.suspend_work);
7693 cancel_work_sync(&hba->clk_scaling.resume_work);
7694 ufshcd_suspend_clkscaling(hba);
7695 }
7696
7697 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7698 req_link_state == UIC_LINK_ACTIVE_STATE) {
7699 goto disable_clks;
7700 }
7701
7702 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7703 (req_link_state == hba->uic_link_state))
7704 goto enable_gating;
7705
7706
7707 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7708 ret = -EINVAL;
7709 goto enable_gating;
7710 }
7711
7712 if (ufshcd_is_runtime_pm(pm_op)) {
7713 if (ufshcd_can_autobkops_during_suspend(hba)) {
7714
7715
7716
7717
7718
7719 ret = ufshcd_urgent_bkops(hba);
7720 if (ret)
7721 goto enable_gating;
7722 } else {
7723
7724 ufshcd_disable_auto_bkops(hba);
7725 }
7726 }
7727
7728 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7729 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7730 !ufshcd_is_runtime_pm(pm_op))) {
7731
7732 ufshcd_disable_auto_bkops(hba);
7733 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7734 if (ret)
7735 goto enable_gating;
7736 }
7737
7738 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7739 if (ret)
7740 goto set_dev_active;
7741
7742 ufshcd_vreg_set_lpm(hba);
7743
7744disable_clks:
7745
7746
7747
7748
7749
7750 ret = ufshcd_vops_suspend(hba, pm_op);
7751 if (ret)
7752 goto set_link_active;
7753
7754 if (!ufshcd_is_link_active(hba))
7755 ufshcd_setup_clocks(hba, false);
7756 else
7757
7758 __ufshcd_setup_clocks(hba, false, true);
7759
7760 hba->clk_gating.state = CLKS_OFF;
7761 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
7762
7763
7764
7765
7766 ufshcd_disable_irq(hba);
7767
7768 ufshcd_hba_vreg_set_lpm(hba);
7769 goto out;
7770
7771set_link_active:
7772 if (hba->clk_scaling.is_allowed)
7773 ufshcd_resume_clkscaling(hba);
7774 ufshcd_vreg_set_hpm(hba);
7775 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7776 ufshcd_set_link_active(hba);
7777 else if (ufshcd_is_link_off(hba))
7778 ufshcd_host_reset_and_restore(hba);
7779set_dev_active:
7780 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7781 ufshcd_disable_auto_bkops(hba);
7782enable_gating:
7783 if (hba->clk_scaling.is_allowed)
7784 ufshcd_resume_clkscaling(hba);
7785 hba->clk_gating.is_suspended = false;
7786 ufshcd_release(hba);
7787out:
7788 hba->pm_op_in_progress = 0;
7789 return ret;
7790}
7791
7792
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7803{
7804 int ret;
7805 enum uic_link_state old_link_state;
7806
7807 hba->pm_op_in_progress = 1;
7808 old_link_state = hba->uic_link_state;
7809
7810 ufshcd_hba_vreg_set_hpm(hba);
7811
7812 ret = ufshcd_setup_clocks(hba, true);
7813 if (ret)
7814 goto out;
7815
7816
7817 ret = ufshcd_enable_irq(hba);
7818 if (ret)
7819 goto disable_irq_and_vops_clks;
7820
7821 ret = ufshcd_vreg_set_hpm(hba);
7822 if (ret)
7823 goto disable_irq_and_vops_clks;
7824
7825
7826
7827
7828
7829
7830 ret = ufshcd_vops_resume(hba, pm_op);
7831 if (ret)
7832 goto disable_vreg;
7833
7834 if (ufshcd_is_link_hibern8(hba)) {
7835 ret = ufshcd_uic_hibern8_exit(hba);
7836 if (!ret)
7837 ufshcd_set_link_active(hba);
7838 else
7839 goto vendor_suspend;
7840 } else if (ufshcd_is_link_off(hba)) {
7841 ret = ufshcd_host_reset_and_restore(hba);
7842
7843
7844
7845
7846 if (ret || !ufshcd_is_link_active(hba))
7847 goto vendor_suspend;
7848 }
7849
7850 if (!ufshcd_is_ufs_dev_active(hba)) {
7851 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7852 if (ret)
7853 goto set_old_link_state;
7854 }
7855
7856 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7857 ufshcd_enable_auto_bkops(hba);
7858 else
7859
7860
7861
7862
7863 ufshcd_urgent_bkops(hba);
7864
7865 hba->clk_gating.is_suspended = false;
7866
7867 if (hba->clk_scaling.is_allowed)
7868 ufshcd_resume_clkscaling(hba);
7869
7870
7871 ufshcd_release(hba);
7872
7873
7874 ufshcd_auto_hibern8_enable(hba);
7875
7876 goto out;
7877
7878set_old_link_state:
7879 ufshcd_link_state_transition(hba, old_link_state, 0);
7880vendor_suspend:
7881 ufshcd_vops_suspend(hba, pm_op);
7882disable_vreg:
7883 ufshcd_vreg_set_lpm(hba);
7884disable_irq_and_vops_clks:
7885 ufshcd_disable_irq(hba);
7886 if (hba->clk_scaling.is_allowed)
7887 ufshcd_suspend_clkscaling(hba);
7888 ufshcd_setup_clocks(hba, false);
7889out:
7890 hba->pm_op_in_progress = 0;
7891 return ret;
7892}
7893
7894
7895
7896
7897
7898
7899
7900
7901
7902int ufshcd_system_suspend(struct ufs_hba *hba)
7903{
7904 int ret = 0;
7905 ktime_t start = ktime_get();
7906
7907 if (!hba || !hba->is_powered)
7908 return 0;
7909
7910 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7911 hba->curr_dev_pwr_mode) &&
7912 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7913 hba->uic_link_state))
7914 goto out;
7915
7916 if (pm_runtime_suspended(hba->dev)) {
7917
7918
7919
7920
7921
7922
7923
7924
7925 ret = ufshcd_runtime_resume(hba);
7926 if (ret)
7927 goto out;
7928 }
7929
7930 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7931out:
7932 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7933 ktime_to_us(ktime_sub(ktime_get(), start)),
7934 hba->curr_dev_pwr_mode, hba->uic_link_state);
7935 if (!ret)
7936 hba->is_sys_suspended = true;
7937 return ret;
7938}
7939EXPORT_SYMBOL(ufshcd_system_suspend);
7940
7941
7942
7943
7944
7945
7946
7947
7948int ufshcd_system_resume(struct ufs_hba *hba)
7949{
7950 int ret = 0;
7951 ktime_t start = ktime_get();
7952
7953 if (!hba)
7954 return -EINVAL;
7955
7956 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
7957
7958
7959
7960
7961 goto out;
7962 else
7963 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7964out:
7965 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7966 ktime_to_us(ktime_sub(ktime_get(), start)),
7967 hba->curr_dev_pwr_mode, hba->uic_link_state);
7968 if (!ret)
7969 hba->is_sys_suspended = false;
7970 return ret;
7971}
7972EXPORT_SYMBOL(ufshcd_system_resume);
7973
7974
7975
7976
7977
7978
7979
7980
7981
7982int ufshcd_runtime_suspend(struct ufs_hba *hba)
7983{
7984 int ret = 0;
7985 ktime_t start = ktime_get();
7986
7987 if (!hba)
7988 return -EINVAL;
7989
7990 if (!hba->is_powered)
7991 goto out;
7992 else
7993 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7994out:
7995 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7996 ktime_to_us(ktime_sub(ktime_get(), start)),
7997 hba->curr_dev_pwr_mode, hba->uic_link_state);
7998 return ret;
7999}
8000EXPORT_SYMBOL(ufshcd_runtime_suspend);
8001
8002
8003
8004
8005
8006
8007
8008
8009
8010
8011
8012
8013
8014
8015
8016
8017
8018
8019
8020
8021
8022
8023int ufshcd_runtime_resume(struct ufs_hba *hba)
8024{
8025 int ret = 0;
8026 ktime_t start = ktime_get();
8027
8028 if (!hba)
8029 return -EINVAL;
8030
8031 if (!hba->is_powered)
8032 goto out;
8033 else
8034 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8035out:
8036 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8037 ktime_to_us(ktime_sub(ktime_get(), start)),
8038 hba->curr_dev_pwr_mode, hba->uic_link_state);
8039 return ret;
8040}
8041EXPORT_SYMBOL(ufshcd_runtime_resume);
8042
8043int ufshcd_runtime_idle(struct ufs_hba *hba)
8044{
8045 return 0;
8046}
8047EXPORT_SYMBOL(ufshcd_runtime_idle);
8048
8049
8050
8051
8052
8053
8054
8055
8056
8057int ufshcd_shutdown(struct ufs_hba *hba)
8058{
8059 int ret = 0;
8060
8061 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8062 goto out;
8063
8064 if (pm_runtime_suspended(hba->dev)) {
8065 ret = ufshcd_runtime_resume(hba);
8066 if (ret)
8067 goto out;
8068 }
8069
8070 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8071out:
8072 if (ret)
8073 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8074
8075 return 0;
8076}
8077EXPORT_SYMBOL(ufshcd_shutdown);
8078
8079
8080
8081
8082
8083
8084void ufshcd_remove(struct ufs_hba *hba)
8085{
8086 ufs_bsg_remove(hba);
8087 ufs_sysfs_remove_nodes(hba->dev);
8088 scsi_remove_host(hba->host);
8089
8090 ufshcd_disable_intr(hba, hba->intr_mask);
8091 ufshcd_hba_stop(hba, true);
8092
8093 ufshcd_exit_clk_scaling(hba);
8094 ufshcd_exit_clk_gating(hba);
8095 if (ufshcd_is_clkscaling_supported(hba))
8096 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
8097 ufshcd_hba_exit(hba);
8098}
8099EXPORT_SYMBOL_GPL(ufshcd_remove);
8100
8101
8102
8103
8104
8105void ufshcd_dealloc_host(struct ufs_hba *hba)
8106{
8107 scsi_host_put(hba->host);
8108}
8109EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8110
8111
8112
8113
8114
8115
8116
8117
8118static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8119{
8120 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8121 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8122 return 0;
8123 }
8124 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8125}
8126
8127
8128
8129
8130
8131
8132
8133int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
8134{
8135 struct Scsi_Host *host;
8136 struct ufs_hba *hba;
8137 int err = 0;
8138
8139 if (!dev) {
8140 dev_err(dev,
8141 "Invalid memory reference for dev is NULL\n");
8142 err = -ENODEV;
8143 goto out_error;
8144 }
8145
8146 host = scsi_host_alloc(&ufshcd_driver_template,
8147 sizeof(struct ufs_hba));
8148 if (!host) {
8149 dev_err(dev, "scsi_host_alloc failed\n");
8150 err = -ENOMEM;
8151 goto out_error;
8152 }
8153 hba = shost_priv(host);
8154 hba->host = host;
8155 hba->dev = dev;
8156 *hba_handle = hba;
8157 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
8158
8159 INIT_LIST_HEAD(&hba->clk_list_head);
8160
8161out_error:
8162 return err;
8163}
8164EXPORT_SYMBOL(ufshcd_alloc_host);
8165
8166
8167
8168
8169
8170
8171
8172
8173int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8174{
8175 int err;
8176 struct Scsi_Host *host = hba->host;
8177 struct device *dev = hba->dev;
8178
8179 if (!mmio_base) {
8180 dev_err(hba->dev,
8181 "Invalid memory reference for mmio_base is NULL\n");
8182 err = -ENODEV;
8183 goto out_error;
8184 }
8185
8186 hba->mmio_base = mmio_base;
8187 hba->irq = irq;
8188
8189
8190 ufshcd_def_desc_sizes(hba);
8191
8192 err = ufshcd_hba_init(hba);
8193 if (err)
8194 goto out_error;
8195
8196
8197 ufshcd_hba_capabilities(hba);
8198
8199
8200 hba->ufs_version = ufshcd_get_ufs_version(hba);
8201
8202 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8203 (hba->ufs_version != UFSHCI_VERSION_11) &&
8204 (hba->ufs_version != UFSHCI_VERSION_20) &&
8205 (hba->ufs_version != UFSHCI_VERSION_21))
8206 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8207 hba->ufs_version);
8208
8209
8210 hba->intr_mask = ufshcd_get_intr_mask(hba);
8211
8212 err = ufshcd_set_dma_mask(hba);
8213 if (err) {
8214 dev_err(hba->dev, "set dma mask failed\n");
8215 goto out_disable;
8216 }
8217
8218
8219 err = ufshcd_memory_alloc(hba);
8220 if (err) {
8221 dev_err(hba->dev, "Memory allocation failed\n");
8222 goto out_disable;
8223 }
8224
8225
8226 ufshcd_host_memory_configure(hba);
8227
8228 host->can_queue = hba->nutrs;
8229 host->cmd_per_lun = hba->nutrs;
8230 host->max_id = UFSHCD_MAX_ID;
8231 host->max_lun = UFS_MAX_LUNS;
8232 host->max_channel = UFSHCD_MAX_CHANNEL;
8233 host->unique_id = host->host_no;
8234 host->max_cmd_len = UFS_CDB_SIZE;
8235
8236 hba->max_pwr_info.is_valid = false;
8237
8238
8239 init_waitqueue_head(&hba->tm_wq);
8240 init_waitqueue_head(&hba->tm_tag_wq);
8241
8242
8243 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
8244 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
8245
8246
8247 mutex_init(&hba->uic_cmd_mutex);
8248
8249
8250 mutex_init(&hba->dev_cmd.lock);
8251
8252 init_rwsem(&hba->clk_scaling_lock);
8253
8254
8255 init_waitqueue_head(&hba->dev_cmd.tag_wq);
8256
8257 ufshcd_init_clk_gating(hba);
8258
8259 ufshcd_init_clk_scaling(hba);
8260
8261
8262
8263
8264
8265
8266 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8267 REG_INTERRUPT_STATUS);
8268 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8269
8270
8271
8272
8273 mb();
8274
8275
8276 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
8277 if (err) {
8278 dev_err(hba->dev, "request irq failed\n");
8279 goto exit_gating;
8280 } else {
8281 hba->is_irq_enabled = true;
8282 }
8283
8284 err = scsi_add_host(host, hba->dev);
8285 if (err) {
8286 dev_err(hba->dev, "scsi_add_host failed\n");
8287 goto exit_gating;
8288 }
8289
8290
8291 err = ufshcd_hba_enable(hba);
8292 if (err) {
8293 dev_err(hba->dev, "Host controller enable failed\n");
8294 ufshcd_print_host_regs(hba);
8295 ufshcd_print_host_state(hba);
8296 goto out_remove_scsi_host;
8297 }
8298
8299
8300
8301
8302
8303
8304 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8305 UFS_SLEEP_PWR_MODE,
8306 UIC_LINK_HIBERN8_STATE);
8307 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8308 UFS_SLEEP_PWR_MODE,
8309 UIC_LINK_HIBERN8_STATE);
8310
8311
8312 if (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) {
8313 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
8314 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
8315 }
8316
8317
8318 pm_runtime_get_sync(dev);
8319 atomic_set(&hba->scsi_block_reqs_cnt, 0);
8320
8321
8322
8323
8324
8325
8326 ufshcd_set_ufs_dev_active(hba);
8327
8328 async_schedule(ufshcd_async_scan, hba);
8329 ufs_sysfs_add_nodes(hba->dev);
8330
8331 return 0;
8332
8333out_remove_scsi_host:
8334 scsi_remove_host(hba->host);
8335exit_gating:
8336 ufshcd_exit_clk_scaling(hba);
8337 ufshcd_exit_clk_gating(hba);
8338out_disable:
8339 hba->is_irq_enabled = false;
8340 ufshcd_hba_exit(hba);
8341out_error:
8342 return err;
8343}
8344EXPORT_SYMBOL_GPL(ufshcd_init);
8345
8346MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8347MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
8348MODULE_DESCRIPTION("Generic UFS host controller driver Core");
8349MODULE_LICENSE("GPL");
8350MODULE_VERSION(UFSHCD_DRIVER_VERSION);
8351