1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************** 3 * 4 * Copyright(c) 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14#ifndef __HALMAC_COM_REG_H__ 15#define __HALMAC_COM_REG_H__ 16/*-------------------------Modification Log----------------------------------- 17 * For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524 18 * The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A 19 * 8812A and 8188E is not included in page0 register 20 * 21 * For other pages, it is based on MAC_Register.doc SVN502 22 * Most IC is the same with 8812A 23 *-------------------------Modification Log----------------------------------- 24 */ 25 26/*--------------------------Include File--------------------------------------*/ 27/*--------------------------Include File--------------------------------------*/ 28 29#define REG_SYS_ISO_CTRL 0x0000 30 31#define REG_SDIO_TX_CTRL 0x10250000 32 33#define REG_SYS_FUNC_EN 0x0002 34#define REG_SYS_PW_CTRL 0x0004 35#define REG_SYS_CLK_CTRL 0x0008 36#define REG_SYS_EEPROM_CTRL 0x000A 37#define REG_EE_VPD 0x000C 38#define REG_SYS_SWR_CTRL1 0x0010 39#define REG_SYS_SWR_CTRL2 0x0014 40 41#define REG_SDIO_HIMR 0x10250014 42 43#define REG_SYS_SWR_CTRL3 0x0018 44 45#define REG_SDIO_HISR 0x10250018 46 47#define REG_RSV_CTRL 0x001C 48 49#define REG_SDIO_RX_REQ_LEN 0x1025001C 50 51#define REG_RF_CTRL 0x001F 52 53#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F 54 55#define REG_AFE_LDO_CTRL 0x0020 56 57#define REG_SDIO_FREE_TXPG 0x10250020 58 59#define REG_AFE_CTRL1 0x0024 60 61#define REG_SDIO_FREE_TXPG2 0x10250024 62 63#define REG_AFE_CTRL2 0x0028 64 65#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028 66 67#define REG_AFE_CTRL3 0x002C 68#define REG_EFUSE_CTRL 0x0030 69 70#define REG_SDIO_HTSFR_INFO 0x10250030 71 72#define REG_LDO_EFUSE_CTRL 0x0034 73#define REG_PWR_OPTION_CTRL 0x0038 74 75#define REG_SDIO_HCPWM1_V2 0x10250038 76#define REG_SDIO_HCPWM2_V2 0x1025003A 77 78#define REG_CAL_TIMER 0x003C 79#define REG_ACLK_MON 0x003E 80#define REG_GPIO_MUXCFG 0x0040 81 82#define REG_SDIO_INDIRECT_REG_CFG 0x10250040 83 84#define REG_GPIO_PIN_CTRL 0x0044 85 86#define REG_SDIO_INDIRECT_REG_DATA 0x10250044 87 88#define REG_GPIO_INTM 0x0048 89#define REG_LED_CFG 0x004C 90#define REG_FSIMR 0x0050 91#define REG_FSISR 0x0054 92#define REG_HSIMR 0x0058 93#define REG_HSISR 0x005C 94#define REG_GPIO_EXT_CTRL 0x0060 95 96#define REG_SDIO_H2C 0x10250060 97 98#define REG_PAD_CTRL1 0x0064 99 100#define REG_SDIO_C2H 0x10250064 101 102#define REG_WL_BT_PWR_CTRL 0x0068 103 104#define REG_SDM_DEBUG 0x006C 105 106#define REG_SYS_SDIO_CTRL 0x0070 107 108#define REG_HCI_OPT_CTRL 0x0074 109 110#define REG_AFE_CTRL4 0x0078 111 112#define REG_LDO_SWR_CTRL 0x007C 113 114#define REG_MCUFW_CTRL 0x0080 115 116#define REG_SDIO_HRPWM1 0x10250080 117#define REG_SDIO_HRPWM2 0x10250082 118 119#define REG_MCU_TST_CFG 0x0084 120 121#define REG_SDIO_HPS_CLKR 0x10250084 122#define REG_SDIO_BUS_CTRL 0x10250085 123 124#define REG_SDIO_HSUS_CTRL 0x10250086 125 126#define REG_HMEBOX_E0_E1 0x0088 127 128#define REG_SDIO_RESPONSE_TIMER 0x10250088 129 130#define REG_SDIO_CMD_CRC 0x1025008A 131 132#define REG_HMEBOX_E2_E3 0x008C 133#define REG_WLLPS_CTRL 0x0090 134 135#define REG_SDIO_HSISR 0x10250090 136#define REG_SDIO_HSIMR 0x10250091 137 138#define REG_AFE_CTRL5 0x0094 139 140#define REG_GPIO_DEBOUNCE_CTRL 0x0098 141#define REG_RPWM2 0x009C 142#define REG_SYSON_FSM_MON 0x00A0 143 144#define REG_AFE_CTRL6 0x00A4 145 146#define REG_PMC_DBG_CTRL1 0x00A8 147 148#define REG_AFE_CTRL7 0x00AC 149 150#define REG_HIMR0 0x00B0 151#define REG_HISR0 0x00B4 152#define REG_HIMR1 0x00B8 153#define REG_HISR1 0x00BC 154#define REG_DBG_PORT_SEL 0x00C0 155 156#define REG_SDIO_ERR_RPT 0x102500C0 157#define REG_SDIO_CMD_ERRCNT 0x102500C1 158#define REG_SDIO_DATA_ERRCNT 0x102500C2 159 160#define REG_PAD_CTRL2 0x00C4 161 162#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4 163 164#define REG_SDIO_CRC_ERR_IDX 0x102500C9 165#define REG_SDIO_DATA_CRC 0x102500CA 166#define REG_SDIO_DATA_REPLY_TIME 0x102500CB 167 168#define REG_PMC_DBG_CTRL2 0x00CC 169#define REG_BIST_CTRL 0x00D0 170#define REG_BIST_RPT 0x00D4 171#define REG_MEM_CTRL 0x00D8 172 173#define REG_AFE_CTRL8 0x00DC 174 175#define REG_USB_SIE_INTF 0x00E0 176#define REG_PCIE_MIO_INTF 0x00E4 177#define REG_PCIE_MIO_INTD 0x00E8 178 179#define REG_WLRF1 0x00EC 180 181#define REG_SYS_CFG1 0x00F0 182#define REG_SYS_STATUS1 0x00F4 183#define REG_SYS_STATUS2 0x00F8 184#define REG_SYS_CFG2 0x00FC 185#define REG_CR 0x0100 186 187#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 188 189#define REG_TSF_CLK_STATE 0x0108 190#define REG_TXDMA_PQ_MAP 0x010C 191#define REG_TRXFF_BNDY 0x0114 192 193#define REG_PTA_I2C_MBOX 0x0118 194 195#define REG_RXFF_BNDY 0x011C 196 197#define REG_FE1IMR 0x0120 198 199#define REG_FE1ISR 0x0124 200 201#define REG_CPWM 0x012C 202#define REG_FWIMR 0x0130 203#define REG_FWISR 0x0134 204#define REG_FTIMR 0x0138 205#define REG_FTISR 0x013C 206#define REG_PKTBUF_DBG_CTRL 0x0140 207#define REG_PKTBUF_DBG_DATA_L 0x0144 208#define REG_PKTBUF_DBG_DATA_H 0x0148 209#define REG_CPWM2 0x014C 210#define REG_TC0_CTRL 0x0150 211#define REG_TC1_CTRL 0x0154 212#define REG_TC2_CTRL 0x0158 213#define REG_TC3_CTRL 0x015C 214#define REG_TC4_CTRL 0x0160 215#define REG_TCUNIT_BASE 0x0164 216#define REG_TC5_CTRL 0x0168 217#define REG_TC6_CTRL 0x016C 218#define REG_MBIST_FAIL 0x0170 219#define REG_MBIST_START_PAUSE 0x0174 220#define REG_MBIST_DONE 0x0178 221 222#define REG_MBIST_FAIL_NRML 0x017C 223 224#define REG_AES_DECRPT_DATA 0x0180 225#define REG_AES_DECRPT_CFG 0x0184 226 227#define REG_TMETER 0x0190 228#define REG_OSC_32K_CTRL 0x0194 229#define REG_32K_CAL_REG1 0x0198 230#define REG_C2HEVT 0x01A0 231 232#define REG_C2HEVT_1 0x01A4 233#define REG_C2HEVT_2 0x01A8 234#define REG_C2HEVT_3 0x01AC 235 236#define REG_SW_DEFINED_PAGE1 0x01B8 237 238#define REG_MCUTST_I 0x01C0 239#define REG_MCUTST_II 0x01C4 240#define REG_FMETHR 0x01C8 241#define REG_HMETFR 0x01CC 242#define REG_HMEBOX0 0x01D0 243#define REG_HMEBOX1 0x01D4 244#define REG_HMEBOX2 0x01D8 245#define REG_HMEBOX3 0x01DC 246#define REG_LLT_INIT 0x01E0 247 248#define REG_LLT_INIT_ADDR 0x01E4 249 250#define REG_BB_ACCESS_CTRL 0x01E8 251#define REG_BB_ACCESS_DATA 0x01EC 252#define REG_HMEBOX_E0 0x01F0 253#define REG_HMEBOX_E1 0x01F4 254#define REG_HMEBOX_E2 0x01F8 255#define REG_HMEBOX_E3 0x01FC 256 257#define REG_FIFOPAGE_CTRL_1 0x0200 258 259#define REG_FIFOPAGE_CTRL_2 0x0204 260 261#define REG_AUTO_LLT_V1 0x0208 262 263#define REG_TXDMA_OFFSET_CHK 0x020C 264#define REG_TXDMA_STATUS 0x0210 265 266#define REG_TX_DMA_DBG 0x0214 267 268#define REG_TQPNT1 0x0218 269#define REG_TQPNT2 0x021C 270 271#define REG_TQPNT3 0x0220 272 273#define REG_TQPNT4 0x0224 274 275#define REG_RQPN_CTRL_1 0x0228 276#define REG_RQPN_CTRL_2 0x022C 277#define REG_FIFOPAGE_INFO_1 0x0230 278#define REG_FIFOPAGE_INFO_2 0x0234 279#define REG_FIFOPAGE_INFO_3 0x0238 280#define REG_FIFOPAGE_INFO_4 0x023C 281#define REG_FIFOPAGE_INFO_5 0x0240 282 283#define REG_H2C_HEAD 0x0244 284#define REG_H2C_TAIL 0x0248 285#define REG_H2C_READ_ADDR 0x024C 286#define REG_H2C_WR_ADDR 0x0250 287#define REG_H2C_INFO 0x0254 288 289#define REG_RXDMA_AGG_PG_TH 0x0280 290#define REG_RXPKT_NUM 0x0284 291#define REG_RXDMA_STATUS 0x0288 292#define REG_RXDMA_DPR 0x028C 293#define REG_RXDMA_MODE 0x0290 294#define REG_C2H_PKT 0x0294 295 296#define REG_FWFF_C2H 0x0298 297#define REG_FWFF_CTRL 0x029C 298#define REG_FWFF_PKT_INFO 0x02A0 299 300#define REG_PCIE_CTRL 0x0300 301 302#define REG_INT_MIG 0x0304 303#define REG_BCNQ_TXBD_DESA 0x0308 304#define REG_MGQ_TXBD_DESA 0x0310 305#define REG_VOQ_TXBD_DESA 0x0318 306#define REG_VIQ_TXBD_DESA 0x0320 307#define REG_BEQ_TXBD_DESA 0x0328 308#define REG_BKQ_TXBD_DESA 0x0330 309#define REG_RXQ_RXBD_DESA 0x0338 310#define REG_HI0Q_TXBD_DESA 0x0340 311#define REG_HI1Q_TXBD_DESA 0x0348 312#define REG_HI2Q_TXBD_DESA 0x0350 313#define REG_HI3Q_TXBD_DESA 0x0358 314#define REG_HI4Q_TXBD_DESA 0x0360 315#define REG_HI5Q_TXBD_DESA 0x0368 316#define REG_HI6Q_TXBD_DESA 0x0370 317#define REG_HI7Q_TXBD_DESA 0x0378 318#define REG_MGQ_TXBD_NUM 0x0380 319#define REG_RX_RXBD_NUM 0x0382 320#define REG_VOQ_TXBD_NUM 0x0384 321#define REG_VIQ_TXBD_NUM 0x0386 322#define REG_BEQ_TXBD_NUM 0x0388 323#define REG_BKQ_TXBD_NUM 0x038A 324#define REG_HI0Q_TXBD_NUM 0x038C 325#define REG_HI1Q_TXBD_NUM 0x038E 326#define REG_HI2Q_TXBD_NUM 0x0390 327#define REG_HI3Q_TXBD_NUM 0x0392 328#define REG_HI4Q_TXBD_NUM 0x0394 329#define REG_HI5Q_TXBD_NUM 0x0396 330#define REG_HI6Q_TXBD_NUM 0x0398 331#define REG_HI7Q_TXBD_NUM 0x039A 332#define REG_TSFTIMER_HCI 0x039C 333#define REG_BD_RWPTR_CLR 0x039C 334#define REG_VOQ_TXBD_IDX 0x03A0 335#define REG_VIQ_TXBD_IDX 0x03A4 336#define REG_BEQ_TXBD_IDX 0x03A8 337#define REG_BKQ_TXBD_IDX 0x03AC 338#define REG_MGQ_TXBD_IDX 0x03B0 339#define REG_RXQ_RXBD_IDX 0x03B4 340#define REG_HI0Q_TXBD_IDX 0x03B8 341#define REG_HI1Q_TXBD_IDX 0x03BC 342#define REG_HI2Q_TXBD_IDX 0x03C0 343#define REG_HI3Q_TXBD_IDX 0x03C4 344#define REG_HI4Q_TXBD_IDX 0x03C8 345#define REG_HI5Q_TXBD_IDX 0x03CC 346#define REG_HI6Q_TXBD_IDX 0x03D0 347#define REG_HI7Q_TXBD_IDX 0x03D4 348 349#define REG_DBG_SEL_V1 0x03D8 350 351#define REG_PCIE_HRPWM1_V1 0x03D9 352 353#define REG_PCIE_HCPWM1_V1 0x03DA 354 355#define REG_PCIE_CTRL2 0x03DB 356 357#define REG_PCIE_HRPWM2_V1 0x03DC 358 359#define REG_PCIE_HCPWM2_V1 0x03DE 360 361#define REG_PCIE_H2C_MSG_V1 0x03E0 362 363#define REG_PCIE_C2H_MSG_V1 0x03E4 364 365#define REG_DBI_WDATA_V1 0x03E8 366 367#define REG_DBI_RDATA_V1 0x03EC 368 369#define REG_DBI_FLAG_V1 0x03F0 370 371#define REG_MDIO_V1 0x03F4 372 373#define REG_PCIE_MIX_CFG 0x03F8 374 375#define REG_HCI_MIX_CFG 0x03FC 376 377#define REG_Q0_INFO 0x0400 378#define REG_Q1_INFO 0x0404 379#define REG_Q2_INFO 0x0408 380#define REG_Q3_INFO 0x040C 381#define REG_MGQ_INFO 0x0410 382#define REG_HIQ_INFO 0x0414 383#define REG_BCNQ_INFO 0x0418 384#define REG_TXPKT_EMPTY 0x041A 385#define REG_CPU_MGQ_INFO 0x041C 386#define REG_FWHW_TXQ_CTRL 0x0420 387 388#define REG_DATAFB_SEL 0x0423 389 390#define REG_BCNQ_BDNY_V1 0x0424 391 392#define REG_LIFETIME_EN 0x0426 393 394#define REG_SPEC_SIFS 0x0428 395#define REG_RETRY_LIMIT 0x042A 396#define REG_TXBF_CTRL 0x042C 397#define REG_DARFRC 0x0430 398#define REG_RARFRC 0x0438 399#define REG_RRSR 0x0440 400#define REG_ARFR0 0x0444 401#define REG_ARFR1_V1 0x044C 402#define REG_CCK_CHECK 0x0454 403 404#define REG_AMPDU_MAX_TIME_V1 0x0455 405 406#define REG_BCNQ1_BDNY_V1 0x0456 407 408#define REG_AMPDU_MAX_LENGTH 0x0458 409#define REG_ACQ_STOP 0x045C 410 411#define REG_NDPA_RATE 0x045D 412 413#define REG_TX_HANG_CTRL 0x045E 414#define REG_NDPA_OPT_CTRL 0x045F 415 416#define REG_RD_RESP_PKT_TH 0x0463 417#define REG_CMDQ_INFO 0x0464 418#define REG_Q4_INFO 0x0468 419#define REG_Q5_INFO 0x046C 420#define REG_Q6_INFO 0x0470 421#define REG_Q7_INFO 0x0474 422 423#define REG_WMAC_LBK_BUF_HD_V1 0x0478 424#define REG_MGQ_BDNY_V1 0x047A 425 426#define REG_TXRPT_CTRL 0x047C 427#define REG_INIRTS_RATE_SEL 0x0480 428#define REG_BASIC_CFEND_RATE 0x0481 429#define REG_STBC_CFEND_RATE 0x0482 430#define REG_DATA_SC 0x0483 431#define REG_MACID_SLEEP3 0x0484 432#define REG_MACID_SLEEP1 0x0488 433#define REG_ARFR2_V1 0x048C 434#define REG_ARFR3_V1 0x0494 435#define REG_ARFR4 0x049C 436#define REG_ARFR5 0x04A4 437#define REG_TXRPT_START_OFFSET 0x04AC 438 439#define REG_POWER_STAGE1 0x04B4 440 441#define REG_POWER_STAGE2 0x04B8 442 443#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC 444#define REG_PKT_LIFE_TIME 0x04C0 445#define REG_STBC_SETTING 0x04C4 446#define REG_STBC_SETTING2 0x04C5 447#define REG_QUEUE_CTRL 0x04C6 448#define REG_SINGLE_AMPDU_CTRL 0x04C7 449#define REG_PROT_MODE_CTRL 0x04C8 450#define REG_BAR_MODE_CTRL 0x04CC 451#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 452#define REG_MACID_SLEEP2 0x04D0 453#define REG_MACID_SLEEP 0x04D4 454 455#define REG_HW_SEQ0 0x04D8 456#define REG_HW_SEQ1 0x04DA 457#define REG_HW_SEQ2 0x04DC 458#define REG_HW_SEQ3 0x04DE 459 460#define REG_NULL_PKT_STATUS_V1 0x04E0 461 462#define REG_PTCL_ERR_STATUS 0x04E2 463 464#define REG_NULL_PKT_STATUS_EXTEND 0x04E3 465 466#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 467 468#define REG_BT_POLLUTE_PKT_CNT 0x04E8 469#define REG_PTCL_DBG 0x04EC 470 471#define REG_CPUMGQ_TIMER_CTRL2 0x04F4 472 473#define REG_DUMMY_PAGE4_V1 0x04FC 474#define REG_MOREDATA 0x04FE 475 476#define REG_EDCA_VO_PARAM 0x0500 477#define REG_EDCA_VI_PARAM 0x0504 478#define REG_EDCA_BE_PARAM 0x0508 479#define REG_EDCA_BK_PARAM 0x050C 480#define REG_BCNTCFG 0x0510 481#define REG_PIFS 0x0512 482#define REG_RDG_PIFS 0x0513 483#define REG_SIFS 0x0514 484#define REG_TSFTR_SYN_OFFSET 0x0518 485#define REG_AGGR_BREAK_TIME 0x051A 486#define REG_SLOT 0x051B 487#define REG_TX_PTCL_CTRL 0x0520 488#define REG_TXPAUSE 0x0522 489#define REG_DIS_TXREQ_CLR 0x0523 490#define REG_RD_CTRL 0x0524 491#define REG_MBSSID_CTRL 0x0526 492#define REG_P2PPS_CTRL 0x0527 493#define REG_PKT_LIFETIME_CTRL 0x0528 494#define REG_P2PPS_SPEC_STATE 0x052B 495 496#define REG_BAR_TX_CTRL 0x0530 497 498#define REG_QUEUE_INCOL_THR 0x0538 499#define REG_QUEUE_INCOL_EN 0x053C 500 501#define REG_TBTT_PROHIBIT 0x0540 502#define REG_P2PPS_STATE 0x0543 503#define REG_RD_NAV_NXT 0x0544 504#define REG_NAV_PROT_LEN 0x0546 505 506#define REG_BCN_CTRL 0x0550 507 508#define REG_BCN_CTRL_CLINT0 0x0551 509 510#define REG_MBID_NUM 0x0552 511#define REG_DUAL_TSF_RST 0x0553 512#define REG_MBSSID_BCN_SPACE 0x0554 513#define REG_DRVERLYINT 0x0558 514#define REG_BCNDMATIM 0x0559 515#define REG_ATIMWND 0x055A 516#define REG_USTIME_TSF 0x055C 517#define REG_BCN_MAX_ERR 0x055D 518#define REG_RXTSF_OFFSET_CCK 0x055E 519#define REG_RXTSF_OFFSET_OFDM 0x055F 520#define REG_TSFTR 0x0560 521 522#define REG_FREERUN_CNT 0x0568 523 524#define REG_ATIMWND1_V1 0x0570 525 526#define REG_TBTT_PROHIBIT_INFRA 0x0571 527 528#define REG_CTWND 0x0572 529#define REG_BCNIVLCUNT 0x0573 530#define REG_BCNDROPCTRL 0x0574 531#define REG_HGQ_TIMEOUT_PERIOD 0x0575 532 533#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 534#define REG_MISC_CTRL 0x0577 535#define REG_BCN_CTRL_CLINT1 0x0578 536#define REG_BCN_CTRL_CLINT2 0x0579 537#define REG_BCN_CTRL_CLINT3 0x057A 538 539#define REG_EXTEND_CTRL 0x057B 540 541#define REG_P2PPS1_SPEC_STATE 0x057C 542#define REG_P2PPS1_STATE 0x057D 543#define REG_P2PPS2_SPEC_STATE 0x057E 544#define REG_P2PPS2_STATE 0x057F 545 546#define REG_PS_TIMER0 0x0580 547 548#define REG_PS_TIMER1 0x0584 549 550#define REG_PS_TIMER2 0x0588 551 552#define REG_TBTT_CTN_AREA 0x058C 553#define REG_FORCE_BCN_IFS 0x058E 554#define REG_TXOP_MIN 0x0590 555#define REG_PRE_BKF_TIME 0x0592 556#define REG_CROSS_TXOP_CTRL 0x0593 557 558#define REG_ATIMWND2 0x05A0 559#define REG_ATIMWND3 0x05A1 560#define REG_ATIMWND4 0x05A2 561#define REG_ATIMWND5 0x05A3 562#define REG_ATIMWND6 0x05A4 563#define REG_ATIMWND7 0x05A5 564#define REG_ATIMUGT 0x05A6 565#define REG_HIQ_NO_LMT_EN 0x05A7 566#define REG_DTIM_COUNTER_ROOT 0x05A8 567#define REG_DTIM_COUNTER_VAP1 0x05A9 568#define REG_DTIM_COUNTER_VAP2 0x05AA 569#define REG_DTIM_COUNTER_VAP3 0x05AB 570#define REG_DTIM_COUNTER_VAP4 0x05AC 571#define REG_DTIM_COUNTER_VAP5 0x05AD 572#define REG_DTIM_COUNTER_VAP6 0x05AE 573#define REG_DTIM_COUNTER_VAP7 0x05AF 574#define REG_DIS_ATIM 0x05B0 575 576#define REG_EARLY_128US 0x05B1 577#define REG_P2PPS1_CTRL 0x05B2 578#define REG_P2PPS2_CTRL 0x05B3 579#define REG_TIMER0_SRC_SEL 0x05B4 580#define REG_NOA_UNIT_SEL 0x05B5 581#define REG_P2POFF_DIS_TXTIME 0x05B7 582#define REG_MBSSID_BCN_SPACE2 0x05B8 583#define REG_MBSSID_BCN_SPACE3 0x05BC 584 585#define REG_ACMHWCTRL 0x05C0 586#define REG_ACMRSTCTRL 0x05C1 587#define REG_ACMAVG 0x05C2 588#define REG_VO_ADMTIME 0x05C4 589#define REG_VI_ADMTIME 0x05C6 590#define REG_BE_ADMTIME 0x05C8 591#define REG_EDCA_RANDOM_GEN 0x05CC 592#define REG_TXCMD_NOA_SEL 0x05CF 593#define REG_NOA_PARAM 0x05E0 594 595#define REG_P2P_RST 0x05F0 596#define REG_SCHEDULER_RST 0x05F1 597 598#define REG_SCH_TXCMD 0x05F8 599#define REG_PAGE5_DUMMY 0x05FC 600#define REG_WMAC_CR 0x0600 601 602#define REG_WMAC_FWPKT_CR 0x0601 603 604#define REG_BWOPMODE 0x0603 605 606#define REG_TCR 0x0604 607#define REG_RCR 0x0608 608#define REG_RX_PKT_LIMIT 0x060C 609#define REG_RX_DLK_TIME 0x060D 610#define REG_RX_DRVINFO_SZ 0x060F 611#define REG_MACID 0x0610 612#define REG_BSSID 0x0618 613#define REG_MAR 0x0620 614#define REG_MBIDCAMCFG_1 0x0628 615#define REG_MBIDCAMCFG_2 0x062C 616 617#define REG_WMAC_TCR_TSFT_OFS 0x0630 618#define REG_UDF_THSD 0x0632 619#define REG_ZLD_NUM 0x0633 620 621#define REG_STMP_THSD 0x0634 622#define REG_WMAC_TXTIMEOUT 0x0635 623#define REG_MCU_TEST_2_V1 0x0636 624 625#define REG_USTIME_EDCA 0x0638 626 627#define REG_MAC_SPEC_SIFS 0x063A 628#define REG_RESP_SIFS_CCK 0x063C 629#define REG_RESP_SIFS_OFDM 0x063E 630#define REG_ACKTO 0x0640 631#define REG_CTS2TO 0x0641 632#define REG_EIFS 0x0642 633 634#define REG_NAV_CTRL 0x0650 635#define REG_BACAMCMD 0x0654 636#define REG_BACAMCONTENT 0x0658 637#define REG_LBDLY 0x0660 638 639#define REG_WMAC_BACAM_RPMEN 0x0661 640 641#define REG_TX_RX 0x0662 642 643#define REG_WMAC_BITMAP_CTL 0x0663 644 645#define REG_RXERR_RPT 0x0664 646#define REG_WMAC_TRXPTCL_CTL 0x0668 647#define REG_CAMCMD 0x0670 648#define REG_CAMWRITE 0x0674 649#define REG_CAMREAD 0x0678 650#define REG_CAMDBG 0x067C 651#define REG_SECCFG 0x0680 652 653#define REG_RXFILTER_CATEGORY_1 0x0682 654#define REG_RXFILTER_ACTION_1 0x0683 655#define REG_RXFILTER_CATEGORY_2 0x0684 656#define REG_RXFILTER_ACTION_2 0x0685 657#define REG_RXFILTER_CATEGORY_3 0x0686 658#define REG_RXFILTER_ACTION_3 0x0687 659#define REG_RXFLTMAP3 0x0688 660#define REG_RXFLTMAP4 0x068A 661#define REG_RXFLTMAP5 0x068C 662#define REG_RXFLTMAP6 0x068E 663 664#define REG_WOW_CTRL 0x0690 665 666#define REG_NAN_RX_TSF_FILTER 0x0691 667 668#define REG_PS_RX_INFO 0x0692 669#define REG_WMMPS_UAPSD_TID 0x0693 670#define REG_LPNAV_CTRL 0x0694 671 672#define REG_WKFMCAM_CMD 0x0698 673#define REG_WKFMCAM_RWD 0x069C 674 675#define REG_RXFLTMAP0 0x06A0 676#define REG_RXFLTMAP1 0x06A2 677#define REG_RXFLTMAP 0x06A4 678#define REG_BCN_PSR_RPT 0x06A8 679 680#define REG_FLC_RPC 0x06AC 681#define REG_FLC_RPCT 0x06AD 682#define REG_FLC_PTS 0x06AE 683#define REG_FLC_TRPC 0x06AF 684 685#define REG_RXPKTMON_CTRL 0x06B0 686 687#define REG_STATE_MON 0x06B4 688 689#define REG_ERROR_MON 0x06B8 690#define REG_SEARCH_MACID 0x06BC 691 692#define REG_BT_COEX_TABLE 0x06C0 693 694#define REG_RXCMD_0 0x06D0 695#define REG_RXCMD_1 0x06D4 696 697#define REG_WMAC_RESP_TXINFO 0x06D8 698 699#define REG_BBPSF_CTRL 0x06DC 700 701#define REG_P2P_RX_BCN_NOA 0x06E0 702#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 703#define REG_ASSOCIATED_BFMER1_INFO 0x06EC 704#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 705#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 706#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC 707#define REG_MACID1 0x0700 708 709#define REG_BSSID1 0x0708 710 711#define REG_BCN_PSR_RPT1 0x0710 712#define REG_ASSOCIATED_BFMEE_SEL 0x0714 713#define REG_SND_PTCL_CTRL 0x0718 714#define REG_RX_CSI_RPT_INFO 0x071C 715#define REG_NS_ARP_CTRL 0x0720 716#define REG_NS_ARP_INFO 0x0724 717 718#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728 719 720#define REG_BEAMFORMING_INFO_NSARP 0x072C 721 722#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 723 724#define REG_WMAC_SWAES_CFG 0x0760 725 726#define REG_BT_COEX_V2 0x0762 727 728#define REG_BT_COEX 0x0764 729 730#define REG_WLAN_ACT_MASK_CTRL 0x0768 731 732#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E 733 734#define REG_BT_ACT_STATISTICS 0x0770 735 736#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778 737 738#define REG_BT_STATUS_REPORT_REGISTER 0x077C 739 740#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780 741 742#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784 743 744#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785 745 746#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F 747 748#define REG_BT_TDMA_TIME_REGISTER 0x0790 749 750#define REG_BT_ACT_REGISTER 0x0794 751 752#define REG_OBFF_CTRL_BASIC 0x0798 753 754#define REG_OBFF_CTRL2_TIMER 0x079C 755 756#define REG_LTR_CTRL_BASIC 0x07A0 757 758#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4 759 760#define REG_LTR_IDLE_LATENCY_V1 0x07A8 761#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC 762 763#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0 764 765#define REG_WMAC_PKTCNT_RWD 0x07B8 766#define REG_WMAC_PKTCNT_CTRL 0x07BC 767 768#define REG_IQ_DUMP 0x07C0 769 770#define REG_WMAC_FTM_CTL 0x07CC 771 772#define REG_WMAC_IQ_MDPK_FUNC 0x07CE 773 774#define REG_WMAC_OPTION_FUNCTION 0x07D0 775 776#define REG_RX_FILTER_FUNCTION 0x07DA 777 778#define REG_NDP_SIG 0x07E0 779#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 780 781#define REG_RTS_ADDRESS_0 0x07F0 782 783#define REG_RTS_ADDRESS_1 0x07F8 784 785#define REG__RPFM_MAP1 0x07FE 786 787#define REG_SYS_CFG3 0x1000 788#define REG_SYS_CFG4 0x1034 789 790#define REG_SYS_CFG5 0x1070 791 792#define REG_CPU_DMEM_CON 0x1080 793 794#define REG_BOOT_REASON 0x1088 795#define REG_NFCPAD_CTRL 0x10A8 796 797#define REG_HIMR2 0x10B0 798#define REG_HISR2 0x10B4 799#define REG_HIMR3 0x10B8 800#define REG_HISR3 0x10BC 801#define REG_SW_MDIO 0x10C0 802#define REG_SW_FLUSH 0x10C4 803 804#define REG_H2C_PKT_READADDR 0x10D0 805#define REG_H2C_PKT_WRITEADDR 0x10D4 806 807#define REG_MEM_PWR_CRTL 0x10D8 808 809#define REG_FW_DBG0 0x10E0 810#define REG_FW_DBG1 0x10E4 811#define REG_FW_DBG2 0x10E8 812#define REG_FW_DBG3 0x10EC 813#define REG_FW_DBG4 0x10F0 814#define REG_FW_DBG5 0x10F4 815#define REG_FW_DBG6 0x10F8 816#define REG_FW_DBG7 0x10FC 817#define REG_CR_EXT 0x1100 818#define REG_FWFF 0x1114 819 820#define REG_RXFF_PTR_V1 0x1118 821#define REG_RXFF_WTR_V1 0x111C 822 823#define REG_FE2IMR 0x1120 824#define REG_FE2ISR 0x1124 825#define REG_FE3IMR 0x1128 826#define REG_FE3ISR 0x112C 827#define REG_FE4IMR 0x1130 828#define REG_FE4ISR 0x1134 829#define REG_FT1IMR 0x1138 830#define REG_FT1ISR 0x113C 831#define REG_SPWR0 0x1140 832#define REG_SPWR1 0x1144 833#define REG_SPWR2 0x1148 834#define REG_SPWR3 0x114C 835#define REG_POWSEQ 0x1150 836 837#define REG_TC7_CTRL_V1 0x1158 838#define REG_TC8_CTRL_V1 0x115C 839 840#define REG_FT2IMR 0x11E0 841#define REG_FT2ISR 0x11E4 842 843#define REG_MSG2 0x11F0 844#define REG_MSG3 0x11F4 845#define REG_MSG4 0x11F8 846#define REG_MSG5 0x11FC 847#define REG_DDMA_CH0SA 0x1200 848#define REG_DDMA_CH0DA 0x1204 849#define REG_DDMA_CH0CTRL 0x1208 850#define REG_DDMA_CH1SA 0x1210 851#define REG_DDMA_CH1DA 0x1214 852#define REG_DDMA_CH1CTRL 0x1218 853#define REG_DDMA_CH2SA 0x1220 854#define REG_DDMA_CH2DA 0x1224 855#define REG_DDMA_CH2CTRL 0x1228 856#define REG_DDMA_CH3SA 0x1230 857#define REG_DDMA_CH3DA 0x1234 858#define REG_DDMA_CH3CTRL 0x1238 859#define REG_DDMA_CH4SA 0x1240 860#define REG_DDMA_CH4DA 0x1244 861#define REG_DDMA_CH4CTRL 0x1248 862#define REG_DDMA_CH5SA 0x1250 863#define REG_DDMA_CH5DA 0x1254 864 865#define REG_REG_DDMA_CH5CTRL 0x1258 866 867#define REG_DDMA_INT_MSK 0x12E0 868#define REG_DDMA_CHSTATUS 0x12E8 869#define REG_DDMA_CHKSUM 0x12F0 870#define REG_DDMA_MONITOR 0x12FC 871 872#define REG_STC_INT_CS 0x1300 873#define REG_ST_INT_CFG 0x1304 874#define REG_CMU_DLY_CTRL 0x1310 875#define REG_CMU_DLY_CFG 0x1314 876#define REG_H2CQ_TXBD_DESA 0x1320 877#define REG_H2CQ_TXBD_NUM 0x1328 878#define REG_H2CQ_TXBD_IDX 0x132C 879#define REG_H2CQ_CSR 0x1330 880 881#define REG_CHANGE_PCIE_SPEED 0x1350 882 883#define REG_OLD_DEHANG 0x13F4 884 885#define REG_Q0_Q1_INFO 0x1400 886#define REG_Q2_Q3_INFO 0x1404 887#define REG_Q4_Q5_INFO 0x1408 888#define REG_Q6_Q7_INFO 0x140C 889#define REG_MGQ_HIQ_INFO 0x1410 890#define REG_CMDQ_BCNQ_INFO 0x1414 891#define REG_USEREG_SETTING 0x1420 892#define REG_AESIV_SETTING 0x1424 893#define REG_BF0_TIME_SETTING 0x1428 894#define REG_BF1_TIME_SETTING 0x142C 895#define REG_BF_TIMEOUT_EN 0x1430 896#define REG_MACID_RELEASE0 0x1434 897#define REG_MACID_RELEASE1 0x1438 898#define REG_MACID_RELEASE2 0x143C 899#define REG_MACID_RELEASE3 0x1440 900#define REG_MACID_RELEASE_SETTING 0x1444 901#define REG_FAST_EDCA_VOVI_SETTING 0x1448 902#define REG_FAST_EDCA_BEBK_SETTING 0x144C 903#define REG_MACID_DROP0 0x1450 904#define REG_MACID_DROP1 0x1454 905#define REG_MACID_DROP2 0x1458 906#define REG_MACID_DROP3 0x145C 907 908#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460 909#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464 910#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468 911#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C 912#define REG_MGG_FIFO_CRTL 0x1470 913#define REG_MGG_FIFO_INT 0x1474 914#define REG_MGG_FIFO_LIFETIME 0x1478 915#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C 916 917#define REG_MACID_SHCUT_OFFSET 0x1480 918 919#define REG_MU_TX_CTL 0x14C0 920#define REG_MU_STA_GID_VLD 0x14C4 921#define REG_MU_STA_USER_POS_INFO 0x14C8 922#define REG_MU_TRX_DBG_CNT 0x14D0 923 924#define REG_CPUMGQ_TX_TIMER 0x1500 925#define REG_PS_TIMER_A 0x1504 926#define REG_PS_TIMER_B 0x1508 927#define REG_PS_TIMER_C 0x150C 928#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510 929#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514 930#define REG_PS_TIMER_A_EARLY 0x1515 931#define REG_PS_TIMER_B_EARLY 0x1516 932#define REG_PS_TIMER_C_EARLY 0x1517 933 934#define REG_BCN_PSR_RPT2 0x1600 935#define REG_BCN_PSR_RPT3 0x1604 936#define REG_BCN_PSR_RPT4 0x1608 937#define REG_A1_ADDR_MASK 0x160C 938#define REG_MACID2 0x1620 939#define REG_BSSID2 0x1628 940#define REG_MACID3 0x1630 941#define REG_BSSID3 0x1638 942#define REG_MACID4 0x1640 943#define REG_BSSID4 0x1648 944 945#define REG_NOA_REPORT 0x1650 946#define REG_PWRBIT_SETTING 0x1660 947#define REG_WMAC_MU_BF_OPTION 0x167C 948 949#define REG_WMAC_MU_ARB 0x167E 950#define REG_WMAC_MU_OPTION 0x167F 951#define REG_WMAC_MU_BF_CTL 0x1680 952 953#define REG_WMAC_MU_BFRPT_PARA 0x1682 954 955#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684 956#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686 957#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688 958#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A 959#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C 960#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E 961 962#define REG_TRANSMIT_ADDRSS_0 0x16A0 963#define REG_TRANSMIT_ADDRSS_1 0x16A8 964#define REG_TRANSMIT_ADDRSS_2 0x16B0 965#define REG_TRANSMIT_ADDRSS_3 0x16B8 966#define REG_TRANSMIT_ADDRSS_4 0x16C0 967 968#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 969#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 970#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 971 972/* ----------------------------------------------------- */ 973/* */ 974/* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */ 975/* */ 976/* ----------------------------------------------------- */ 977#define REG_RXPKTBUF_STARTADDR 0xFB00 978#define REG_TXPKTBUF_STARTADDR 0xFC00 979 980/* ----------------------------------------------------- */ 981/* */ 982/* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */ 983/* */ 984/* ----------------------------------------------------- */ 985#define REG_SYS_CTRL 0xFD00 986#define REG_PONSTS_RPT1 0xFD01 987#define REG_PONSTS_RPT2 0xFD02 988#define REG_PONSTS_RPT3 0xFD03 989#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */ 990#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */ 991#define REG_8051ERRFLAG 0xFD08 992#define REG_8051ERRFLAG_MASK 0xFD09 993#define REG_TXADDRH 0xFD10 /* Tx Packet High address */ 994#define REG_RXADDRH 0xFD11 /* Rx Packet High address */ 995#define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf 996 * high64k as external register 997 */ 998 999#define REG_U3_STATE 0xFD48 /* (Read only) 1000 * [7:4] : usb3 changed last state.
1001 * [3:0] : usb3 state 1002 */ 1003 1004/* for MAILBOX */ 1005#define REG_OUTDATA0 0xFD50 1006#define REG_OUTDATA1 0xFD54 1007#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, 1008 * bit[1] : OutEmptyIntEn 1009 */ 1010 1011#define REG_INDATA0 0xFD60 1012#define REG_INDATA1 0xFD64 1013#define REG_INRDY 0xFD68 /* bit[0] : InReady, 1014 * bit[1] : InRdyIntEn 1015 */ 1016 1017/* MCU ERROR debug REG */ 1018#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */ 1019#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */ 1020#define REG_MCUERR_ACC 0xFD92 1021#define REG_MCUERR_B 0xFD93 1022#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */ 1023#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */ 1024#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */ 1025#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */ 1026#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */ 1027#define REG_VERA_SIM 0xFD9F 1028/* 0xFD99~0xFD9F are reserved.. */ 1029 1030/* ----------------------------------------------------- */ 1031/* */ 1032/* 0xFE00h ~ 0xFEFFh USB Configuration */ 1033/* */ 1034/* ----------------------------------------------------- */ 1035 1036/* RTS5101 USB Register Definition */ 1037#define REG_USB_SETUP_DEC_INT 0xFE00 1038#define REG_USB_DMACTL 0xFE01 1039#define REG_USB_IRQSTAT0 0xFE02 1040#define REG_USB_IRQSTAT1 0xFE03 1041#define REG_USB_IRQEN0 0xFE04 1042#define REG_USB_IRQEN1 0xFE05 1043#define REG_USB_AUTOPTRL 0xFE06 1044#define REG_USB_AUTOPTRH 0xFE07 1045#define REG_USB_AUTODAT 0xFE08 1046 1047#define REG_USB_SCRATCH0 0xFE09 1048#define REG_USB_SCRATCH1 0xFE0A 1049#define REG_USB_SEEPROM 0xFE0B 1050#define REG_USB_GPIO0 0xFE0C 1051#define REG_USB_GPIO0DIR 0xFE0D 1052#define REG_USB_CLKSEL 0xFE0E 1053#define REG_USB_BOOTCTL 0xFE0F 1054 1055#define REG_USB_USBCTL 0xFE10 1056#define REG_USB_USBSTAT 0xFE11 1057#define REG_USB_DEVADDR 0xFE12 1058#define REG_USB_USBTEST 0xFE13 1059#define REG_USB_FNUM0 0xFE14 1060#define REG_USB_FNUM1 0xFE15 1061 1062#define REG_USB_EP_IDX 0xFE20 1063#define REG_USB_EP_CFG 0xFE21 1064#define REG_USB_EP_CTL 0xFE22 1065#define REG_USB_EP_STAT 0xFE23 1066#define REG_USB_EP_IRQ 0xFE24 1067#define REG_USB_EP_IRQEN 0xFE25 1068#define REG_USB_EP_MAXPKT0 0xFE26 1069#define REG_USB_EP_MAXPKT1 0xFE27 1070#define REG_USB_EP_DAT 0xFE28 1071#define REG_USB_EP_BC0 0xFE29 1072#define REG_USB_EP_BC1 0xFE2A 1073#define REG_USB_EP_TC0 0xFE2B 1074#define REG_USB_EP_TC1 0xFE2C 1075#define REG_USB_EP_TC2 0xFE2D 1076#define REG_USB_EP_CTL2 0xFE2E 1077 1078#define REG_USB_INFO 0xFE17 1079#define REG_USB_SPECIAL_OPTION 0xFE55 1080#define REG_USB_DMA_AGG_TO 0xFE5B 1081#define REG_USB_AGG_TO 0xFE5C 1082#define REG_USB_AGG_TH 0xFE5D 1083 1084#define REG_USB_VID 0xFE60 1085#define REG_USB_PID 0xFE62 1086#define REG_USB_OPT 0xFE64 1087#define REG_USB_CONFIG 0xFE65 /* RX EP setting. 1088 * 0xFE65 Bit[3:0] : RXQ, 1089 * Bit[7:4] : INTQ 1090 */ 1091 /* TX EP setting. 1092 * 0xFE66 Bit[3:0] : TXQ0, 1093 * Bit[7:4] : TXQ1, 1094 * 0xFE67 Bit[3:0] : TXQ2 1095 */ 1096#define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]), 1097 * Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0]) 1098 */ 1099#define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]), 1100 * Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]), 1101 * Bit[1]: SE0_LVL (USB PHY 0xE5[7]), 1102 * Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1]) 1103 */ 1104#define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]), 1105 * Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]), 1106 * Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]), 1107 * Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]), 1108 * Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1]) 1109 */ 1110#define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */ 1111#define REG_USB_OPT2 0xFE6C 1112#define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ 1113#define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max: 32 bytes*/ 1114#define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max: 48 bytes*/ 1115#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max: 12 bytes*/ 1116 1117#define REG_USB_ALTERNATE_SETTING 0xFE4F 1118#define REG_USB_INT_BINTERVAL 0xFE6E 1119#define REG_USB_GPS_EP_CONFIG 0xFE6D 1120 1121#endif /* __HALMAC_COM_REG_H__ */ 1122