1
2
3
4
5
6
7
8
9
10
11#ifndef __DRIVERS_USB_DWC3_CORE_H
12#define __DRIVERS_USB_DWC3_CORE_H
13
14#include <linux/device.h>
15#include <linux/spinlock.h>
16#include <linux/ioport.h>
17#include <linux/list.h>
18#include <linux/bitops.h>
19#include <linux/dma-mapping.h>
20#include <linux/mm.h>
21#include <linux/debugfs.h>
22#include <linux/wait.h>
23#include <linux/workqueue.h>
24
25#include <linux/usb/ch9.h>
26#include <linux/usb/gadget.h>
27#include <linux/usb/otg.h>
28#include <linux/ulpi/interface.h>
29
30#include <linux/phy/phy.h>
31
32#define DWC3_MSG_MAX 500
33
34
35#define DWC3_PULL_UP_TIMEOUT 500
36#define DWC3_BOUNCE_SIZE 1024
37#define DWC3_EP0_SETUP_SIZE 512
38#define DWC3_ENDPOINTS_NUM 32
39#define DWC3_XHCI_RESOURCES_NUM 2
40#define DWC3_ISOC_MAX_RETRIES 5
41
42#define DWC3_SCRATCHBUF_SIZE 4096
43#define DWC3_EVENT_BUFFERS_SIZE 4096
44#define DWC3_EVENT_TYPE_MASK 0xfe
45
46#define DWC3_EVENT_TYPE_DEV 0
47#define DWC3_EVENT_TYPE_CARKIT 3
48#define DWC3_EVENT_TYPE_I2C 4
49
50#define DWC3_DEVICE_EVENT_DISCONNECT 0
51#define DWC3_DEVICE_EVENT_RESET 1
52#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
53#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
54#define DWC3_DEVICE_EVENT_WAKEUP 4
55#define DWC3_DEVICE_EVENT_HIBER_REQ 5
56#define DWC3_DEVICE_EVENT_EOPF 6
57#define DWC3_DEVICE_EVENT_SOF 7
58#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
59#define DWC3_DEVICE_EVENT_CMD_CMPL 10
60#define DWC3_DEVICE_EVENT_OVERFLOW 11
61
62
63#define DWC3_OTG_ROLE_IDLE 0
64#define DWC3_OTG_ROLE_HOST 1
65#define DWC3_OTG_ROLE_DEVICE 2
66
67#define DWC3_GEVNTCOUNT_MASK 0xfffc
68#define DWC3_GEVNTCOUNT_EHB BIT(31)
69#define DWC3_GSNPSID_MASK 0xffff0000
70#define DWC3_GSNPSREV_MASK 0xffff
71
72
73#define DWC3_XHCI_REGS_START 0x0
74#define DWC3_XHCI_REGS_END 0x7fff
75#define DWC3_GLOBALS_REGS_START 0xc100
76#define DWC3_GLOBALS_REGS_END 0xc6ff
77#define DWC3_DEVICE_REGS_START 0xc700
78#define DWC3_DEVICE_REGS_END 0xcbff
79#define DWC3_OTG_REGS_START 0xcc00
80#define DWC3_OTG_REGS_END 0xccff
81
82
83#define DWC3_GSBUSCFG0 0xc100
84#define DWC3_GSBUSCFG1 0xc104
85#define DWC3_GTXTHRCFG 0xc108
86#define DWC3_GRXTHRCFG 0xc10c
87#define DWC3_GCTL 0xc110
88#define DWC3_GEVTEN 0xc114
89#define DWC3_GSTS 0xc118
90#define DWC3_GUCTL1 0xc11c
91#define DWC3_GSNPSID 0xc120
92#define DWC3_GGPIO 0xc124
93#define DWC3_GUID 0xc128
94#define DWC3_GUCTL 0xc12c
95#define DWC3_GBUSERRADDR0 0xc130
96#define DWC3_GBUSERRADDR1 0xc134
97#define DWC3_GPRTBIMAP0 0xc138
98#define DWC3_GPRTBIMAP1 0xc13c
99#define DWC3_GHWPARAMS0 0xc140
100#define DWC3_GHWPARAMS1 0xc144
101#define DWC3_GHWPARAMS2 0xc148
102#define DWC3_GHWPARAMS3 0xc14c
103#define DWC3_GHWPARAMS4 0xc150
104#define DWC3_GHWPARAMS5 0xc154
105#define DWC3_GHWPARAMS6 0xc158
106#define DWC3_GHWPARAMS7 0xc15c
107#define DWC3_GDBGFIFOSPACE 0xc160
108#define DWC3_GDBGLTSSM 0xc164
109#define DWC3_GDBGBMU 0xc16c
110#define DWC3_GDBGLSPMUX 0xc170
111#define DWC3_GDBGLSP 0xc174
112#define DWC3_GDBGEPINFO0 0xc178
113#define DWC3_GDBGEPINFO1 0xc17c
114#define DWC3_GPRTBIMAP_HS0 0xc180
115#define DWC3_GPRTBIMAP_HS1 0xc184
116#define DWC3_GPRTBIMAP_FS0 0xc188
117#define DWC3_GPRTBIMAP_FS1 0xc18c
118#define DWC3_GUCTL2 0xc19c
119
120#define DWC3_VER_NUMBER 0xc1a0
121#define DWC3_VER_TYPE 0xc1a4
122
123#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
124#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
125
126#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
127
128#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
129
130#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
131#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
132
133#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
134#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
135#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
136#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
137
138#define DWC3_GHWPARAMS8 0xc600
139#define DWC3_GFLADJ 0xc630
140
141
142#define DWC3_DCFG 0xc700
143#define DWC3_DCTL 0xc704
144#define DWC3_DEVTEN 0xc708
145#define DWC3_DSTS 0xc70c
146#define DWC3_DGCMDPAR 0xc710
147#define DWC3_DGCMD 0xc714
148#define DWC3_DALEPENA 0xc720
149
150#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
151#define DWC3_DEPCMDPAR2 0x00
152#define DWC3_DEPCMDPAR1 0x04
153#define DWC3_DEPCMDPAR0 0x08
154#define DWC3_DEPCMD 0x0c
155
156#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
157
158
159#define DWC3_OCFG 0xcc00
160#define DWC3_OCTL 0xcc04
161#define DWC3_OEVT 0xcc08
162#define DWC3_OEVTEN 0xcc0C
163#define DWC3_OSTS 0xcc10
164
165
166
167
168#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7)
169#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6)
170#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5)
171#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4)
172#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3)
173#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2)
174#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1)
175#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0)
176#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
177
178
179#define DWC3_GDBGLSPMUX_ENDBC BIT(15)
180#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
181#define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
182#define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
183
184
185#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
186#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
187#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
188
189#define DWC3_TXFIFO 0
190#define DWC3_RXFIFO 1
191#define DWC3_TXREQQ 2
192#define DWC3_RXREQQ 3
193#define DWC3_RXINFOQ 4
194#define DWC3_PSTATQ 5
195#define DWC3_DESCFETCHQ 6
196#define DWC3_EVENTQ 7
197#define DWC3_AUXEVENTQ 8
198
199
200#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
201#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
202#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
203
204
205#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
206#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
207#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
208#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
209#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
210#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
211#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
212#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
213
214
215#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
216#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
217#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
218#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
219#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
220#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
221#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
222#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
223
224
225#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
226#define DWC3_GCTL_U2RSTECN BIT(16)
227#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
228#define DWC3_GCTL_CLK_BUS (0)
229#define DWC3_GCTL_CLK_PIPE (1)
230#define DWC3_GCTL_CLK_PIPEHALF (2)
231#define DWC3_GCTL_CLK_MASK (3)
232
233#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
234#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
235#define DWC3_GCTL_PRTCAP_HOST 1
236#define DWC3_GCTL_PRTCAP_DEVICE 2
237#define DWC3_GCTL_PRTCAP_OTG 3
238
239#define DWC3_GCTL_CORESOFTRESET BIT(11)
240#define DWC3_GCTL_SOFITPSYNC BIT(10)
241#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
242#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
243#define DWC3_GCTL_DISSCRAMBLE BIT(3)
244#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
245#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
246#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
247
248
249#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
250
251
252#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
253#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
254
255
256#define DWC3_GSTS_OTG_IP BIT(10)
257#define DWC3_GSTS_BC_IP BIT(9)
258#define DWC3_GSTS_ADP_IP BIT(8)
259#define DWC3_GSTS_HOST_IP BIT(7)
260#define DWC3_GSTS_DEVICE_IP BIT(6)
261#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
262#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
263#define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
264#define DWC3_GSTS_CURMOD_DEVICE 0
265#define DWC3_GSTS_CURMOD_HOST 1
266
267
268#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
269#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
270#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
271#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
272#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
273#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
274#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
275#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
276#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
277#define USBTRDTIM_UTMI_8_BIT 9
278#define USBTRDTIM_UTMI_16_BIT 5
279#define UTMI_PHYIF_16_BIT 1
280#define UTMI_PHYIF_8_BIT 0
281
282
283#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
284#define DWC3_GUSB2PHYACC_BUSY BIT(23)
285#define DWC3_GUSB2PHYACC_WRITE BIT(22)
286#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
287#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
288#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
289
290
291#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
292#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
293#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
294#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
295#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
296#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
297#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
298#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
299#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
300#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
301#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
302#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
303#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
304#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
305
306
307#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15)
308#define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff)
309#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
310#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
311
312
313#define DWC3_GEVNTSIZ_INTMASK BIT(31)
314#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
315
316
317#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
318#define DWC3_GHWPARAMS0_MODE_GADGET 0
319#define DWC3_GHWPARAMS0_MODE_HOST 1
320#define DWC3_GHWPARAMS0_MODE_DRD 2
321#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
322#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
323#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
324#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
325#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
326
327
328#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
329#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
330#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
331#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
332#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
333#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
334#define DWC3_GHWPARAMS1_ENDBC BIT(31)
335
336
337#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
338#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
339#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
340#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2
341#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
342#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
343#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
344#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
345#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
346#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
347#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
348#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
349
350
351#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
352#define DWC3_MAX_HIBER_SCRATCHBUFS 15
353
354
355#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
356#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
357#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
358#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
359#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
360#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
361
362
363#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
364#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
365
366
367#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
368#define DWC3_GFLADJ_30MHZ_MASK 0x3f
369
370
371#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
372
373
374#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
375#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
376
377#define DWC3_DCFG_SPEED_MASK (7 << 0)
378#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)
379#define DWC3_DCFG_SUPERSPEED (4 << 0)
380#define DWC3_DCFG_HIGHSPEED (0 << 0)
381#define DWC3_DCFG_FULLSPEED BIT(0)
382#define DWC3_DCFG_LOWSPEED (2 << 0)
383
384#define DWC3_DCFG_NUMP_SHIFT 17
385#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
386#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
387#define DWC3_DCFG_LPM_CAP BIT(22)
388
389
390#define DWC3_DCTL_RUN_STOP BIT(31)
391#define DWC3_DCTL_CSFTRST BIT(30)
392#define DWC3_DCTL_LSFTRST BIT(29)
393
394#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
395#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
396
397#define DWC3_DCTL_APPL1RES BIT(23)
398
399
400#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
401#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
402#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
403#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
404#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
405#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
406#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
407
408
409#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
410#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
411
412#define DWC3_DCTL_KEEP_CONNECT BIT(19)
413#define DWC3_DCTL_L1_HIBER_EN BIT(18)
414#define DWC3_DCTL_CRS BIT(17)
415#define DWC3_DCTL_CSS BIT(16)
416
417#define DWC3_DCTL_INITU2ENA BIT(12)
418#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
419#define DWC3_DCTL_INITU1ENA BIT(10)
420#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
421#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
422
423#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
424#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
425
426#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
427#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
428#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
429#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
430#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
431#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
432#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
433
434
435#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
436#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
437#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
438#define DWC3_DEVTEN_ERRTICERREN BIT(9)
439#define DWC3_DEVTEN_SOFEN BIT(7)
440#define DWC3_DEVTEN_EOPFEN BIT(6)
441#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
442#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
443#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
444#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
445#define DWC3_DEVTEN_USBRSTEN BIT(1)
446#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
447
448
449#define DWC3_DSTS_DCNRD BIT(29)
450
451
452#define DWC3_DSTS_PWRUPREQ BIT(24)
453
454
455#define DWC3_DSTS_RSS BIT(25)
456#define DWC3_DSTS_SSS BIT(24)
457
458#define DWC3_DSTS_COREIDLE BIT(23)
459#define DWC3_DSTS_DEVCTRLHLT BIT(22)
460
461#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
462#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
463
464#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
465
466#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
467#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
468
469#define DWC3_DSTS_CONNECTSPD (7 << 0)
470
471#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0)
472#define DWC3_DSTS_SUPERSPEED (4 << 0)
473#define DWC3_DSTS_HIGHSPEED (0 << 0)
474#define DWC3_DSTS_FULLSPEED BIT(0)
475#define DWC3_DSTS_LOWSPEED (2 << 0)
476
477
478#define DWC3_DGCMD_SET_LMP 0x01
479#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
480#define DWC3_DGCMD_XMIT_FUNCTION 0x03
481
482
483#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
484#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
485
486#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
487#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
488#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
489#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
490
491#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
492#define DWC3_DGCMD_CMDACT BIT(10)
493#define DWC3_DGCMD_CMDIOC BIT(8)
494
495
496#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
497#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
498#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
499#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
500#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
501#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
502
503
504#define DWC3_DEPCMD_PARAM_SHIFT 16
505#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
506#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
507#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
508#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
509#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
510#define DWC3_DEPCMD_CMDACT BIT(10)
511#define DWC3_DEPCMD_CMDIOC BIT(8)
512
513#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
514#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
515#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
516#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
517#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
518#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
519
520#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
521
522#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
523#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
524#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
525
526#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
527
528
529#define DWC3_DALEPENA_EP(n) BIT(n)
530
531#define DWC3_DEPCMD_TYPE_CONTROL 0
532#define DWC3_DEPCMD_TYPE_ISOC 1
533#define DWC3_DEPCMD_TYPE_BULK 2
534#define DWC3_DEPCMD_TYPE_INTR 3
535
536#define DWC3_DEV_IMOD_COUNT_SHIFT 16
537#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
538#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
539#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
540
541
542#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
543#define DWC3_OCFG_HIBDISMASK BIT(4)
544#define DWC3_OCFG_SFTRSTMASK BIT(3)
545#define DWC3_OCFG_OTGVERSION BIT(2)
546#define DWC3_OCFG_HNPCAP BIT(1)
547#define DWC3_OCFG_SRPCAP BIT(0)
548
549
550#define DWC3_OCTL_OTG3GOERR BIT(7)
551#define DWC3_OCTL_PERIMODE BIT(6)
552#define DWC3_OCTL_PRTPWRCTL BIT(5)
553#define DWC3_OCTL_HNPREQ BIT(4)
554#define DWC3_OCTL_SESREQ BIT(3)
555#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
556#define DWC3_OCTL_DEVSETHNPEN BIT(1)
557#define DWC3_OCTL_HSTSETHNPEN BIT(0)
558
559
560#define DWC3_OEVT_DEVICEMODE BIT(31)
561#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
562#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
563#define DWC3_OEVT_HIBENTRY BIT(25)
564#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
565#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
566#define DWC3_OEVT_HRRINITNOTIF BIT(22)
567#define DWC3_OEVT_ADEVIDLE BIT(21)
568#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
569#define DWC3_OEVT_ADEVHOST BIT(19)
570#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
571#define DWC3_OEVT_ADEVSRPDET BIT(17)
572#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
573#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
574#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
575#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
576#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
577#define DWC3_OEVT_BSESSVLD BIT(3)
578#define DWC3_OEVT_HSTNEGSTS BIT(2)
579#define DWC3_OEVT_SESREQSTS BIT(1)
580#define DWC3_OEVT_ERROR BIT(0)
581
582
583#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
584#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
585#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
586#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
587#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
588#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
589#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
590#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
591#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
592#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
593#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
594#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
595#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
596#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
597#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
598#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
599
600
601#define DWC3_OSTS_DEVRUNSTP BIT(13)
602#define DWC3_OSTS_XHCIRUNSTP BIT(12)
603#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
604#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
605#define DWC3_OSTS_BSESVLD BIT(2)
606#define DWC3_OSTS_VBUSVLD BIT(1)
607#define DWC3_OSTS_CONIDSTS BIT(0)
608
609
610
611struct dwc3_trb;
612
613
614
615
616
617
618
619
620
621
622
623
624struct dwc3_event_buffer {
625 void *buf;
626 void *cache;
627 unsigned length;
628 unsigned int lpos;
629 unsigned int count;
630 unsigned int flags;
631
632#define DWC3_EVENT_PENDING BIT(0)
633
634 dma_addr_t dma;
635
636 struct dwc3 *dwc;
637};
638
639#define DWC3_EP_FLAG_STALLED BIT(0)
640#define DWC3_EP_FLAG_WEDGED BIT(1)
641
642#define DWC3_EP_DIRECTION_TX true
643#define DWC3_EP_DIRECTION_RX false
644
645#define DWC3_TRB_NUM 256
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675struct dwc3_ep {
676 struct usb_ep endpoint;
677 struct list_head cancelled_list;
678 struct list_head pending_list;
679 struct list_head started_list;
680
681 spinlock_t lock;
682 void __iomem *regs;
683
684 struct dwc3_trb *trb_pool;
685 dma_addr_t trb_pool_dma;
686 struct dwc3 *dwc;
687
688 u32 saved_state;
689 unsigned flags;
690#define DWC3_EP_ENABLED BIT(0)
691#define DWC3_EP_STALL BIT(1)
692#define DWC3_EP_WEDGE BIT(2)
693#define DWC3_EP_TRANSFER_STARTED BIT(3)
694#define DWC3_EP_PENDING_REQUEST BIT(5)
695
696
697#define DWC3_EP0_DIR_IN BIT(31)
698
699
700
701
702
703
704
705
706
707
708 u8 trb_enqueue;
709 u8 trb_dequeue;
710
711 u8 number;
712 u8 type;
713 u8 resource_index;
714 u32 frame_number;
715 u32 interval;
716
717 char name[20];
718
719 unsigned direction:1;
720 unsigned stream_capable:1;
721
722
723 u8 combo_num;
724 int start_cmd_status;
725};
726
727enum dwc3_phy {
728 DWC3_PHY_UNKNOWN = 0,
729 DWC3_PHY_USB3,
730 DWC3_PHY_USB2,
731};
732
733enum dwc3_ep0_next {
734 DWC3_EP0_UNKNOWN = 0,
735 DWC3_EP0_COMPLETE,
736 DWC3_EP0_NRDY_DATA,
737 DWC3_EP0_NRDY_STATUS,
738};
739
740enum dwc3_ep0_state {
741 EP0_UNCONNECTED = 0,
742 EP0_SETUP_PHASE,
743 EP0_DATA_PHASE,
744 EP0_STATUS_PHASE,
745};
746
747enum dwc3_link_state {
748
749 DWC3_LINK_STATE_U0 = 0x00,
750 DWC3_LINK_STATE_U1 = 0x01,
751 DWC3_LINK_STATE_U2 = 0x02,
752 DWC3_LINK_STATE_U3 = 0x03,
753 DWC3_LINK_STATE_SS_DIS = 0x04,
754 DWC3_LINK_STATE_RX_DET = 0x05,
755 DWC3_LINK_STATE_SS_INACT = 0x06,
756 DWC3_LINK_STATE_POLL = 0x07,
757 DWC3_LINK_STATE_RECOV = 0x08,
758 DWC3_LINK_STATE_HRESET = 0x09,
759 DWC3_LINK_STATE_CMPLY = 0x0a,
760 DWC3_LINK_STATE_LPBK = 0x0b,
761 DWC3_LINK_STATE_RESET = 0x0e,
762 DWC3_LINK_STATE_RESUME = 0x0f,
763 DWC3_LINK_STATE_MASK = 0x0f,
764};
765
766
767#define DWC3_TRB_SIZE_MASK (0x00ffffff)
768#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
769#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
770#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
771
772#define DWC3_TRBSTS_OK 0
773#define DWC3_TRBSTS_MISSED_ISOC 1
774#define DWC3_TRBSTS_SETUP_PENDING 2
775#define DWC3_TRB_STS_XFER_IN_PROG 4
776
777
778#define DWC3_TRB_CTRL_HWO BIT(0)
779#define DWC3_TRB_CTRL_LST BIT(1)
780#define DWC3_TRB_CTRL_CHN BIT(2)
781#define DWC3_TRB_CTRL_CSP BIT(3)
782#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
783#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
784#define DWC3_TRB_CTRL_IOC BIT(11)
785#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
786#define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
787
788#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
789#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
790#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
791#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
792#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
793#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
794#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
795#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
796#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
797
798
799
800
801
802
803
804
805struct dwc3_trb {
806 u32 bpl;
807 u32 bph;
808 u32 size;
809 u32 ctrl;
810} __packed;
811
812
813
814
815
816
817
818
819
820
821
822
823
824struct dwc3_hwparams {
825 u32 hwparams0;
826 u32 hwparams1;
827 u32 hwparams2;
828 u32 hwparams3;
829 u32 hwparams4;
830 u32 hwparams5;
831 u32 hwparams6;
832 u32 hwparams7;
833 u32 hwparams8;
834};
835
836
837#define DWC3_MODE(n) ((n) & 0x7)
838
839#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
840
841
842#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
843
844
845#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
846#define DWC3_NUM_EPS_MASK (0x3f << 12)
847#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
848 (DWC3_NUM_EPS_MASK)) >> 12)
849#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
850 (DWC3_NUM_IN_EPS_MASK)) >> 18)
851
852
853#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875struct dwc3_request {
876 struct usb_request request;
877 struct list_head list;
878 struct dwc3_ep *dep;
879 struct scatterlist *sg;
880 struct scatterlist *start_sg;
881
882 unsigned num_pending_sgs;
883 unsigned int num_queued_sgs;
884 unsigned remaining;
885
886 unsigned int status;
887#define DWC3_REQUEST_STATUS_QUEUED 0
888#define DWC3_REQUEST_STATUS_STARTED 1
889#define DWC3_REQUEST_STATUS_CANCELLED 2
890#define DWC3_REQUEST_STATUS_COMPLETED 3
891#define DWC3_REQUEST_STATUS_UNKNOWN -1
892
893 u8 epnum;
894 struct dwc3_trb *trb;
895 dma_addr_t trb_dma;
896
897 unsigned num_trbs;
898
899 unsigned needs_extra_trb:1;
900 unsigned direction:1;
901 unsigned mapped:1;
902};
903
904
905
906
907
908struct dwc3_scratchpad_array {
909 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
910};
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036struct dwc3 {
1037 struct work_struct drd_work;
1038 struct dwc3_trb *ep0_trb;
1039 void *bounce;
1040 void *scratchbuf;
1041 u8 *setup_buf;
1042 dma_addr_t ep0_trb_addr;
1043 dma_addr_t bounce_addr;
1044 dma_addr_t scratch_addr;
1045 struct dwc3_request ep0_usb_req;
1046 struct completion ep0_in_setup;
1047
1048
1049 spinlock_t lock;
1050
1051 struct device *dev;
1052 struct device *sysdev;
1053
1054 struct platform_device *xhci;
1055 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1056
1057 struct dwc3_event_buffer *ev_buf;
1058 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1059
1060 struct usb_gadget gadget;
1061 struct usb_gadget_driver *gadget_driver;
1062
1063 struct clk_bulk_data *clks;
1064 int num_clks;
1065
1066 struct reset_control *reset;
1067
1068 struct usb_phy *usb2_phy;
1069 struct usb_phy *usb3_phy;
1070
1071 struct phy *usb2_generic_phy;
1072 struct phy *usb3_generic_phy;
1073
1074 bool phys_ready;
1075
1076 struct ulpi *ulpi;
1077 bool ulpi_ready;
1078
1079 void __iomem *regs;
1080 size_t regs_size;
1081
1082 enum usb_dr_mode dr_mode;
1083 u32 current_dr_role;
1084 u32 desired_dr_role;
1085 struct extcon_dev *edev;
1086 struct notifier_block edev_nb;
1087 enum usb_phy_interface hsphy_mode;
1088
1089 u32 fladj;
1090 u32 irq_gadget;
1091 u32 otg_irq;
1092 u32 current_otg_role;
1093 u32 desired_otg_role;
1094 bool otg_restart_host;
1095 u32 nr_scratch;
1096 u32 u1u2;
1097 u32 maximum_speed;
1098
1099
1100
1101
1102
1103
1104
1105
1106 u32 revision;
1107
1108#define DWC3_REVISION_173A 0x5533173a
1109#define DWC3_REVISION_175A 0x5533175a
1110#define DWC3_REVISION_180A 0x5533180a
1111#define DWC3_REVISION_183A 0x5533183a
1112#define DWC3_REVISION_185A 0x5533185a
1113#define DWC3_REVISION_187A 0x5533187a
1114#define DWC3_REVISION_188A 0x5533188a
1115#define DWC3_REVISION_190A 0x5533190a
1116#define DWC3_REVISION_194A 0x5533194a
1117#define DWC3_REVISION_200A 0x5533200a
1118#define DWC3_REVISION_202A 0x5533202a
1119#define DWC3_REVISION_210A 0x5533210a
1120#define DWC3_REVISION_220A 0x5533220a
1121#define DWC3_REVISION_230A 0x5533230a
1122#define DWC3_REVISION_240A 0x5533240a
1123#define DWC3_REVISION_250A 0x5533250a
1124#define DWC3_REVISION_260A 0x5533260a
1125#define DWC3_REVISION_270A 0x5533270a
1126#define DWC3_REVISION_280A 0x5533280a
1127#define DWC3_REVISION_290A 0x5533290a
1128#define DWC3_REVISION_300A 0x5533300a
1129#define DWC3_REVISION_310A 0x5533310a
1130#define DWC3_REVISION_330A 0x5533330a
1131
1132
1133
1134
1135
1136#define DWC3_REVISION_IS_DWC31 0x80000000
1137#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
1138#define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
1139#define DWC3_USB31_REVISION_160A (0x3136302a | DWC3_REVISION_IS_DWC31)
1140#define DWC3_USB31_REVISION_170A (0x3137302a | DWC3_REVISION_IS_DWC31)
1141
1142 u32 version_type;
1143
1144#define DWC31_VERSIONTYPE_EA01 0x65613031
1145#define DWC31_VERSIONTYPE_EA02 0x65613032
1146#define DWC31_VERSIONTYPE_EA03 0x65613033
1147#define DWC31_VERSIONTYPE_EA04 0x65613034
1148#define DWC31_VERSIONTYPE_EA05 0x65613035
1149#define DWC31_VERSIONTYPE_EA06 0x65613036
1150
1151 enum dwc3_ep0_next ep0_next_event;
1152 enum dwc3_ep0_state ep0state;
1153 enum dwc3_link_state link_state;
1154
1155 u16 u2sel;
1156 u16 u2pel;
1157 u8 u1sel;
1158 u8 u1pel;
1159
1160 u8 speed;
1161
1162 u8 num_eps;
1163
1164 struct dwc3_hwparams hwparams;
1165 struct dentry *root;
1166 struct debugfs_regset32 *regset;
1167
1168 u32 dbg_lsp_select;
1169
1170 u8 test_mode;
1171 u8 test_mode_nr;
1172 u8 lpm_nyet_threshold;
1173 u8 hird_threshold;
1174 u8 rx_thr_num_pkt_prd;
1175 u8 rx_max_burst_prd;
1176 u8 tx_thr_num_pkt_prd;
1177 u8 tx_max_burst_prd;
1178
1179 const char *hsphy_interface;
1180
1181 unsigned connected:1;
1182 unsigned delayed_status:1;
1183 unsigned ep0_bounced:1;
1184 unsigned ep0_expect_in:1;
1185 unsigned has_hibernation:1;
1186 unsigned sysdev_is_parent:1;
1187 unsigned has_lpm_erratum:1;
1188 unsigned is_utmi_l1_suspend:1;
1189 unsigned is_fpga:1;
1190 unsigned pending_events:1;
1191 unsigned pullups_connected:1;
1192 unsigned setup_packet_pending:1;
1193 unsigned three_stage_setup:1;
1194 unsigned dis_start_transfer_quirk:1;
1195 unsigned usb3_lpm_capable:1;
1196 unsigned usb2_lpm_disable:1;
1197
1198 unsigned disable_scramble_quirk:1;
1199 unsigned u2exit_lfps_quirk:1;
1200 unsigned u2ss_inp3_quirk:1;
1201 unsigned req_p1p2p3_quirk:1;
1202 unsigned del_p1p2p3_quirk:1;
1203 unsigned del_phy_power_chg_quirk:1;
1204 unsigned lfps_filter_quirk:1;
1205 unsigned rx_detect_poll_quirk:1;
1206 unsigned dis_u3_susphy_quirk:1;
1207 unsigned dis_u2_susphy_quirk:1;
1208 unsigned dis_enblslpm_quirk:1;
1209 unsigned dis_rxdet_inp3_quirk:1;
1210 unsigned dis_u2_freeclk_exists_quirk:1;
1211 unsigned dis_del_phy_power_chg_quirk:1;
1212 unsigned dis_tx_ipgap_linecheck_quirk:1;
1213
1214 unsigned tx_de_emphasis_quirk:1;
1215 unsigned tx_de_emphasis:2;
1216
1217 unsigned dis_metastability_quirk:1;
1218
1219 u16 imod_interval;
1220};
1221
1222#define INCRX_BURST_MODE 0
1223#define INCRX_UNDEF_LENGTH_BURST_MODE 1
1224
1225#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1226
1227
1228
1229struct dwc3_event_type {
1230 u32 is_devspec:1;
1231 u32 type:7;
1232 u32 reserved8_31:24;
1233} __packed;
1234
1235#define DWC3_DEPEVT_XFERCOMPLETE 0x01
1236#define DWC3_DEPEVT_XFERINPROGRESS 0x02
1237#define DWC3_DEPEVT_XFERNOTREADY 0x03
1238#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1239#define DWC3_DEPEVT_STREAMEVT 0x06
1240#define DWC3_DEPEVT_EPCMDCMPLT 0x07
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261struct dwc3_event_depevt {
1262 u32 one_bit:1;
1263 u32 endpoint_number:5;
1264 u32 endpoint_event:4;
1265 u32 reserved11_10:2;
1266 u32 status:4;
1267
1268
1269#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1270
1271
1272#define DEPEVT_STATUS_BUSERR BIT(0)
1273#define DEPEVT_STATUS_SHORT BIT(1)
1274#define DEPEVT_STATUS_IOC BIT(2)
1275#define DEPEVT_STATUS_LST BIT(3)
1276#define DEPEVT_STATUS_MISSED_ISOC BIT(3)
1277
1278
1279#define DEPEVT_STREAMEVT_FOUND 1
1280#define DEPEVT_STREAMEVT_NOTFOUND 2
1281
1282
1283#define DEPEVT_STATUS_CONTROL_DATA 1
1284#define DEPEVT_STATUS_CONTROL_STATUS 2
1285#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1286
1287
1288#define DEPEVT_TRANSFER_NO_RESOURCE 1
1289#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1290
1291 u32 parameters:16;
1292
1293
1294#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1295} __packed;
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319struct dwc3_event_devt {
1320 u32 one_bit:1;
1321 u32 device_event:7;
1322 u32 type:4;
1323 u32 reserved15_12:4;
1324 u32 event_info:9;
1325 u32 reserved31_25:7;
1326} __packed;
1327
1328
1329
1330
1331
1332
1333
1334
1335struct dwc3_event_gevt {
1336 u32 one_bit:1;
1337 u32 device_event:7;
1338 u32 phy_port_number:4;
1339 u32 reserved31_12:20;
1340} __packed;
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350union dwc3_event {
1351 u32 raw;
1352 struct dwc3_event_type type;
1353 struct dwc3_event_depevt depevt;
1354 struct dwc3_event_devt devt;
1355 struct dwc3_event_gevt gevt;
1356};
1357
1358
1359
1360
1361
1362
1363
1364
1365struct dwc3_gadget_ep_cmd_params {
1366 u32 param2;
1367 u32 param1;
1368 u32 param0;
1369};
1370
1371
1372
1373
1374
1375#define DWC3_HAS_PERIPHERAL BIT(0)
1376#define DWC3_HAS_XHCI BIT(1)
1377#define DWC3_HAS_OTG BIT(3)
1378
1379
1380void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1381void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1382u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1383
1384
1385static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1386{
1387 return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1388}
1389
1390
1391static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1392{
1393 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1394}
1395
1396bool dwc3_has_imod(struct dwc3 *dwc);
1397
1398int dwc3_event_buffers_setup(struct dwc3 *dwc);
1399void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1400
1401#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1402int dwc3_host_init(struct dwc3 *dwc);
1403void dwc3_host_exit(struct dwc3 *dwc);
1404#else
1405static inline int dwc3_host_init(struct dwc3 *dwc)
1406{ return 0; }
1407static inline void dwc3_host_exit(struct dwc3 *dwc)
1408{ }
1409#endif
1410
1411#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1412int dwc3_gadget_init(struct dwc3 *dwc);
1413void dwc3_gadget_exit(struct dwc3 *dwc);
1414int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1415int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1416int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1417int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1418 struct dwc3_gadget_ep_cmd_params *params);
1419int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1420#else
1421static inline int dwc3_gadget_init(struct dwc3 *dwc)
1422{ return 0; }
1423static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1424{ }
1425static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1426{ return 0; }
1427static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1428{ return 0; }
1429static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1430 enum dwc3_link_state state)
1431{ return 0; }
1432
1433static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1434 struct dwc3_gadget_ep_cmd_params *params)
1435{ return 0; }
1436static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1437 int cmd, u32 param)
1438{ return 0; }
1439#endif
1440
1441#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1442int dwc3_drd_init(struct dwc3 *dwc);
1443void dwc3_drd_exit(struct dwc3 *dwc);
1444void dwc3_otg_init(struct dwc3 *dwc);
1445void dwc3_otg_exit(struct dwc3 *dwc);
1446void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1447void dwc3_otg_host_init(struct dwc3 *dwc);
1448#else
1449static inline int dwc3_drd_init(struct dwc3 *dwc)
1450{ return 0; }
1451static inline void dwc3_drd_exit(struct dwc3 *dwc)
1452{ }
1453static inline void dwc3_otg_init(struct dwc3 *dwc)
1454{ }
1455static inline void dwc3_otg_exit(struct dwc3 *dwc)
1456{ }
1457static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1458{ }
1459static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1460{ }
1461#endif
1462
1463
1464#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1465int dwc3_gadget_suspend(struct dwc3 *dwc);
1466int dwc3_gadget_resume(struct dwc3 *dwc);
1467void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1468#else
1469static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1470{
1471 return 0;
1472}
1473
1474static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1475{
1476 return 0;
1477}
1478
1479static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1480{
1481}
1482#endif
1483
1484#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1485int dwc3_ulpi_init(struct dwc3 *dwc);
1486void dwc3_ulpi_exit(struct dwc3 *dwc);
1487#else
1488static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1489{ return 0; }
1490static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1491{ }
1492#endif
1493
1494#endif
1495