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33#ifndef SOC_NPS_COMMON_H
34#define SOC_NPS_COMMON_H
35
36#ifdef CONFIG_SMP
37#define NPS_IPI_IRQ 5
38#endif
39
40#define NPS_HOST_REG_BASE 0xF6000000
41
42#define NPS_MSU_BLKID 0x018
43
44#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
45#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
46#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
47
48#ifndef __ASSEMBLY__
49
50
51#ifdef CONFIG_ARC
52static inline void nps_ack_gic(void)
53{
54 __asm__ __volatile__ (
55 " .word %0\n"
56 :
57 : "i"(CTOP_INST_RSPI_GIC_0_R12)
58 : "memory");
59}
60#else
61static inline void nps_ack_gic(void) { }
62#define write_aux_reg(r, v)
63#define read_aux_reg(r) 0
64#endif
65
66
67struct global_id {
68 union {
69 struct {
70#ifdef CONFIG_EZNPS_MTM_EXT
71 u32 __reserved:20, cluster:4, core:4, thread:4;
72#else
73 u32 __reserved:24, cluster:4, core:4;
74#endif
75 };
76 u32 value;
77 };
78};
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100static inline int nps_cluster_logic_to_phys(int cluster)
101{
102#ifdef __arc__
103 __asm__ __volatile__(
104 " mov r3,%0\n"
105 " .short %1\n"
106 " .word %2\n"
107 " mov %0,r3\n"
108 : "+r"(cluster)
109 : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
110 "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
111 : "r3");
112#endif
113
114 return cluster;
115}
116
117#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
118 ({ struct global_id gid; gid.value = cpu; \
119 nps_cluster_logic_to_phys(gid.cluster); })
120
121struct nps_host_reg_address {
122 union {
123 struct {
124 u32 base:8, cl_x:4, cl_y:4,
125 blkid:6, reg:8, __reserved:2;
126 };
127 u32 value;
128 };
129};
130
131struct nps_host_reg_address_non_cl {
132 union {
133 struct {
134 u32 base:7, blkid:11, reg:12, __reserved:2;
135 };
136 u32 value;
137 };
138};
139
140static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
141{
142 struct nps_host_reg_address_non_cl reg_address;
143
144 reg_address.value = NPS_HOST_REG_BASE;
145 reg_address.blkid = blkid;
146 reg_address.reg = reg;
147
148 return (void *)reg_address.value;
149}
150
151static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
152{
153 struct nps_host_reg_address reg_address;
154 u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
155
156 reg_address.value = NPS_HOST_REG_BASE;
157 reg_address.cl_x = (cl >> 2) & 0x3;
158 reg_address.cl_y = cl & 0x3;
159 reg_address.blkid = blkid;
160 reg_address.reg = reg;
161
162 return (void *)reg_address.value;
163}
164#endif
165
166#endif
167