1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $ 3 * linux/include/linux/cyclades.h 4 * 5 * This file was initially written by 6 * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by 7 * Ivan Passos <ivan@cyclades.com>. 8 * 9 * This file contains the general definitions for the cyclades.c driver 10 *$Log: cyclades.h,v $ 11 *Revision 3.1 2002/01/29 11:36:16 henrique 12 *added throttle field on struct cyclades_port to indicate whether the 13 *port is throttled or not 14 * 15 *Revision 3.1 2000/04/19 18:52:52 ivan 16 *converted address fields to unsigned long and added fields for physical 17 *addresses on cyclades_card structure; 18 * 19 *Revision 3.0 1998/11/02 14:20:59 ivan 20 *added nports field on cyclades_card structure; 21 * 22 *Revision 2.5 1998/08/03 16:57:01 ivan 23 *added cyclades_idle_stats structure; 24 * 25 *Revision 2.4 1998/06/01 12:09:53 ivan 26 *removed closing_wait2 from cyclades_port structure; 27 * 28 *Revision 2.3 1998/03/16 18:01:12 ivan 29 *changes in the cyclades_port structure to get it closer to the 30 *standard serial port structure; 31 *added constants for new ioctls; 32 * 33 *Revision 2.2 1998/02/17 16:50:00 ivan 34 *changes in the cyclades_port structure (addition of shutdown_wait and 35 *chip_rev variables); 36 *added constants for new ioctls and for CD1400 rev. numbers. 37 * 38 *Revision 2.1 1997/10/24 16:03:00 ivan 39 *added rflow (which allows enabling the CD1400 special flow control 40 *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to 41 *cyclades_port structure; 42 *added Alpha support 43 * 44 *Revision 2.0 1997/06/30 10:30:00 ivan 45 *added some new doorbell command constants related to IOCTLW and 46 *UART error signaling 47 * 48 *Revision 1.8 1997/06/03 15:30:00 ivan 49 *added constant ZFIRM_HLT 50 *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) 51 * 52 *Revision 1.7 1997/03/26 10:30:00 daniel 53 *new entries at the end of cyclades_port struct to reallocate 54 *variables illegally allocated within card memory. 55 * 56 *Revision 1.6 1996/09/09 18:35:30 bentson 57 *fold in changes for Cyclom-Z -- including structures for 58 *communicating with board as well modest changes to original 59 *structures to support new features. 60 * 61 *Revision 1.5 1995/11/13 21:13:31 bentson 62 *changes suggested by Michael Chastain <mec@duracef.shout.net> 63 *to support use of this file in non-kernel applications 64 * 65 * 66 */ 67 68#ifndef _UAPI_LINUX_CYCLADES_H 69#define _UAPI_LINUX_CYCLADES_H 70 71#include <linux/types.h> 72 73struct cyclades_monitor { 74 unsigned long int_count; 75 unsigned long char_count; 76 unsigned long char_max; 77 unsigned long char_last; 78}; 79 80/* 81 * These stats all reflect activity since the device was last initialized. 82 * (i.e., since the port was opened with no other processes already having it 83 * open) 84 */ 85struct cyclades_idle_stats { 86 __kernel_time_t in_use; /* Time device has been in use (secs) */ 87 __kernel_time_t recv_idle; /* Time since last char received (secs) */ 88 __kernel_time_t xmit_idle; /* Time since last char transmitted (secs) */ 89 unsigned long recv_bytes; /* Bytes received */ 90 unsigned long xmit_bytes; /* Bytes transmitted */ 91 unsigned long overruns; /* Input overruns */ 92 unsigned long frame_errs; /* Input framing errors */ 93 unsigned long parity_errs; /* Input parity errors */ 94}; 95 96#define CYCLADES_MAGIC 0x4359 97 98#define CYGETMON 0x435901 99#define CYGETTHRESH 0x435902 100#define CYSETTHRESH 0x435903 101#define CYGETDEFTHRESH 0x435904 102#define CYSETDEFTHRESH 0x435905 103#define CYGETTIMEOUT 0x435906 104#define CYSETTIMEOUT 0x435907 105#define CYGETDEFTIMEOUT 0x435908 106#define CYSETDEFTIMEOUT 0x435909 107#define CYSETRFLOW 0x43590a 108#define CYGETRFLOW 0x43590b 109#define CYSETRTSDTR_INV 0x43590c 110#define CYGETRTSDTR_INV 0x43590d 111#define CYZSETPOLLCYCLE 0x43590e 112#define CYZGETPOLLCYCLE 0x43590f 113#define CYGETCD1400VER 0x435910 114#define CYSETWAIT 0x435912 115#define CYGETWAIT 0x435913 116 117/*************** CYCLOM-Z ADDITIONS ***************/ 118 119#define CZIOC ('M' << 8) 120#define CZ_NBOARDS (CZIOC|0xfa) 121#define CZ_BOOT_START (CZIOC|0xfb) 122#define CZ_BOOT_DATA (CZIOC|0xfc) 123#define CZ_BOOT_END (CZIOC|0xfd) 124#define CZ_TEST (CZIOC|0xfe) 125 126#define CZ_DEF_POLL (HZ/25) 127 128#define MAX_BOARD 4 /* Max number of boards */ 129#define MAX_DEV 256 /* Max number of ports total */ 130#define CYZ_MAX_SPEED 921600 131 132#define CYZ_FIFO_SIZE 16 133 134#define CYZ_BOOT_NWORDS 0x100 135struct CYZ_BOOT_CTRL { 136 unsigned short nboard; 137 int status[MAX_BOARD]; 138 int nchannel[MAX_BOARD]; 139 int fw_rev[MAX_BOARD]; 140 unsigned long offset; 141 unsigned long data[CYZ_BOOT_NWORDS]; 142}; 143 144 145#ifndef DP_WINDOW_SIZE 146/* 147 * Memory Window Sizes 148 */ 149 150#define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ 151#define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and 152 8Zo V.2 */ 153#define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ 154 155/* 156 * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver 157 * normally will access only interested on the fpga_id, fpga_version, 158 * start_cpu and stop_cpu. 159 */ 160 161struct CUSTOM_REG { 162 __u32 fpga_id; /* FPGA Identification Register */ 163 __u32 fpga_version; /* FPGA Version Number Register */ 164 __u32 cpu_start; /* CPU start Register (write) */ 165 __u32 cpu_stop; /* CPU stop Register (write) */ 166 __u32 misc_reg; /* Miscellaneous Register */ 167 __u32 idt_mode; /* IDT mode Register */ 168 __u32 uart_irq_status; /* UART IRQ status Register */ 169 __u32 clear_timer0_irq; /* Clear timer interrupt Register */ 170 __u32 clear_timer1_irq; /* Clear timer interrupt Register */ 171 __u32 clear_timer2_irq; /* Clear timer interrupt Register */ 172 __u32 test_register; /* Test Register */ 173 __u32 test_count; /* Test Count Register */ 174 __u32 timer_select; /* Timer select register */ 175 __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ 176 __u32 ram_wait_state; /* RAM wait-state Register */ 177 __u32 uart_wait_state; /* UART wait-state Register */ 178 __u32 timer_wait_state; /* timer wait-state Register */ 179 __u32 ack_wait_state; /* ACK wait State Register */ 180}; 181 182/* 183 * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime 184 * registers. This structure can be used to access the 9060 registers 185 * (memory mapped). 186 */ 187 188struct RUNTIME_9060 { 189 __u32 loc_addr_range; /* 00h - Local Address Range */ 190 __u32 loc_addr_base; /* 04h - Local Address Base */ 191 __u32 loc_arbitr; /* 08h - Local Arbitration */ 192 __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */ 193 __u32 loc_rom_range; /* 10h - Local ROM Range */ 194 __u32 loc_rom_base; /* 14h - Local ROM Base */ 195 __u32 loc_bus_descr; /* 18h - Local Bus descriptor */ 196 __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */ 197 __u32 loc_base_mst; /* 20h - Local Base for Master PCI */ 198 __u32 loc_range_io; /* 24h - Local Range for Master IO */ 199 __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */ 200 __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */ 201 __u32 filler1; /* 30h */ 202 __u32 filler2; /* 34h */ 203 __u32 filler3; /* 38h */ 204 __u32 filler4; /* 3Ch */ 205 __u32 mail_box_0; /* 40h - Mail Box 0 */ 206 __u32 mail_box_1; /* 44h - Mail Box 1 */ 207 __u32 mail_box_2; /* 48h - Mail Box 2 */ 208 __u32 mail_box_3; /* 4Ch - Mail Box 3 */ 209 __u32 filler5; /* 50h */ 210 __u32 filler6; /* 54h */ 211 __u32 filler7; /* 58h */ 212 __u32 filler8; /* 5Ch */ 213 __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */ 214 __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */ 215 __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */ 216 __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ 217}; 218 219/* Values for the Local Base Address re-map register */ 220 221#define WIN_RAM 0x00000001L /* set the sliding window to RAM */ 222#define WIN_CREG 0x14000001L /* set the window to custom Registers */ 223 224/* Values timer select registers */ 225 226#define TIMER_BY_1M 0x00 /* clock divided by 1M */ 227#define TIMER_BY_256K 0x01 /* clock divided by 256k */ 228#define TIMER_BY_128K 0x02 /* clock divided by 128k */ 229#define TIMER_BY_32K 0x03 /* clock divided by 32k */ 230 231/****************** ****************** *******************/ 232#endif 233 234#ifndef ZFIRM_ID 235/* #include "zfwint.h" */ 236/****************** ****************** *******************/ 237/* 238 * This file contains the definitions for interfacing with the 239 * Cyclom-Z ZFIRM Firmware. 240 */ 241 242/* General Constant definitions */ 243 244#define MAX_CHAN 64 /* max number of channels per board */ 245 246/* firmware id structure (set after boot) */ 247 248#define ID_ADDRESS 0x00000180L /* signature/pointer address */ 249#define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ 250#define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ 251#define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ 252 253#define ZF_TINACT_DEF 1000 /* default inactivity timeout 254 (1000 ms) */ 255#define ZF_TINACT ZF_TINACT_DEF 256 257struct FIRM_ID { 258 __u32 signature; /* ZFIRM/U signature */ 259 __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */ 260}; 261 262/* Op. System id */ 263 264#define C_OS_LINUX 0x00000030 /* generic Linux system */ 265 266/* channel op_mode */ 267 268#define C_CH_DISABLE 0x00000000 /* channel is disabled */ 269#define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ 270#define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ 271#define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ 272#define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ 273 274/* comm_parity - parity */ 275 276#define C_PR_NONE 0x00000000 /* None */ 277#define C_PR_ODD 0x00000001 /* Odd */ 278#define C_PR_EVEN 0x00000002 /* Even */ 279#define C_PR_MARK 0x00000004 /* Mark */ 280#define C_PR_SPACE 0x00000008 /* Space */ 281#define C_PR_PARITY 0x000000ff 282 283#define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ 284#define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ 285 286/* comm_data_l - data length and stop bits */ 287 288#define C_DL_CS5 0x00000001 289#define C_DL_CS6 0x00000002 290#define C_DL_CS7 0x00000004 291#define C_DL_CS8 0x00000008 292#define C_DL_CS 0x0000000f 293#define C_DL_1STOP 0x00000010 294#define C_DL_15STOP 0x00000020 295#define C_DL_2STOP 0x00000040 296#define C_DL_STOP 0x000000f0 297 298/* interrupt enabling/status */ 299 300#define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ 301#define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ 302#define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ 303#define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ 304#define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ 305#define C_IN_MDCD 0x00000100 /* modem DCD change */ 306#define C_IN_MDSR 0x00000200 /* modem DSR change */ 307#define C_IN_MRI 0x00000400 /* modem RI change */ 308#define C_IN_MCTS 0x00000800 /* modem CTS change */ 309#define C_IN_RXBRK 0x00001000 /* Break received */ 310#define C_IN_PR_ERROR 0x00002000 /* parity error */ 311#define C_IN_FR_ERROR 0x00004000 /* frame error */ 312#define C_IN_OVR_ERROR 0x00008000 /* overrun error */ 313#define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ 314#define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ 315#define C_IN_MRTS 0x00040000 /* modem RTS drop */ 316#define C_IN_ICHAR 0x00080000 317 318/* flow control */ 319 320#define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ 321#define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ 322#define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ 323#define C_FL_SWFLOW 0x0000000f 324 325/* flow status */ 326 327#define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ 328#define C_FS_SENDING 0x00000001 /* UART is sending data */ 329#define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ 330 331/* rs_control/rs_status RS-232 signals */ 332 333#define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in 334 IOCTLM command */ 335#define C_RS_RTS 0x00000001 /* RTS */ 336#define C_RS_DTR 0x00000004 /* DTR */ 337#define C_RS_DCD 0x00000100 /* CD */ 338#define C_RS_DSR 0x00000200 /* DSR */ 339#define C_RS_RI 0x00000400 /* RI */ 340#define C_RS_CTS 0x00000800 /* CTS */ 341 342/* commands Host <-> Board */ 343 344#define C_CM_RESET 0x01 /* reset/flush buffers */ 345#define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ 346#define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ 347#define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ 348#define C_CM_SENDXOFF 0x10 /* send Xoff */ 349#define C_CM_SENDXON 0x11 /* send Xon */ 350#define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ 351#define C_CM_SENDBRK 0x41 /* send break */ 352#define C_CM_INTBACK 0x42 /* Interrupt back */ 353#define C_CM_SET_BREAK 0x43 /* Tx break on */ 354#define C_CM_CLR_BREAK 0x44 /* Tx break off */ 355#define C_CM_CMD_DONE 0x45 /* Previous command done */ 356#define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ 357#define C_CM_TINACT 0x51 /* set inactivity detection */ 358#define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ 359#define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ 360#define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ 361#define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ 362#define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ 363#define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ 364#define C_CM_Q_ENABLE 0x58 /* enables queue access from the 365 driver */ 366#define C_CM_Q_DISABLE 0x59 /* disables queue access from the 367 driver */ 368 369#define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ 370#define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ 371#define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ 372#define C_CM_RXNNDT 0x63 /* rx no new data timeout */ 373#define C_CM_TXFEMPTY 0x64 374#define C_CM_ICHAR 0x65 375#define C_CM_MDCD 0x70 /* modem DCD change */ 376#define C_CM_MDSR 0x71 /* modem DSR change */ 377#define C_CM_MRI 0x72 /* modem RI change */ 378#define C_CM_MCTS 0x73 /* modem CTS change */ 379#define C_CM_MRTS 0x74 /* modem RTS drop */ 380#define C_CM_RXBRK 0x84 /* Break received */ 381#define C_CM_PR_ERROR 0x85 /* Parity error */ 382#define C_CM_FR_ERROR 0x86 /* Frame error */ 383#define C_CM_OVR_ERROR 0x87 /* Overrun error */ 384#define C_CM_RXOFL 0x88 /* RX buffer overflow */ 385#define C_CM_CMDERROR 0x90 /* command error */ 386#define C_CM_FATAL 0x91 /* fatal error */ 387#define C_CM_HW_RESET 0x92 /* reset board */ 388 389/* 390 * CH_CTRL - This per port structure contains all parameters 391 * that control an specific port. It can be seen as the 392 * configuration registers of a "super-serial-controller". 393 */ 394 395struct CH_CTRL { 396 __u32 op_mode; /* operation mode */ 397 __u32 intr_enable; /* interrupt masking */ 398 __u32 sw_flow; /* SW flow control */ 399 __u32 flow_status; /* output flow status */ 400 __u32 comm_baud; /* baud rate - numerically specified */ 401 __u32 comm_parity; /* parity */ 402 __u32 comm_data_l; /* data length/stop */ 403 __u32 comm_flags; /* other flags */ 404 __u32 hw_flow; /* HW flow control */ 405 __u32 rs_control; /* RS-232 outputs */ 406 __u32 rs_status; /* RS-232 inputs */ 407 __u32 flow_xon; /* xon char */ 408 __u32 flow_xoff; /* xoff char */ 409 __u32 hw_overflow; /* hw overflow counter */ 410 __u32 sw_overflow; /* sw overflow counter */ 411 __u32 comm_error; /* frame/parity error counter */ 412 __u32 ichar; 413 __u32 filler[7]; 414}; 415 416 417/* 418 * BUF_CTRL - This per channel structure contains 419 * all Tx and Rx buffer control for a given channel. 420 */ 421 422struct BUF_CTRL { 423 __u32 flag_dma; /* buffers are in Host memory */ 424 __u32 tx_bufaddr; /* address of the tx buffer */ 425 __u32 tx_bufsize; /* tx buffer size */ 426 __u32 tx_threshold; /* tx low water mark */ 427 __u32 tx_get; /* tail index tx buf */ 428 __u32 tx_put; /* head index tx buf */ 429 __u32 rx_bufaddr; /* address of the rx buffer */ 430 __u32 rx_bufsize; /* rx buffer size */ 431 __u32 rx_threshold; /* rx high water mark */ 432 __u32 rx_get; /* tail index rx buf */ 433 __u32 rx_put; /* head index rx buf */ 434 __u32 filler[5]; /* filler to align structures */ 435}; 436 437/* 438 * BOARD_CTRL - This per board structure contains all global 439 * control fields related to the board. 440 */ 441 442struct BOARD_CTRL { 443 444 /* static info provided by the on-board CPU */ 445 __u32 n_channel; /* number of channels */ 446 __u32 fw_version; /* firmware version */ 447 448 /* static info provided by the driver */ 449 __u32 op_system; /* op_system id */ 450 __u32 dr_version; /* driver version */ 451 452 /* board control area */ 453 __u32 inactivity; /* inactivity control */ 454 455 /* host to FW commands */ 456 __u32 hcmd_channel; /* channel number */ 457 __u32 hcmd_param; /* pointer to parameters */ 458 459 /* FW to Host commands */ 460 __u32 fwcmd_channel; /* channel number */ 461 __u32 fwcmd_param; /* pointer to parameters */ 462 __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */ 463 464 /* filler so the structures are aligned */ 465 __u32 filler[6]; 466}; 467 468/* Host Interrupt Queue */ 469 470#define QUEUE_SIZE (10*MAX_CHAN) 471 472struct INT_QUEUE { 473 unsigned char intr_code[QUEUE_SIZE]; 474 unsigned long channel[QUEUE_SIZE]; 475 unsigned long param[QUEUE_SIZE]; 476 unsigned long put; 477 unsigned long get; 478}; 479 480/* 481 * ZFW_CTRL - This is the data structure that includes all other 482 * data structures used by the Firmware. 483 */ 484 485struct ZFW_CTRL { 486 struct BOARD_CTRL board_ctrl; 487 struct CH_CTRL ch_ctrl[MAX_CHAN]; 488 struct BUF_CTRL buf_ctrl[MAX_CHAN]; 489}; 490 491/****************** ****************** *******************/ 492#endif 493 494#endif /* _UAPI_LINUX_CYCLADES_H */ 495