1#ifndef __SOUND_ICE1712_H
2#define __SOUND_ICE1712_H
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25#include <linux/io.h>
26#include <sound/control.h>
27#include <sound/ac97_codec.h>
28#include <sound/rawmidi.h>
29#include <sound/i2c.h>
30#include <sound/ak4xxx-adda.h>
31#include <sound/ak4114.h>
32#include <sound/pt2258.h>
33#include <sound/pcm.h>
34#include <sound/mpu401.h>
35
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38
39
40
41#define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
42
43#define ICE1712_REG_CONTROL 0x00
44#define ICE1712_RESET 0x80
45#define ICE1712_SERR_ASSERT_DS_DMA 0x40
46#define ICE1712_DOS_VOL 0x10
47#define ICE1712_SERR_LEVEL 0x08
48#define ICE1712_SERR_ASSERT_SB 0x02
49#define ICE1712_NATIVE 0x01
50#define ICE1712_REG_IRQMASK 0x01
51#define ICE1712_IRQ_MPU1 0x80
52#define ICE1712_IRQ_TIMER 0x40
53#define ICE1712_IRQ_MPU2 0x20
54#define ICE1712_IRQ_PROPCM 0x10
55#define ICE1712_IRQ_FM 0x08
56#define ICE1712_IRQ_PBKDS 0x04
57#define ICE1712_IRQ_CONCAP 0x02
58#define ICE1712_IRQ_CONPBK 0x01
59#define ICE1712_REG_IRQSTAT 0x02
60
61#define ICE1712_REG_INDEX 0x03
62#define ICE1712_REG_DATA 0x04
63#define ICE1712_REG_NMI_STAT1 0x05
64#define ICE1712_REG_NMI_DATA 0x06
65#define ICE1712_REG_NMI_INDEX 0x07
66#define ICE1712_REG_AC97_INDEX 0x08
67#define ICE1712_REG_AC97_CMD 0x09
68#define ICE1712_AC97_COLD 0x80
69#define ICE1712_AC97_WARM 0x40
70#define ICE1712_AC97_WRITE 0x20
71#define ICE1712_AC97_READ 0x10
72#define ICE1712_AC97_READY 0x08
73#define ICE1712_AC97_PBK_VSR 0x02
74#define ICE1712_AC97_CAP_VSR 0x01
75#define ICE1712_REG_AC97_DATA 0x0a
76#define ICE1712_REG_MPU1_CTRL 0x0c
77#define ICE1712_REG_MPU1_DATA 0x0d
78#define ICE1712_REG_I2C_DEV_ADDR 0x10
79#define ICE1712_I2C_WRITE 0x01
80#define ICE1712_REG_I2C_BYTE_ADDR 0x11
81#define ICE1712_REG_I2C_DATA 0x12
82#define ICE1712_REG_I2C_CTRL 0x13
83#define ICE1712_I2C_EEPROM 0x80
84#define ICE1712_I2C_BUSY 0x01
85#define ICE1712_REG_CONCAP_ADDR 0x14
86#define ICE1712_REG_CONCAP_COUNT 0x18
87#define ICE1712_REG_SERR_SHADOW 0x1b
88#define ICE1712_REG_MPU2_CTRL 0x1c
89#define ICE1712_REG_MPU2_DATA 0x1d
90#define ICE1712_REG_TIMER 0x1e
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95
96#define ICE1712_IREG_PBK_COUNT_LO 0x00
97#define ICE1712_IREG_PBK_COUNT_HI 0x01
98#define ICE1712_IREG_PBK_CTRL 0x02
99#define ICE1712_IREG_PBK_LEFT 0x03
100#define ICE1712_IREG_PBK_RIGHT 0x04
101#define ICE1712_IREG_PBK_SOFT 0x05
102#define ICE1712_IREG_PBK_RATE_LO 0x06
103#define ICE1712_IREG_PBK_RATE_MID 0x07
104#define ICE1712_IREG_PBK_RATE_HI 0x08
105#define ICE1712_IREG_CAP_COUNT_LO 0x10
106#define ICE1712_IREG_CAP_COUNT_HI 0x11
107#define ICE1712_IREG_CAP_CTRL 0x12
108#define ICE1712_IREG_GPIO_DATA 0x20
109#define ICE1712_IREG_GPIO_WRITE_MASK 0x21
110#define ICE1712_IREG_GPIO_DIRECTION 0x22
111#define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
112#define ICE1712_IREG_PRO_POWERDOWN 0x31
113
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117
118#define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
119
120#define ICE1712_DS_INTMASK 0x00
121#define ICE1712_DS_INTSTAT 0x02
122#define ICE1712_DS_DATA 0x04
123#define ICE1712_DS_INDEX 0x08
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128
129#define ICE1712_DSC_ADDR0 0x00
130#define ICE1712_DSC_COUNT0 0x01
131#define ICE1712_DSC_ADDR1 0x02
132#define ICE1712_DSC_COUNT1 0x03
133#define ICE1712_DSC_CONTROL 0x04
134#define ICE1712_BUFFER1 0x80
135#define ICE1712_BUFFER1_AUTO 0x40
136#define ICE1712_BUFFER0_AUTO 0x20
137#define ICE1712_FLUSH 0x10
138#define ICE1712_STEREO 0x08
139#define ICE1712_16BIT 0x04
140#define ICE1712_PAUSE 0x02
141#define ICE1712_START 0x01
142#define ICE1712_DSC_RATE 0x05
143#define ICE1712_DSC_VOLUME 0x06
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147
148
149#define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
150
151#define ICE1712_MT_IRQ 0x00
152#define ICE1712_MULTI_CAPTURE 0x80
153#define ICE1712_MULTI_PLAYBACK 0x40
154#define ICE1712_MULTI_CAPSTATUS 0x02
155#define ICE1712_MULTI_PBKSTATUS 0x01
156#define ICE1712_MT_RATE 0x01
157#define ICE1712_SPDIF_MASTER 0x10
158#define ICE1712_MT_I2S_FORMAT 0x02
159#define ICE1712_MT_AC97_INDEX 0x04
160#define ICE1712_MT_AC97_CMD 0x05
161
162#define ICE1712_MT_AC97_DATA 0x06
163#define ICE1712_MT_PLAYBACK_ADDR 0x10
164#define ICE1712_MT_PLAYBACK_SIZE 0x14
165#define ICE1712_MT_PLAYBACK_COUNT 0x16
166#define ICE1712_MT_PLAYBACK_CONTROL 0x18
167#define ICE1712_CAPTURE_START_SHADOW 0x04
168#define ICE1712_PLAYBACK_PAUSE 0x02
169#define ICE1712_PLAYBACK_START 0x01
170#define ICE1712_MT_CAPTURE_ADDR 0x20
171#define ICE1712_MT_CAPTURE_SIZE 0x24
172#define ICE1712_MT_CAPTURE_COUNT 0x26
173#define ICE1712_MT_CAPTURE_CONTROL 0x28
174#define ICE1712_CAPTURE_START 0x01
175#define ICE1712_MT_ROUTE_PSDOUT03 0x30
176#define ICE1712_MT_ROUTE_SPDOUT 0x32
177#define ICE1712_MT_ROUTE_CAPTURE 0x34
178#define ICE1712_MT_MONITOR_VOLUME 0x38
179#define ICE1712_MT_MONITOR_INDEX 0x3a
180#define ICE1712_MT_MONITOR_RATE 0x3b
181#define ICE1712_MT_MONITOR_ROUTECTRL 0x3c
182#define ICE1712_ROUTE_AC97 0x01
183#define ICE1712_MT_MONITOR_PEAKINDEX 0x3e
184#define ICE1712_MT_MONITOR_PEAKDATA 0x3f
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190
191#define ICE1712_CFG_CLOCK 0xc0
192#define ICE1712_CFG_CLOCK512 0x00
193#define ICE1712_CFG_CLOCK384 0x40
194#define ICE1712_CFG_EXT 0x80
195#define ICE1712_CFG_2xMPU401 0x20
196#define ICE1712_CFG_NO_CON_AC97 0x10
197#define ICE1712_CFG_ADC_MASK 0x0c
198#define ICE1712_CFG_DAC_MASK 0x03
199
200#define ICE1712_CFG_PRO_I2S 0x80
201#define ICE1712_CFG_AC97_PACKED 0x01
202
203#define ICE1712_CFG_I2S_VOLUME 0x80
204#define ICE1712_CFG_I2S_96KHZ 0x40
205#define ICE1712_CFG_I2S_RESMASK 0x30
206#define ICE1712_CFG_I2S_OTHER 0x0f
207
208#define ICE1712_CFG_I2S_CHIPID 0xfc
209#define ICE1712_CFG_SPDIF_IN 0x02
210#define ICE1712_CFG_SPDIF_OUT 0x01
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214
215
216#define ICE1712_DMA_MODE_WRITE 0x48
217#define ICE1712_DMA_AUTOINIT 0x10
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221
222
223#define ICE_I2C_EEPROM_ADDR 0xA0
224
225struct snd_ice1712;
226
227struct snd_ice1712_eeprom {
228 unsigned int subvendor;
229 unsigned char size;
230 unsigned char version;
231 unsigned char data[32];
232 unsigned int gpiomask;
233 unsigned int gpiostate;
234 unsigned int gpiodir;
235};
236
237enum {
238 ICE_EEP1_CODEC = 0,
239 ICE_EEP1_ACLINK,
240 ICE_EEP1_I2SID,
241 ICE_EEP1_SPDIF,
242 ICE_EEP1_GPIO_MASK,
243 ICE_EEP1_GPIO_STATE,
244 ICE_EEP1_GPIO_DIR,
245 ICE_EEP1_AC97_MAIN_LO,
246 ICE_EEP1_AC97_MAIN_HI,
247 ICE_EEP1_AC97_PCM_LO,
248 ICE_EEP1_AC97_PCM_HI,
249 ICE_EEP1_AC97_REC_LO,
250 ICE_EEP1_AC97_REC_HI,
251 ICE_EEP1_AC97_RECSRC,
252 ICE_EEP1_DAC_ID,
253 ICE_EEP1_DAC_ID1,
254 ICE_EEP1_DAC_ID2,
255 ICE_EEP1_DAC_ID3,
256 ICE_EEP1_ADC_ID,
257 ICE_EEP1_ADC_ID1,
258 ICE_EEP1_ADC_ID2,
259 ICE_EEP1_ADC_ID3
260};
261
262#define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97))
263
264
265struct snd_ak4xxx_private {
266 unsigned int cif:1;
267 unsigned char caddr;
268 unsigned int data_mask;
269 unsigned int clk_mask;
270 unsigned int cs_mask;
271 unsigned int cs_addr;
272 unsigned int cs_none;
273 unsigned int add_flags;
274 unsigned int mask_flags;
275 struct snd_akm4xxx_ops {
276 void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate);
277 } ops;
278};
279
280struct snd_ice1712_spdif {
281 unsigned char cs8403_bits;
282 unsigned char cs8403_stream_bits;
283 struct snd_kcontrol *stream_ctl;
284
285 struct snd_ice1712_spdif_ops {
286 void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *);
287 void (*setup_rate)(struct snd_ice1712 *, int rate);
288 void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *);
289 void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
290 int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
291 void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
292 int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol);
293 } ops;
294};
295
296struct snd_ice1712_card_info;
297
298struct snd_ice1712 {
299 unsigned long conp_dma_size;
300 unsigned long conc_dma_size;
301 unsigned long prop_dma_size;
302 unsigned long proc_dma_size;
303 int irq;
304
305 unsigned long port;
306 unsigned long ddma_port;
307 unsigned long dmapath_port;
308 unsigned long profi_port;
309
310 struct pci_dev *pci;
311 struct snd_card *card;
312 struct snd_pcm *pcm;
313 struct snd_pcm *pcm_ds;
314 struct snd_pcm *pcm_pro;
315 struct snd_pcm_substream *playback_con_substream;
316 struct snd_pcm_substream *playback_con_substream_ds[6];
317 struct snd_pcm_substream *capture_con_substream;
318 struct snd_pcm_substream *playback_pro_substream;
319 struct snd_pcm_substream *capture_pro_substream;
320 unsigned int playback_pro_size;
321 unsigned int capture_pro_size;
322 unsigned int playback_con_virt_addr[6];
323 unsigned int playback_con_active_buf[6];
324 unsigned int capture_con_virt_addr;
325 unsigned int ac97_ext_id;
326 struct snd_ac97 *ac97;
327 struct snd_rawmidi *rmidi[2];
328
329 spinlock_t reg_lock;
330 struct snd_info_entry *proc_entry;
331
332 struct snd_ice1712_eeprom eeprom;
333 struct snd_ice1712_card_info *card_info;
334
335 unsigned int pro_volumes[20];
336 unsigned int omni:1;
337 unsigned int dxr_enable:1;
338 unsigned int vt1724:1;
339 unsigned int vt1720:1;
340 unsigned int has_spdif:1;
341 unsigned int force_pdma4:1;
342 unsigned int force_rdma1:1;
343 unsigned int midi_output:1;
344 unsigned int midi_input:1;
345 unsigned int own_routing:1;
346 unsigned int num_total_dacs;
347 unsigned int num_total_adcs;
348 unsigned int cur_rate;
349
350 struct mutex open_mutex;
351 struct snd_pcm_substream *pcm_reserved[4];
352 const struct snd_pcm_hw_constraint_list *hw_rates;
353
354 unsigned int akm_codecs;
355 struct snd_akm4xxx *akm;
356 struct snd_ice1712_spdif spdif;
357
358 struct mutex i2c_mutex;
359 struct snd_i2c_bus *i2c;
360 struct snd_i2c_device *cs8427;
361 unsigned int cs8427_timeout;
362
363 struct ice1712_gpio {
364 unsigned int direction;
365 unsigned int write_mask;
366 unsigned int saved[2];
367
368 void (*set_mask)(struct snd_ice1712 *ice, unsigned int data);
369 unsigned int (*get_mask)(struct snd_ice1712 *ice);
370 void (*set_dir)(struct snd_ice1712 *ice, unsigned int data);
371 unsigned int (*get_dir)(struct snd_ice1712 *ice);
372 void (*set_data)(struct snd_ice1712 *ice, unsigned int data);
373 unsigned int (*get_data)(struct snd_ice1712 *ice);
374
375 void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate);
376 void (*i2s_mclk_changed)(struct snd_ice1712 *ice);
377 } gpio;
378 struct mutex gpio_mutex;
379
380
381 void *spec;
382
383
384 int pro_rate_default;
385 int (*is_spdif_master)(struct snd_ice1712 *ice);
386 unsigned int (*get_rate)(struct snd_ice1712 *ice);
387 void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate);
388 unsigned char (*set_mclk)(struct snd_ice1712 *ice, unsigned int rate);
389 int (*set_spdif_clock)(struct snd_ice1712 *ice, int type);
390 int (*get_spdif_master_type)(struct snd_ice1712 *ice);
391 const char * const *ext_clock_names;
392 int ext_clock_count;
393 void (*pro_open)(struct snd_ice1712 *, struct snd_pcm_substream *);
394#ifdef CONFIG_PM_SLEEP
395 int (*pm_suspend)(struct snd_ice1712 *);
396 int (*pm_resume)(struct snd_ice1712 *);
397 unsigned int pm_suspend_enabled:1;
398 unsigned int pm_saved_is_spdif_master:1;
399 unsigned int pm_saved_spdif_ctrl;
400 unsigned char pm_saved_spdif_cfg;
401 unsigned int pm_saved_route;
402#endif
403};
404
405
406
407
408
409static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits)
410{
411 ice->gpio.set_dir(ice, bits);
412}
413
414static inline unsigned int snd_ice1712_gpio_get_dir(struct snd_ice1712 *ice)
415{
416 return ice->gpio.get_dir(ice);
417}
418
419static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits)
420{
421 ice->gpio.set_mask(ice, bits);
422}
423
424static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val)
425{
426 ice->gpio.set_data(ice, val);
427}
428
429static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice)
430{
431 return ice->gpio.get_data(ice);
432}
433
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436
437
438
439static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice)
440{
441 mutex_lock(&ice->gpio_mutex);
442 ice->gpio.saved[0] = ice->gpio.direction;
443 ice->gpio.saved[1] = ice->gpio.write_mask;
444}
445
446static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice)
447{
448 ice->gpio.set_dir(ice, ice->gpio.saved[0]);
449 ice->gpio.set_mask(ice, ice->gpio.saved[1]);
450 ice->gpio.direction = ice->gpio.saved[0];
451 ice->gpio.write_mask = ice->gpio.saved[1];
452 mutex_unlock(&ice->gpio_mutex);
453}
454
455
456#define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \
457{ .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \
458 .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \
459 .private_value = mask | (invert << 24) }
460
461int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
462int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
463
464
465
466
467static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice,
468 unsigned int mask, unsigned int bits)
469{
470 unsigned val;
471
472 ice->gpio.direction |= mask;
473 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
474 val = snd_ice1712_gpio_read(ice);
475 val &= ~mask;
476 val |= mask & bits;
477 snd_ice1712_gpio_write(ice, val);
478}
479
480static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice,
481 unsigned int mask)
482{
483 ice->gpio.direction &= ~mask;
484 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
485 return snd_ice1712_gpio_read(ice) & mask;
486}
487
488
489int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift);
490int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
491 int shift);
492
493int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice);
494
495int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak,
496 const struct snd_akm4xxx *template,
497 const struct snd_ak4xxx_private *priv,
498 struct snd_ice1712 *ice);
499void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice);
500int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice);
501
502int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr);
503
504static inline void snd_ice1712_write(struct snd_ice1712 *ice, u8 addr, u8 data)
505{
506 outb(addr, ICEREG(ice, INDEX));
507 outb(data, ICEREG(ice, DATA));
508}
509
510static inline u8 snd_ice1712_read(struct snd_ice1712 *ice, u8 addr)
511{
512 outb(addr, ICEREG(ice, INDEX));
513 return inb(ICEREG(ice, DATA));
514}
515
516
517
518
519
520
521struct snd_ice1712_card_info {
522 unsigned int subvendor;
523 const char *name;
524 const char *model;
525 const char *driver;
526 int (*chip_init)(struct snd_ice1712 *);
527 void (*chip_exit)(struct snd_ice1712 *);
528 int (*build_controls)(struct snd_ice1712 *);
529 unsigned int no_mpu401:1;
530 unsigned int mpu401_1_info_flags;
531 unsigned int mpu401_2_info_flags;
532 const char *mpu401_1_name;
533 const char *mpu401_2_name;
534 const unsigned int eeprom_size;
535 const unsigned char *eeprom_data;
536};
537
538
539#endif
540