1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/sizes.h>
21#include <linux/pm_runtime.h>
22
23#include <sound/soc.h>
24#include <drm/amd_asic_type.h>
25#include "acp.h"
26
27#define DRV_NAME "acp_audio_dma"
28
29#define PLAYBACK_MIN_NUM_PERIODS 2
30#define PLAYBACK_MAX_NUM_PERIODS 2
31#define PLAYBACK_MAX_PERIOD_SIZE 16384
32#define PLAYBACK_MIN_PERIOD_SIZE 1024
33#define CAPTURE_MIN_NUM_PERIODS 2
34#define CAPTURE_MAX_NUM_PERIODS 2
35#define CAPTURE_MAX_PERIOD_SIZE 16384
36#define CAPTURE_MIN_PERIOD_SIZE 1024
37
38#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
39#define MIN_BUFFER MAX_BUFFER
40
41#define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
42#define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE
43#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
44#define ST_MIN_BUFFER ST_MAX_BUFFER
45
46#define DRV_NAME "acp_audio_dma"
47bool bt_uart_enable = true;
48EXPORT_SYMBOL(bt_uart_enable);
49
50static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
51 .info = SNDRV_PCM_INFO_INTERLEAVED |
52 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
53 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
54 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
55 .formats = SNDRV_PCM_FMTBIT_S16_LE |
56 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
57 .channels_min = 1,
58 .channels_max = 8,
59 .rates = SNDRV_PCM_RATE_8000_96000,
60 .rate_min = 8000,
61 .rate_max = 96000,
62 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
63 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
64 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
65 .periods_min = PLAYBACK_MIN_NUM_PERIODS,
66 .periods_max = PLAYBACK_MAX_NUM_PERIODS,
67};
68
69static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
70 .info = SNDRV_PCM_INFO_INTERLEAVED |
71 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
72 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
73 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
74 .formats = SNDRV_PCM_FMTBIT_S16_LE |
75 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
76 .channels_min = 1,
77 .channels_max = 2,
78 .rates = SNDRV_PCM_RATE_8000_48000,
79 .rate_min = 8000,
80 .rate_max = 48000,
81 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
82 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
83 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
84 .periods_min = CAPTURE_MIN_NUM_PERIODS,
85 .periods_max = CAPTURE_MAX_NUM_PERIODS,
86};
87
88static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
89 .info = SNDRV_PCM_INFO_INTERLEAVED |
90 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
91 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
92 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
93 .formats = SNDRV_PCM_FMTBIT_S16_LE |
94 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
95 .channels_min = 1,
96 .channels_max = 8,
97 .rates = SNDRV_PCM_RATE_8000_96000,
98 .rate_min = 8000,
99 .rate_max = 96000,
100 .buffer_bytes_max = ST_MAX_BUFFER,
101 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
102 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
103 .periods_min = PLAYBACK_MIN_NUM_PERIODS,
104 .periods_max = PLAYBACK_MAX_NUM_PERIODS,
105};
106
107static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
108 .info = SNDRV_PCM_INFO_INTERLEAVED |
109 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
110 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
111 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
112 .formats = SNDRV_PCM_FMTBIT_S16_LE |
113 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
114 .channels_min = 1,
115 .channels_max = 2,
116 .rates = SNDRV_PCM_RATE_8000_48000,
117 .rate_min = 8000,
118 .rate_max = 48000,
119 .buffer_bytes_max = ST_MAX_BUFFER,
120 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
121 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
122 .periods_min = CAPTURE_MIN_NUM_PERIODS,
123 .periods_max = CAPTURE_MAX_NUM_PERIODS,
124};
125
126static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
127{
128 return readl(acp_mmio + (reg * 4));
129}
130
131static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
132{
133 writel(val, acp_mmio + (reg * 4));
134}
135
136
137
138
139
140static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
141 u16 dscr_strt_idx, u16 num_dscrs,
142 enum acp_dma_priority_level priority_level)
143{
144 u32 dma_ctrl;
145
146
147 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
148 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
149 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
150
151
152 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
153 & dscr_strt_idx),
154 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
155
156
157
158
159
160 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
161 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
162
163
164 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
165}
166
167
168static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
169 u16 descr_idx,
170 acp_dma_dscr_transfer_t *descr_info)
171{
172 u32 sram_offset;
173
174 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
175
176
177 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
178 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
179
180 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
181 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
182
183
184 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
185 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
186}
187
188static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)
189{
190 u32 dma_ctrl;
191 int ret;
192
193
194 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
195 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
196 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
197
198 ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),
199 dma_ctrl,
200 !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK),
201 100, ACP_DMA_RESET_TIME);
202 if (ret < 0)
203 pr_err("Failed to clear reset of channel : %d\n", ch_num);
204}
205
206
207
208
209
210static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
211 u32 size, int direction,
212 u32 pte_offset, u16 ch,
213 u32 sram_bank, u16 dma_dscr_idx,
214 u32 asic_type)
215{
216 u16 i;
217 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
218
219 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
220 dmadscr[i].xfer_val = 0;
221 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
222 dma_dscr_idx = dma_dscr_idx + i;
223 dmadscr[i].dest = sram_bank + (i * (size / 2));
224 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
225 + (pte_offset * SZ_4K) + (i * (size / 2));
226 switch (asic_type) {
227 case CHIP_STONEY:
228 dmadscr[i].xfer_val |=
229 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) |
230 (size / 2);
231 break;
232 default:
233 dmadscr[i].xfer_val |=
234 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) |
235 (size / 2);
236 }
237 } else {
238 dma_dscr_idx = dma_dscr_idx + i;
239 dmadscr[i].src = sram_bank + (i * (size / 2));
240 dmadscr[i].dest =
241 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
242 (pte_offset * SZ_4K) + (i * (size / 2));
243 switch (asic_type) {
244 case CHIP_STONEY:
245 dmadscr[i].xfer_val |=
246 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
247 (size / 2);
248 break;
249 default:
250 dmadscr[i].xfer_val |=
251 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
252 (size / 2);
253 }
254 }
255 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
256 &dmadscr[i]);
257 }
258 pre_config_reset(acp_mmio, ch);
259 config_acp_dma_channel(acp_mmio, ch,
260 dma_dscr_idx - 1,
261 NUM_DSCRS_PER_CHANNEL,
262 ACP_DMA_PRIORITY_LEVEL_NORMAL);
263}
264
265
266
267
268
269static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
270 int direction, u32 sram_bank,
271 u16 destination, u16 ch,
272 u16 dma_dscr_idx, u32 asic_type)
273{
274 u16 i;
275 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
276
277 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
278 dmadscr[i].xfer_val = 0;
279 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
280 dma_dscr_idx = dma_dscr_idx + i;
281 dmadscr[i].src = sram_bank + (i * (size / 2));
282
283 dmadscr[i].dest = 0;
284 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
285 (size / 2);
286 } else {
287 dma_dscr_idx = dma_dscr_idx + i;
288
289 dmadscr[i].src = 0;
290 dmadscr[i].dest =
291 sram_bank + (i * (size / 2));
292 dmadscr[i].xfer_val |= BIT(22) |
293 (destination << 16) | (size / 2);
294 }
295 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
296 &dmadscr[i]);
297 }
298 pre_config_reset(acp_mmio, ch);
299
300 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
301 NUM_DSCRS_PER_CHANNEL,
302 ACP_DMA_PRIORITY_LEVEL_NORMAL);
303}
304
305
306static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,
307 u16 num_of_pages, u32 pte_offset)
308{
309 u16 page_idx;
310 u32 low;
311 u32 high;
312 u32 offset;
313
314 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
315 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
316
317 acp_reg_write((offset + (page_idx * 8)),
318 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
319
320 low = lower_32_bits(addr);
321 high = upper_32_bits(addr);
322
323 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
324
325
326 acp_reg_write((offset + (page_idx * 8) + 4),
327 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
328
329
330 high |= BIT(31);
331 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
332
333
334 addr += PAGE_SIZE;
335 }
336}
337
338static void config_acp_dma(void __iomem *acp_mmio,
339 struct audio_substream_data *rtd,
340 u32 asic_type)
341{
342 u16 ch_acp_sysmem, ch_acp_i2s;
343
344 acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages,
345 rtd->pte_offset);
346
347 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
348 ch_acp_sysmem = rtd->ch1;
349 ch_acp_i2s = rtd->ch2;
350 } else {
351 ch_acp_i2s = rtd->ch1;
352 ch_acp_sysmem = rtd->ch2;
353 }
354
355 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
356 rtd->direction, rtd->pte_offset,
357 ch_acp_sysmem, rtd->sram_bank,
358 rtd->dma_dscr_idx_1, asic_type);
359
360 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
361 rtd->direction, rtd->sram_bank,
362 rtd->destination, ch_acp_i2s,
363 rtd->dma_dscr_idx_2, asic_type);
364}
365
366static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
367 u16 cap_channel)
368{
369 u32 val, ch_reg, imr_reg, res_reg;
370
371 switch (cap_channel) {
372 case CAP_CHANNEL1:
373 ch_reg = mmACP_I2SMICSP_RER1;
374 res_reg = mmACP_I2SMICSP_RCR1;
375 imr_reg = mmACP_I2SMICSP_IMR1;
376 break;
377 case CAP_CHANNEL0:
378 default:
379 ch_reg = mmACP_I2SMICSP_RER0;
380 res_reg = mmACP_I2SMICSP_RCR0;
381 imr_reg = mmACP_I2SMICSP_IMR0;
382 break;
383 }
384 val = acp_reg_read(acp_mmio,
385 mmACP_I2S_16BIT_RESOLUTION_EN);
386 if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {
387 acp_reg_write(0x0, acp_mmio, ch_reg);
388
389 acp_reg_write(0x2, acp_mmio, res_reg);
390 }
391 val = acp_reg_read(acp_mmio, imr_reg);
392 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
393 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
394 acp_reg_write(val, acp_mmio, imr_reg);
395 acp_reg_write(0x1, acp_mmio, ch_reg);
396}
397
398static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
399 u16 cap_channel)
400{
401 u32 val, ch_reg, imr_reg;
402
403 switch (cap_channel) {
404 case CAP_CHANNEL1:
405 imr_reg = mmACP_I2SMICSP_IMR1;
406 ch_reg = mmACP_I2SMICSP_RER1;
407 break;
408 case CAP_CHANNEL0:
409 default:
410 imr_reg = mmACP_I2SMICSP_IMR0;
411 ch_reg = mmACP_I2SMICSP_RER0;
412 break;
413 }
414 val = acp_reg_read(acp_mmio, imr_reg);
415 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
416 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
417 acp_reg_write(val, acp_mmio, imr_reg);
418 acp_reg_write(0x0, acp_mmio, ch_reg);
419}
420
421
422static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)
423{
424 u32 dma_ctrl;
425
426
427 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
428
429
430 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
431
432
433
434
435
436
437 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
438
439 switch (ch_num) {
440 case ACP_TO_I2S_DMA_CH_NUM:
441 case I2S_TO_ACP_DMA_CH_NUM:
442 case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
443 case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
444 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
445 break;
446 default:
447 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
448 break;
449 }
450
451
452 if (is_circular == true)
453 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
454 else
455 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
456
457 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
458}
459
460
461static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
462{
463 u32 dma_ctrl;
464 u32 dma_ch_sts;
465 u32 count = ACP_DMA_RESET_TIME;
466
467 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
468
469
470
471
472
473 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
474 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
475
476 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
477 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
478
479 if (dma_ch_sts & BIT(ch_num)) {
480
481
482
483
484 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
485 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
486 }
487
488
489 while (true) {
490 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
491 if (!(dma_ch_sts & BIT(ch_num))) {
492
493
494
495
496 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
497
498 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
499 + ch_num);
500 break;
501 }
502 if (--count == 0) {
503 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
504 return -ETIMEDOUT;
505 }
506 udelay(100);
507 }
508 return 0;
509}
510
511static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
512 bool power_on)
513{
514 u32 val, req_reg, sts_reg, sts_reg_mask;
515 u32 loops = 1000;
516
517 if (bank < 32) {
518 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
519 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
520 sts_reg_mask = 0xFFFFFFFF;
521
522 } else {
523 bank -= 32;
524 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
525 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
526 sts_reg_mask = 0x0000FFFF;
527 }
528
529 val = acp_reg_read(acp_mmio, req_reg);
530 if (val & (1 << bank)) {
531
532 if (power_on == true)
533
534 val &= ~(1 << bank);
535 else
536
537 return;
538 } else {
539
540 if (power_on == false)
541
542 val |= 1 << bank;
543 else
544
545 return;
546 }
547 acp_reg_write(val, acp_mmio, req_reg);
548
549 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
550 if (!loops--) {
551 pr_err("ACP SRAM bank %d state change failed\n", bank);
552 break;
553 }
554 cpu_relax();
555 }
556}
557
558
559static int acp_init(void __iomem *acp_mmio, u32 asic_type)
560{
561 u16 bank;
562 u32 val, count, sram_pte_offset;
563
564
565 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
566
567 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
568 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
569
570 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
571 while (true) {
572 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
573 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
574 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
575 break;
576 if (--count == 0) {
577 pr_err("Failed to reset ACP\n");
578 return -ETIMEDOUT;
579 }
580 udelay(100);
581 }
582
583
584 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
585 val = val | ACP_CONTROL__ClkEn_MASK;
586 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
587
588 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
589
590 while (true) {
591 val = acp_reg_read(acp_mmio, mmACP_STATUS);
592 if (val & (u32)0x1)
593 break;
594 if (--count == 0) {
595 pr_err("Failed to reset ACP\n");
596 return -ETIMEDOUT;
597 }
598 udelay(100);
599 }
600
601
602 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
603 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
604 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
605
606
607 if (!bt_uart_enable) {
608 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
609 val |= ACP_BT_UART_PAD_SELECT_MASK;
610 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
611 }
612
613
614 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
615 mmACP_AXI2DAGB_ONION_CNTL);
616
617
618 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
619 mmACP_AXI2DAGB_GARLIC_CNTL);
620
621 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
622 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
623 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
624 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
625 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
626 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
627 mmACP_DAGB_PAGE_SIZE_GRP_1);
628
629 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
630 mmACP_DMA_DESC_BASE_ADDR);
631
632
633 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
634 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
635 acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
636
637
638
639
640
641
642
643
644
645 if (asic_type != CHIP_STONEY) {
646 for (bank = 1; bank < 48; bank++)
647 acp_set_sram_bank_state(acp_mmio, bank, false);
648 }
649 return 0;
650}
651
652
653static int acp_deinit(void __iomem *acp_mmio)
654{
655 u32 val;
656 u32 count;
657
658
659 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
660
661 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
662 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
663
664 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
665 while (true) {
666 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
667 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
668 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
669 break;
670 if (--count == 0) {
671 pr_err("Failed to reset ACP\n");
672 return -ETIMEDOUT;
673 }
674 udelay(100);
675 }
676
677 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
678 val &= ~ACP_CONTROL__ClkEn_MASK;
679 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
680
681 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
682
683 while (true) {
684 val = acp_reg_read(acp_mmio, mmACP_STATUS);
685 if (!(val & (u32)0x1))
686 break;
687 if (--count == 0) {
688 pr_err("Failed to reset ACP\n");
689 return -ETIMEDOUT;
690 }
691 udelay(100);
692 }
693 return 0;
694}
695
696
697static irqreturn_t dma_irq_handler(int irq, void *arg)
698{
699 u16 dscr_idx;
700 u32 intr_flag, ext_intr_status;
701 struct audio_drv_data *irq_data;
702 void __iomem *acp_mmio;
703 struct device *dev = arg;
704 bool valid_irq = false;
705
706 irq_data = dev_get_drvdata(dev);
707 acp_mmio = irq_data->acp_mmio;
708
709 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
710 intr_flag = (((ext_intr_status &
711 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
712 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
713
714 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
715 valid_irq = true;
716 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
717 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
718 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
719 }
720
721 if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
722 valid_irq = true;
723 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
724 acp_reg_write((intr_flag &
725 BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
726 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
727 }
728
729 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
730 valid_irq = true;
731 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==
732 CAPTURE_START_DMA_DESCR_CH15)
733 dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
734 else
735 dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
736 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
737 1, 0);
738 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
739
740 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
741 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
742 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
743 }
744
745 if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
746 valid_irq = true;
747 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==
748 CAPTURE_START_DMA_DESCR_CH11)
749 dscr_idx = CAPTURE_END_DMA_DESCR_CH10;
750 else
751 dscr_idx = CAPTURE_START_DMA_DESCR_CH10;
752 config_acp_dma_channel(acp_mmio,
753 ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
754 dscr_idx, 1, 0);
755 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
756 false);
757
758 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
759 acp_reg_write((intr_flag &
760 BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
761 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
762 }
763
764 if (valid_irq)
765 return IRQ_HANDLED;
766 else
767 return IRQ_NONE;
768}
769
770static int acp_dma_open(struct snd_pcm_substream *substream)
771{
772 u16 bank;
773 int ret = 0;
774 struct snd_pcm_runtime *runtime = substream->runtime;
775 struct snd_soc_pcm_runtime *prtd = substream->private_data;
776 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
777 DRV_NAME);
778 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
779 struct audio_substream_data *adata =
780 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
781 if (!adata)
782 return -ENOMEM;
783
784 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
785 switch (intr_data->asic_type) {
786 case CHIP_STONEY:
787 runtime->hw = acp_st_pcm_hardware_playback;
788 break;
789 default:
790 runtime->hw = acp_pcm_hardware_playback;
791 }
792 } else {
793 switch (intr_data->asic_type) {
794 case CHIP_STONEY:
795 runtime->hw = acp_st_pcm_hardware_capture;
796 break;
797 default:
798 runtime->hw = acp_pcm_hardware_capture;
799 }
800 }
801
802 ret = snd_pcm_hw_constraint_integer(runtime,
803 SNDRV_PCM_HW_PARAM_PERIODS);
804 if (ret < 0) {
805 dev_err(component->dev, "set integer constraint failed\n");
806 kfree(adata);
807 return ret;
808 }
809
810 adata->acp_mmio = intr_data->acp_mmio;
811 runtime->private_data = adata;
812
813
814
815
816
817
818
819 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
820 !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream)
821 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
822
823 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
824
825
826
827
828
829 if (intr_data->asic_type != CHIP_STONEY) {
830 for (bank = 1; bank <= 4; bank++)
831 acp_set_sram_bank_state(intr_data->acp_mmio,
832 bank, true);
833 }
834 } else {
835 if (intr_data->asic_type != CHIP_STONEY) {
836 for (bank = 5; bank <= 8; bank++)
837 acp_set_sram_bank_state(intr_data->acp_mmio,
838 bank, true);
839 }
840 }
841
842 return 0;
843}
844
845static int acp_dma_hw_params(struct snd_pcm_substream *substream,
846 struct snd_pcm_hw_params *params)
847{
848 int status;
849 uint64_t size;
850 u32 val = 0;
851 struct snd_pcm_runtime *runtime;
852 struct audio_substream_data *rtd;
853 struct snd_soc_pcm_runtime *prtd = substream->private_data;
854 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
855 DRV_NAME);
856 struct audio_drv_data *adata = dev_get_drvdata(component->dev);
857 struct snd_soc_card *card = prtd->card;
858 struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
859
860 runtime = substream->runtime;
861 rtd = runtime->private_data;
862
863 if (WARN_ON(!rtd))
864 return -EINVAL;
865
866 if (pinfo) {
867 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
868 rtd->i2s_instance = pinfo->play_i2s_instance;
869 } else {
870 rtd->i2s_instance = pinfo->cap_i2s_instance;
871 rtd->capture_channel = pinfo->capture_channel;
872 }
873 }
874 if (adata->asic_type == CHIP_STONEY) {
875 val = acp_reg_read(adata->acp_mmio,
876 mmACP_I2S_16BIT_RESOLUTION_EN);
877 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
878 switch (rtd->i2s_instance) {
879 case I2S_BT_INSTANCE:
880 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
881 break;
882 case I2S_SP_INSTANCE:
883 default:
884 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
885 }
886 } else {
887 switch (rtd->i2s_instance) {
888 case I2S_BT_INSTANCE:
889 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
890 break;
891 case I2S_SP_INSTANCE:
892 default:
893 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
894 }
895 }
896 acp_reg_write(val, adata->acp_mmio,
897 mmACP_I2S_16BIT_RESOLUTION_EN);
898 }
899
900 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
901 switch (rtd->i2s_instance) {
902 case I2S_BT_INSTANCE:
903 rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
904 rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
905 rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
906 rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
907 rtd->destination = TO_BLUETOOTH;
908 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
909 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
910 rtd->byte_cnt_high_reg_offset =
911 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
912 rtd->byte_cnt_low_reg_offset =
913 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
914 adata->play_i2sbt_stream = substream;
915 break;
916 case I2S_SP_INSTANCE:
917 default:
918 switch (adata->asic_type) {
919 case CHIP_STONEY:
920 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
921 break;
922 default:
923 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
924 }
925 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
926 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
927 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
928 rtd->destination = TO_ACP_I2S_1;
929 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
930 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
931 rtd->byte_cnt_high_reg_offset =
932 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
933 rtd->byte_cnt_low_reg_offset =
934 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
935 adata->play_i2ssp_stream = substream;
936 }
937 } else {
938 switch (rtd->i2s_instance) {
939 case I2S_BT_INSTANCE:
940 rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
941 rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
942 rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
943 rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
944 rtd->destination = FROM_BLUETOOTH;
945 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
946 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
947 rtd->byte_cnt_high_reg_offset =
948 mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
949 rtd->byte_cnt_low_reg_offset =
950 mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
951 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11;
952 adata->capture_i2sbt_stream = substream;
953 break;
954 case I2S_SP_INSTANCE:
955 default:
956 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
957 rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM;
958 rtd->ch2 = ACP_TO_SYSRAM_CH_NUM;
959 switch (adata->asic_type) {
960 case CHIP_STONEY:
961 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
962 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
963 break;
964 default:
965 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
966 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
967 }
968 rtd->destination = FROM_ACP_I2S_1;
969 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
970 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
971 rtd->byte_cnt_high_reg_offset =
972 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
973 rtd->byte_cnt_low_reg_offset =
974 mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
975 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15;
976 adata->capture_i2ssp_stream = substream;
977 }
978 }
979
980 size = params_buffer_bytes(params);
981 status = snd_pcm_lib_malloc_pages(substream, size);
982 if (status < 0)
983 return status;
984
985 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
986
987 if (substream->dma_buffer.area) {
988 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
989
990 rtd->dma_addr = substream->dma_buffer.addr;
991 rtd->order = get_order(size);
992
993
994 rtd->size = size;
995 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
996 rtd->direction = substream->stream;
997
998 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
999 status = 0;
1000 } else {
1001 status = -ENOMEM;
1002 }
1003 return status;
1004}
1005
1006static int acp_dma_hw_free(struct snd_pcm_substream *substream)
1007{
1008 return snd_pcm_lib_free_pages(substream);
1009}
1010
1011static u64 acp_get_byte_count(struct audio_substream_data *rtd)
1012{
1013 union acp_dma_count byte_count;
1014
1015 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
1016 rtd->byte_cnt_high_reg_offset);
1017 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio,
1018 rtd->byte_cnt_low_reg_offset);
1019 return byte_count.bytescount;
1020}
1021
1022static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
1023{
1024 u32 buffersize;
1025 u32 pos = 0;
1026 u64 bytescount = 0;
1027 u16 dscr;
1028 u32 period_bytes, delay;
1029
1030 struct snd_pcm_runtime *runtime = substream->runtime;
1031 struct audio_substream_data *rtd = runtime->private_data;
1032
1033 if (!rtd)
1034 return -EINVAL;
1035
1036 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1037 period_bytes = frames_to_bytes(runtime, runtime->period_size);
1038 bytescount = acp_get_byte_count(rtd);
1039 if (bytescount >= rtd->bytescount)
1040 bytescount -= rtd->bytescount;
1041 if (bytescount < period_bytes) {
1042 pos = 0;
1043 } else {
1044 dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr);
1045 if (dscr == rtd->dma_dscr_idx_1)
1046 pos = period_bytes;
1047 else
1048 pos = 0;
1049 }
1050 if (bytescount > 0) {
1051 delay = do_div(bytescount, period_bytes);
1052 runtime->delay = bytes_to_frames(runtime, delay);
1053 }
1054 } else {
1055 buffersize = frames_to_bytes(runtime, runtime->buffer_size);
1056 bytescount = acp_get_byte_count(rtd);
1057 if (bytescount > rtd->bytescount)
1058 bytescount -= rtd->bytescount;
1059 pos = do_div(bytescount, buffersize);
1060 }
1061 return bytes_to_frames(runtime, pos);
1062}
1063
1064static int acp_dma_mmap(struct snd_pcm_substream *substream,
1065 struct vm_area_struct *vma)
1066{
1067 return snd_pcm_lib_default_mmap(substream, vma);
1068}
1069
1070static int acp_dma_prepare(struct snd_pcm_substream *substream)
1071{
1072 struct snd_pcm_runtime *runtime = substream->runtime;
1073 struct audio_substream_data *rtd = runtime->private_data;
1074 u16 ch_acp_sysmem, ch_acp_i2s;
1075
1076 if (!rtd)
1077 return -EINVAL;
1078
1079 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
1080 ch_acp_sysmem = rtd->ch1;
1081 ch_acp_i2s = rtd->ch2;
1082 } else {
1083 ch_acp_i2s = rtd->ch1;
1084 ch_acp_sysmem = rtd->ch2;
1085 }
1086 config_acp_dma_channel(rtd->acp_mmio,
1087 ch_acp_sysmem,
1088 rtd->dma_dscr_idx_1,
1089 NUM_DSCRS_PER_CHANNEL, 0);
1090 config_acp_dma_channel(rtd->acp_mmio,
1091 ch_acp_i2s,
1092 rtd->dma_dscr_idx_2,
1093 NUM_DSCRS_PER_CHANNEL, 0);
1094 return 0;
1095}
1096
1097static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
1098{
1099 int ret;
1100
1101 struct snd_pcm_runtime *runtime = substream->runtime;
1102 struct audio_substream_data *rtd = runtime->private_data;
1103
1104 if (!rtd)
1105 return -EINVAL;
1106 switch (cmd) {
1107 case SNDRV_PCM_TRIGGER_START:
1108 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1109 case SNDRV_PCM_TRIGGER_RESUME:
1110 rtd->bytescount = acp_get_byte_count(rtd);
1111 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1112 if (rtd->capture_channel == CAP_CHANNEL0) {
1113 acp_dma_cap_channel_disable(rtd->acp_mmio,
1114 CAP_CHANNEL1);
1115 acp_dma_cap_channel_enable(rtd->acp_mmio,
1116 CAP_CHANNEL0);
1117 }
1118 if (rtd->capture_channel == CAP_CHANNEL1) {
1119 acp_dma_cap_channel_disable(rtd->acp_mmio,
1120 CAP_CHANNEL0);
1121 acp_dma_cap_channel_enable(rtd->acp_mmio,
1122 CAP_CHANNEL1);
1123 }
1124 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1125 } else {
1126 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1127 acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
1128 }
1129 ret = 0;
1130 break;
1131 case SNDRV_PCM_TRIGGER_STOP:
1132 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1133 case SNDRV_PCM_TRIGGER_SUSPEND:
1134 acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1135 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1136 break;
1137 default:
1138 ret = -EINVAL;
1139 }
1140 return ret;
1141}
1142
1143static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
1144{
1145 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,
1146 DRV_NAME);
1147 struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1148 struct device *parent = component->dev->parent;
1149
1150 switch (adata->asic_type) {
1151 case CHIP_STONEY:
1152 snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1153 SNDRV_DMA_TYPE_DEV,
1154 parent,
1155 ST_MIN_BUFFER,
1156 ST_MAX_BUFFER);
1157 break;
1158 default:
1159 snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1160 SNDRV_DMA_TYPE_DEV,
1161 parent,
1162 MIN_BUFFER,
1163 MAX_BUFFER);
1164 break;
1165 }
1166 return 0;
1167}
1168
1169static int acp_dma_close(struct snd_pcm_substream *substream)
1170{
1171 u16 bank;
1172 struct snd_pcm_runtime *runtime = substream->runtime;
1173 struct audio_substream_data *rtd = runtime->private_data;
1174 struct snd_soc_pcm_runtime *prtd = substream->private_data;
1175 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
1176 DRV_NAME);
1177 struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1178
1179 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1180 switch (rtd->i2s_instance) {
1181 case I2S_BT_INSTANCE:
1182 adata->play_i2sbt_stream = NULL;
1183 break;
1184 case I2S_SP_INSTANCE:
1185 default:
1186 adata->play_i2ssp_stream = NULL;
1187
1188
1189
1190
1191
1192
1193
1194 if (adata->asic_type != CHIP_STONEY) {
1195 for (bank = 1; bank <= 4; bank++)
1196 acp_set_sram_bank_state(adata->acp_mmio,
1197 bank, false);
1198 }
1199 }
1200 } else {
1201 switch (rtd->i2s_instance) {
1202 case I2S_BT_INSTANCE:
1203 adata->capture_i2sbt_stream = NULL;
1204 break;
1205 case I2S_SP_INSTANCE:
1206 default:
1207 adata->capture_i2ssp_stream = NULL;
1208 if (adata->asic_type != CHIP_STONEY) {
1209 for (bank = 5; bank <= 8; bank++)
1210 acp_set_sram_bank_state(adata->acp_mmio,
1211 bank, false);
1212 }
1213 }
1214 }
1215
1216
1217
1218
1219
1220 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
1221 !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream)
1222 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1223 kfree(rtd);
1224 return 0;
1225}
1226
1227static const struct snd_pcm_ops acp_dma_ops = {
1228 .open = acp_dma_open,
1229 .close = acp_dma_close,
1230 .ioctl = snd_pcm_lib_ioctl,
1231 .hw_params = acp_dma_hw_params,
1232 .hw_free = acp_dma_hw_free,
1233 .trigger = acp_dma_trigger,
1234 .pointer = acp_dma_pointer,
1235 .mmap = acp_dma_mmap,
1236 .prepare = acp_dma_prepare,
1237};
1238
1239static const struct snd_soc_component_driver acp_asoc_platform = {
1240 .name = DRV_NAME,
1241 .ops = &acp_dma_ops,
1242 .pcm_new = acp_dma_new,
1243};
1244
1245static int acp_audio_probe(struct platform_device *pdev)
1246{
1247 int status;
1248 struct audio_drv_data *audio_drv_data;
1249 struct resource *res;
1250 const u32 *pdata = pdev->dev.platform_data;
1251
1252 if (!pdata) {
1253 dev_err(&pdev->dev, "Missing platform data\n");
1254 return -ENODEV;
1255 }
1256
1257 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
1258 GFP_KERNEL);
1259 if (!audio_drv_data)
1260 return -ENOMEM;
1261
1262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1263 audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
1264 if (IS_ERR(audio_drv_data->acp_mmio))
1265 return PTR_ERR(audio_drv_data->acp_mmio);
1266
1267
1268
1269
1270
1271
1272
1273 audio_drv_data->play_i2ssp_stream = NULL;
1274 audio_drv_data->capture_i2ssp_stream = NULL;
1275 audio_drv_data->play_i2sbt_stream = NULL;
1276 audio_drv_data->capture_i2sbt_stream = NULL;
1277
1278 audio_drv_data->asic_type = *pdata;
1279
1280 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1281 if (!res) {
1282 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
1283 return -ENODEV;
1284 }
1285
1286 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
1287 0, "ACP_IRQ", &pdev->dev);
1288 if (status) {
1289 dev_err(&pdev->dev, "ACP IRQ request failed\n");
1290 return status;
1291 }
1292
1293 dev_set_drvdata(&pdev->dev, audio_drv_data);
1294
1295
1296 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
1297 if (status) {
1298 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
1299 return status;
1300 }
1301
1302 status = devm_snd_soc_register_component(&pdev->dev,
1303 &acp_asoc_platform, NULL, 0);
1304 if (status != 0) {
1305 dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
1306 return status;
1307 }
1308
1309 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
1310 pm_runtime_use_autosuspend(&pdev->dev);
1311 pm_runtime_enable(&pdev->dev);
1312
1313 return status;
1314}
1315
1316static int acp_audio_remove(struct platform_device *pdev)
1317{
1318 int status;
1319 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
1320
1321 status = acp_deinit(adata->acp_mmio);
1322 if (status)
1323 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
1324 pm_runtime_disable(&pdev->dev);
1325
1326 return 0;
1327}
1328
1329static int acp_pcm_resume(struct device *dev)
1330{
1331 u16 bank;
1332 int status;
1333 struct audio_substream_data *rtd;
1334 struct audio_drv_data *adata = dev_get_drvdata(dev);
1335
1336 status = acp_init(adata->acp_mmio, adata->asic_type);
1337 if (status) {
1338 dev_err(dev, "ACP Init failed status:%d\n", status);
1339 return status;
1340 }
1341
1342 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
1343
1344
1345
1346
1347
1348 if (adata->asic_type != CHIP_STONEY) {
1349 for (bank = 1; bank <= 4; bank++)
1350 acp_set_sram_bank_state(adata->acp_mmio, bank,
1351 true);
1352 }
1353 rtd = adata->play_i2ssp_stream->runtime->private_data;
1354 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1355 }
1356 if (adata->capture_i2ssp_stream &&
1357 adata->capture_i2ssp_stream->runtime) {
1358 if (adata->asic_type != CHIP_STONEY) {
1359 for (bank = 5; bank <= 8; bank++)
1360 acp_set_sram_bank_state(adata->acp_mmio, bank,
1361 true);
1362 }
1363 rtd = adata->capture_i2ssp_stream->runtime->private_data;
1364 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1365 }
1366 if (adata->asic_type != CHIP_CARRIZO) {
1367 if (adata->play_i2sbt_stream &&
1368 adata->play_i2sbt_stream->runtime) {
1369 rtd = adata->play_i2sbt_stream->runtime->private_data;
1370 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1371 }
1372 if (adata->capture_i2sbt_stream &&
1373 adata->capture_i2sbt_stream->runtime) {
1374 rtd = adata->capture_i2sbt_stream->runtime->private_data;
1375 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1376 }
1377 }
1378 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1379 return 0;
1380}
1381
1382static int acp_pcm_runtime_suspend(struct device *dev)
1383{
1384 int status;
1385 struct audio_drv_data *adata = dev_get_drvdata(dev);
1386
1387 status = acp_deinit(adata->acp_mmio);
1388 if (status)
1389 dev_err(dev, "ACP Deinit failed status:%d\n", status);
1390 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1391 return 0;
1392}
1393
1394static int acp_pcm_runtime_resume(struct device *dev)
1395{
1396 int status;
1397 struct audio_drv_data *adata = dev_get_drvdata(dev);
1398
1399 status = acp_init(adata->acp_mmio, adata->asic_type);
1400 if (status) {
1401 dev_err(dev, "ACP Init failed status:%d\n", status);
1402 return status;
1403 }
1404 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1405 return 0;
1406}
1407
1408static const struct dev_pm_ops acp_pm_ops = {
1409 .resume = acp_pcm_resume,
1410 .runtime_suspend = acp_pcm_runtime_suspend,
1411 .runtime_resume = acp_pcm_runtime_resume,
1412};
1413
1414static struct platform_driver acp_dma_driver = {
1415 .probe = acp_audio_probe,
1416 .remove = acp_audio_remove,
1417 .driver = {
1418 .name = DRV_NAME,
1419 .pm = &acp_pm_ops,
1420 },
1421};
1422
1423module_platform_driver(acp_dma_driver);
1424
1425MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1426MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
1427MODULE_DESCRIPTION("AMD ACP PCM Driver");
1428MODULE_LICENSE("GPL v2");
1429MODULE_ALIAS("platform:"DRV_NAME);
1430
