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26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/pm.h>
31#include <linux/gpio.h>
32#include <linux/of_gpio.h>
33#include <linux/cdev.h>
34#include <linux/slab.h>
35#include <linux/clk.h>
36#include <linux/regulator/consumer.h>
37
38#include <sound/tlv320aic32x4.h>
39#include <sound/core.h>
40#include <sound/pcm.h>
41#include <sound/pcm_params.h>
42#include <sound/soc.h>
43#include <sound/soc-dapm.h>
44#include <sound/initval.h>
45#include <sound/tlv.h>
46
47#include "tlv320aic32x4.h"
48
49struct aic32x4_rate_divs {
50 u32 mclk;
51 u32 rate;
52 u8 p_val;
53 u8 pll_j;
54 u16 pll_d;
55 u16 dosr;
56 u8 ndac;
57 u8 mdac;
58 u8 aosr;
59 u8 nadc;
60 u8 madc;
61 u8 blck_N;
62};
63
64struct aic32x4_priv {
65 struct regmap *regmap;
66 u32 sysclk;
67 u32 power_cfg;
68 u32 micpga_routing;
69 bool swapdacs;
70 int rstn_gpio;
71 struct clk *mclk;
72
73 struct regulator *supply_ldo;
74 struct regulator *supply_iov;
75 struct regulator *supply_dv;
76 struct regulator *supply_av;
77
78 struct aic32x4_setup_data *setup;
79 struct device *dev;
80};
81
82static int mic_bias_event(struct snd_soc_dapm_widget *w,
83 struct snd_kcontrol *kcontrol, int event)
84{
85 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
86
87 switch (event) {
88 case SND_SOC_DAPM_POST_PMU:
89
90 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
91 AIC32x4_MICBIAS_MASK,
92 AIC32X4_MICBIAS_LDOIN |
93 AIC32X4_MICBIAS_2075V);
94 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
95 break;
96 case SND_SOC_DAPM_PRE_PMD:
97 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
98 AIC32x4_MICBIAS_MASK, 0);
99 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
100 __func__);
101 break;
102 }
103
104 return 0;
105}
106
107
108static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
109 struct snd_ctl_elem_value *ucontrol)
110{
111 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
112 u8 val;
113
114 val = snd_soc_component_read32(component, AIC32X4_DINCTL);
115
116 ucontrol->value.integer.value[0] = (val & 0x01);
117
118 return 0;
119};
120
121static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
122 struct snd_ctl_elem_value *ucontrol)
123{
124 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
125 u8 val;
126 u8 gpio_check;
127
128 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL);
129 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
130 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
131 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
132 __func__);
133 return -EINVAL;
134 }
135
136 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
137 return 0;
138
139 if (ucontrol->value.integer.value[0])
140 val |= ucontrol->value.integer.value[0];
141 else
142 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
143
144 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
145
146 return 0;
147};
148
149static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
150 struct snd_ctl_elem_value *ucontrol)
151{
152 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
153 u8 val;
154
155 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL);
156
157 ucontrol->value.integer.value[0] = (val & 0x01);
158
159 return 0;
160};
161
162static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
163 struct snd_ctl_elem_value *ucontrol)
164{
165 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
166 u8 val;
167 u8 gpio_check;
168
169 val = snd_soc_component_read32(component, AIC32X4_MISOCTL);
170 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
171 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
172 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
173 __func__);
174 return -EINVAL;
175 }
176
177 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
178 return 0;
179
180 if (ucontrol->value.integer.value[0])
181 val |= ucontrol->value.integer.value[0];
182 else
183 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
184
185 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
186
187 return 0;
188};
189
190static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
191 struct snd_ctl_elem_value *ucontrol)
192{
193 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
194 u8 val;
195
196 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
197 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
198
199 return 0;
200};
201
202static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
203 struct snd_ctl_elem_value *ucontrol)
204{
205 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
206 u8 val;
207 u8 gpio_check;
208
209 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL);
210 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
211 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
212 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
213 __func__);
214 return -EINVAL;
215 }
216
217 if (ucontrol->value.integer.value[0] == (val & 0x1))
218 return 0;
219
220 if (ucontrol->value.integer.value[0])
221 val |= ucontrol->value.integer.value[0];
222 else
223 val &= 0xfe;
224
225 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
226
227 return 0;
228};
229
230static const struct snd_kcontrol_new aic32x4_mfp1[] = {
231 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
232};
233
234static const struct snd_kcontrol_new aic32x4_mfp2[] = {
235 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
236};
237
238static const struct snd_kcontrol_new aic32x4_mfp3[] = {
239 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
240};
241
242static const struct snd_kcontrol_new aic32x4_mfp4[] = {
243 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
244};
245
246static const struct snd_kcontrol_new aic32x4_mfp5[] = {
247 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
248 aic32x4_set_mfp5_gpio),
249};
250
251
252static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
253
254static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
255
256static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
257
258static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
259
260static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
261 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
262 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
263 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
264 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
265 tlv_driver_gain),
266 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
267 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
268 tlv_driver_gain),
269 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
270 AIC32X4_HPRGAIN, 6, 0x01, 1),
271 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
272 AIC32X4_LORGAIN, 6, 0x01, 1),
273 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
274 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
275
276 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
277 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
278
279 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
280 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
281 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
282 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
283
284 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
285
286 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
287 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
288 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
289 4, 0x07, 0),
290 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
291 0, 0x03, 0),
292 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
293 6, 0x03, 0),
294 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
295 1, 0x1F, 0),
296 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
297 0, 0x7F, 0),
298 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
299 3, 0x1F, 0),
300 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
301 3, 0x1F, 0),
302 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
303 0, 0x1F, 0),
304 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
305 0, 0x0F, 0),
306};
307
308static const struct aic32x4_rate_divs aic32x4_divs[] = {
309
310 {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
311 {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
312 {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
313
314 {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
315 {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
316
317 {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
318 {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
319 {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
320
321 {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
322 {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
323 {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
324
325 {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
326 {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
327
328 {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
329 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
330 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
331
332 {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
333 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
334 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
335
336
337 {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
338};
339
340static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
341 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
342 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
343};
344
345static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
346 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
347 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
348};
349
350static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
351 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
352};
353
354static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
355 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
356};
357
358static const char * const resistor_text[] = {
359 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
360};
361
362
363static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
364static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
365static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
366static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
367
368static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
369static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
370static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
371
372static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
373 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
374};
375static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
376 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
377};
378static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
379 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
380};
381static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
382 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
383};
384static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
385 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
386};
387static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
388 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
389};
390static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
391 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
392};
393
394
395static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
396static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
397static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
398static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
399static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
400static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
401static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
402
403static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
404 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
405};
406static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
407 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
408};
409static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
410 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
411};
412static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
413 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
414};
415static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
416 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
417};
418static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
419 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
420};
421static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
422 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
423};
424
425static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
426 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
427 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
428 &hpl_output_mixer_controls[0],
429 ARRAY_SIZE(hpl_output_mixer_controls)),
430 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
431
432 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
433 &lol_output_mixer_controls[0],
434 ARRAY_SIZE(lol_output_mixer_controls)),
435 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
436
437 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
438 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
439 &hpr_output_mixer_controls[0],
440 ARRAY_SIZE(hpr_output_mixer_controls)),
441 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
442 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
443 &lor_output_mixer_controls[0],
444 ARRAY_SIZE(lor_output_mixer_controls)),
445 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
446
447 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
448 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
449 in1r_to_rmixer_controls),
450 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
451 in2r_to_rmixer_controls),
452 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
453 in3r_to_rmixer_controls),
454 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
455 in2l_to_rmixer_controls),
456 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
457 cmr_to_rmixer_controls),
458 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
459 in1l_to_rmixer_controls),
460 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
461 in3l_to_rmixer_controls),
462
463 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
464 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
465 in1l_to_lmixer_controls),
466 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
467 in2l_to_lmixer_controls),
468 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
469 in3l_to_lmixer_controls),
470 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
471 in1r_to_lmixer_controls),
472 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
473 cml_to_lmixer_controls),
474 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
475 in2r_to_lmixer_controls),
476 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
477 in3r_to_lmixer_controls),
478
479 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
480 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
481
482
483 SND_SOC_DAPM_OUTPUT("HPL"),
484 SND_SOC_DAPM_OUTPUT("HPR"),
485 SND_SOC_DAPM_OUTPUT("LOL"),
486 SND_SOC_DAPM_OUTPUT("LOR"),
487 SND_SOC_DAPM_INPUT("IN1_L"),
488 SND_SOC_DAPM_INPUT("IN1_R"),
489 SND_SOC_DAPM_INPUT("IN2_L"),
490 SND_SOC_DAPM_INPUT("IN2_R"),
491 SND_SOC_DAPM_INPUT("IN3_L"),
492 SND_SOC_DAPM_INPUT("IN3_R"),
493 SND_SOC_DAPM_INPUT("CM_L"),
494 SND_SOC_DAPM_INPUT("CM_R"),
495};
496
497static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
498
499 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
500 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
501
502 {"HPL Power", NULL, "HPL Output Mixer"},
503 {"HPL", NULL, "HPL Power"},
504
505 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
506
507 {"LOL Power", NULL, "LOL Output Mixer"},
508 {"LOL", NULL, "LOL Power"},
509
510
511 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
512 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
513
514 {"HPR Power", NULL, "HPR Output Mixer"},
515 {"HPR", NULL, "HPR Power"},
516
517 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
518
519 {"LOR Power", NULL, "LOR Output Mixer"},
520 {"LOR", NULL, "LOR Power"},
521
522
523 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
524 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
525 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
526 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
527
528 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
529 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
530 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
531 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
532
533 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
534 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
535 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
536 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
537
538 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
539 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
540 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
541 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
542
543 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
544 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
545 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
546 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
547
548 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
549 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
550 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
551 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
552
553 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
554 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
555 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
556 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
557
558
559 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
560 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
561 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
562 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
563
564 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
565 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
566 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
567 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
568
569 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
570 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
571 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
572 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
573
574 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
575 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
576 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
577 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
578
579 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
580 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
581 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
582 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
583
584 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
585 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
586 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
587 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
588
589 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
590 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
591 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
592 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
593};
594
595static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
596 {
597 .selector_reg = 0,
598 .selector_mask = 0xff,
599 .window_start = 0,
600 .window_len = 128,
601 .range_min = 0,
602 .range_max = AIC32X4_RMICPGAVOL,
603 },
604};
605
606const struct regmap_config aic32x4_regmap_config = {
607 .max_register = AIC32X4_RMICPGAVOL,
608 .ranges = aic32x4_regmap_pages,
609 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
610};
611EXPORT_SYMBOL(aic32x4_regmap_config);
612
613static inline int aic32x4_get_divs(int mclk, int rate)
614{
615 int i;
616
617 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
618 if ((aic32x4_divs[i].rate == rate)
619 && (aic32x4_divs[i].mclk == mclk)) {
620 return i;
621 }
622 }
623 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
624 return -EINVAL;
625}
626
627static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
628 int clk_id, unsigned int freq, int dir)
629{
630 struct snd_soc_component *component = codec_dai->component;
631 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
632
633 switch (freq) {
634 case 12000000:
635 case 24000000:
636 case 25000000:
637 aic32x4->sysclk = freq;
638 return 0;
639 }
640 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
641 return -EINVAL;
642}
643
644static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
645{
646 struct snd_soc_component *component = codec_dai->component;
647 u8 iface_reg_1 = 0;
648 u8 iface_reg_2 = 0;
649 u8 iface_reg_3 = 0;
650
651
652 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
653 case SND_SOC_DAIFMT_CBM_CFM:
654 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
655 break;
656 case SND_SOC_DAIFMT_CBS_CFS:
657 break;
658 default:
659 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
660 return -EINVAL;
661 }
662
663 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
664 case SND_SOC_DAIFMT_I2S:
665 break;
666 case SND_SOC_DAIFMT_DSP_A:
667 iface_reg_1 |= (AIC32X4_DSP_MODE <<
668 AIC32X4_IFACE1_DATATYPE_SHIFT);
669 iface_reg_3 |= AIC32X4_BCLKINV_MASK;
670 iface_reg_2 = 0x01;
671 break;
672 case SND_SOC_DAIFMT_DSP_B:
673 iface_reg_1 |= (AIC32X4_DSP_MODE <<
674 AIC32X4_IFACE1_DATATYPE_SHIFT);
675 iface_reg_3 |= AIC32X4_BCLKINV_MASK;
676 break;
677 case SND_SOC_DAIFMT_RIGHT_J:
678 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
679 AIC32X4_IFACE1_DATATYPE_SHIFT);
680 break;
681 case SND_SOC_DAIFMT_LEFT_J:
682 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
683 AIC32X4_IFACE1_DATATYPE_SHIFT);
684 break;
685 default:
686 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
687 return -EINVAL;
688 }
689
690 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
691 AIC32X4_IFACE1_DATATYPE_MASK |
692 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
693 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
694 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
695 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
696 AIC32X4_BCLKINV_MASK, iface_reg_3);
697
698 return 0;
699}
700
701static int aic32x4_hw_params(struct snd_pcm_substream *substream,
702 struct snd_pcm_hw_params *params,
703 struct snd_soc_dai *dai)
704{
705 struct snd_soc_component *component = dai->component;
706 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
707 u8 iface1_reg = 0;
708 u8 dacsetup_reg = 0;
709 int i;
710
711 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
712 if (i < 0) {
713 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
714 return i;
715 }
716
717
718 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
719 AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
720
721 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
722 AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
723
724 snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
725 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
726
727
728 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
729
730
731 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
732 aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
733
734
735 snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
736
737
738 snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
739 snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
740
741
742 snd_soc_component_update_bits(component, AIC32X4_NDAC,
743 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
744
745
746 snd_soc_component_update_bits(component, AIC32X4_MDAC,
747 AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
748
749
750 snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
751 snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
752
753
754 snd_soc_component_update_bits(component, AIC32X4_NADC,
755 AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
756
757
758 snd_soc_component_update_bits(component, AIC32X4_MADC,
759 AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
760
761
762 snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
763
764
765 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
766 AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
767
768 switch (params_width(params)) {
769 case 16:
770 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
771 AIC32X4_IFACE1_DATALEN_SHIFT);
772 break;
773 case 20:
774 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
775 AIC32X4_IFACE1_DATALEN_SHIFT);
776 break;
777 case 24:
778 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
779 AIC32X4_IFACE1_DATALEN_SHIFT);
780 break;
781 case 32:
782 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
783 AIC32X4_IFACE1_DATALEN_SHIFT);
784 break;
785 }
786 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
787 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
788
789 if (params_channels(params) == 1) {
790 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
791 } else {
792 if (aic32x4->swapdacs)
793 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
794 else
795 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
796 }
797 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
798 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
799
800 return 0;
801}
802
803static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
804{
805 struct snd_soc_component *component = dai->component;
806
807 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
808 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
809
810 return 0;
811}
812
813static int aic32x4_set_bias_level(struct snd_soc_component *component,
814 enum snd_soc_bias_level level)
815{
816 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
817 int ret;
818
819 switch (level) {
820 case SND_SOC_BIAS_ON:
821
822 ret = clk_prepare_enable(aic32x4->mclk);
823 if (ret) {
824 dev_err(component->dev, "Failed to enable master clock\n");
825 return ret;
826 }
827
828
829 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
830 AIC32X4_PLLEN, AIC32X4_PLLEN);
831
832
833 snd_soc_component_update_bits(component, AIC32X4_NDAC,
834 AIC32X4_NDACEN, AIC32X4_NDACEN);
835
836
837 snd_soc_component_update_bits(component, AIC32X4_MDAC,
838 AIC32X4_MDACEN, AIC32X4_MDACEN);
839
840
841 snd_soc_component_update_bits(component, AIC32X4_NADC,
842 AIC32X4_NADCEN, AIC32X4_NADCEN);
843
844
845 snd_soc_component_update_bits(component, AIC32X4_MADC,
846 AIC32X4_MADCEN, AIC32X4_MADCEN);
847
848
849 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
850 AIC32X4_BCLKEN, AIC32X4_BCLKEN);
851 break;
852 case SND_SOC_BIAS_PREPARE:
853 break;
854 case SND_SOC_BIAS_STANDBY:
855
856 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
857 break;
858
859
860 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
861 AIC32X4_BCLKEN, 0);
862
863
864 snd_soc_component_update_bits(component, AIC32X4_MADC,
865 AIC32X4_MADCEN, 0);
866
867
868 snd_soc_component_update_bits(component, AIC32X4_NADC,
869 AIC32X4_NADCEN, 0);
870
871
872 snd_soc_component_update_bits(component, AIC32X4_MDAC,
873 AIC32X4_MDACEN, 0);
874
875
876 snd_soc_component_update_bits(component, AIC32X4_NDAC,
877 AIC32X4_NDACEN, 0);
878
879
880 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
881 AIC32X4_PLLEN, 0);
882
883
884 clk_disable_unprepare(aic32x4->mclk);
885 break;
886 case SND_SOC_BIAS_OFF:
887 break;
888 }
889 return 0;
890}
891
892#define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
893#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
894 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
895
896static const struct snd_soc_dai_ops aic32x4_ops = {
897 .hw_params = aic32x4_hw_params,
898 .digital_mute = aic32x4_mute,
899 .set_fmt = aic32x4_set_dai_fmt,
900 .set_sysclk = aic32x4_set_dai_sysclk,
901};
902
903static struct snd_soc_dai_driver aic32x4_dai = {
904 .name = "tlv320aic32x4-hifi",
905 .playback = {
906 .stream_name = "Playback",
907 .channels_min = 1,
908 .channels_max = 2,
909 .rates = AIC32X4_RATES,
910 .formats = AIC32X4_FORMATS,},
911 .capture = {
912 .stream_name = "Capture",
913 .channels_min = 1,
914 .channels_max = 2,
915 .rates = AIC32X4_RATES,
916 .formats = AIC32X4_FORMATS,},
917 .ops = &aic32x4_ops,
918 .symmetric_rates = 1,
919};
920
921static void aic32x4_setup_gpios(struct snd_soc_component *component)
922{
923 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
924
925
926
927 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
928 snd_soc_component_write(component, AIC32X4_DINCTL,
929 aic32x4->setup->gpio_func[0]);
930 snd_soc_add_component_controls(component, aic32x4_mfp1,
931 ARRAY_SIZE(aic32x4_mfp1));
932 }
933
934
935 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
936 snd_soc_component_write(component, AIC32X4_DOUTCTL,
937 aic32x4->setup->gpio_func[1]);
938 snd_soc_add_component_controls(component, aic32x4_mfp2,
939 ARRAY_SIZE(aic32x4_mfp2));
940 }
941
942
943 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
944 snd_soc_component_write(component, AIC32X4_SCLKCTL,
945 aic32x4->setup->gpio_func[2]);
946 snd_soc_add_component_controls(component, aic32x4_mfp3,
947 ARRAY_SIZE(aic32x4_mfp3));
948 }
949
950
951 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
952 snd_soc_component_write(component, AIC32X4_MISOCTL,
953 aic32x4->setup->gpio_func[3]);
954 snd_soc_add_component_controls(component, aic32x4_mfp4,
955 ARRAY_SIZE(aic32x4_mfp4));
956 }
957
958
959 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
960 snd_soc_component_write(component, AIC32X4_GPIOCTL,
961 aic32x4->setup->gpio_func[4]);
962 snd_soc_add_component_controls(component, aic32x4_mfp5,
963 ARRAY_SIZE(aic32x4_mfp5));
964 }
965}
966
967static int aic32x4_component_probe(struct snd_soc_component *component)
968{
969 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
970 u32 tmp_reg;
971
972 if (gpio_is_valid(aic32x4->rstn_gpio)) {
973 ndelay(10);
974 gpio_set_value(aic32x4->rstn_gpio, 1);
975 mdelay(1);
976 }
977
978 snd_soc_component_write(component, AIC32X4_RESET, 0x01);
979
980 if (aic32x4->setup)
981 aic32x4_setup_gpios(component);
982
983
984 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
985 snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
986 AIC32X4_MICBIAS_2075V);
987 }
988 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
989 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
990
991 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
992 AIC32X4_LDOCTLEN : 0;
993 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
994
995 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE);
996 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
997 tmp_reg |= AIC32X4_LDOIN_18_36;
998 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
999 tmp_reg |= AIC32X4_LDOIN2HP;
1000 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1001
1002
1003 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1004 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1005 AIC32X4_LMICPGANIN_IN2R_10K);
1006 else
1007 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1008 AIC32X4_LMICPGANIN_CM1L_10K);
1009 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1010 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1011 AIC32X4_RMICPGANIN_IN1L_10K);
1012 else
1013 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1014 AIC32X4_RMICPGANIN_CM1R_10K);
1015
1016
1017
1018
1019
1020
1021 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);
1022 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1023 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1024 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1025
1026 return 0;
1027}
1028
1029static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1030 .probe = aic32x4_component_probe,
1031 .set_bias_level = aic32x4_set_bias_level,
1032 .controls = aic32x4_snd_controls,
1033 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1034 .dapm_widgets = aic32x4_dapm_widgets,
1035 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1036 .dapm_routes = aic32x4_dapm_routes,
1037 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1038 .suspend_bias_off = 1,
1039 .idle_bias_on = 1,
1040 .use_pmdown_time = 1,
1041 .endianness = 1,
1042 .non_legacy_dai_naming = 1,
1043};
1044
1045static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1046 struct device_node *np)
1047{
1048 struct aic32x4_setup_data *aic32x4_setup;
1049
1050 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1051 GFP_KERNEL);
1052 if (!aic32x4_setup)
1053 return -ENOMEM;
1054
1055 aic32x4->swapdacs = false;
1056 aic32x4->micpga_routing = 0;
1057 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1058
1059 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1060 aic32x4_setup->gpio_func, 5) >= 0)
1061 aic32x4->setup = aic32x4_setup;
1062 return 0;
1063}
1064
1065static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1066{
1067 regulator_disable(aic32x4->supply_iov);
1068
1069 if (!IS_ERR(aic32x4->supply_ldo))
1070 regulator_disable(aic32x4->supply_ldo);
1071
1072 if (!IS_ERR(aic32x4->supply_dv))
1073 regulator_disable(aic32x4->supply_dv);
1074
1075 if (!IS_ERR(aic32x4->supply_av))
1076 regulator_disable(aic32x4->supply_av);
1077}
1078
1079static int aic32x4_setup_regulators(struct device *dev,
1080 struct aic32x4_priv *aic32x4)
1081{
1082 int ret = 0;
1083
1084 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1085 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1086 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1087 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1088
1089
1090
1091 if (IS_ERR(aic32x4->supply_iov)) {
1092 dev_err(dev, "Missing supply 'iov'\n");
1093 return PTR_ERR(aic32x4->supply_iov);
1094 }
1095
1096 if (IS_ERR(aic32x4->supply_ldo)) {
1097 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1098 return -EPROBE_DEFER;
1099
1100 if (IS_ERR(aic32x4->supply_dv)) {
1101 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1102 return PTR_ERR(aic32x4->supply_dv);
1103 }
1104 if (IS_ERR(aic32x4->supply_av)) {
1105 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1106 return PTR_ERR(aic32x4->supply_av);
1107 }
1108 } else {
1109 if (IS_ERR(aic32x4->supply_dv) &&
1110 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1111 return -EPROBE_DEFER;
1112 if (IS_ERR(aic32x4->supply_av) &&
1113 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1114 return -EPROBE_DEFER;
1115 }
1116
1117 ret = regulator_enable(aic32x4->supply_iov);
1118 if (ret) {
1119 dev_err(dev, "Failed to enable regulator iov\n");
1120 return ret;
1121 }
1122
1123 if (!IS_ERR(aic32x4->supply_ldo)) {
1124 ret = regulator_enable(aic32x4->supply_ldo);
1125 if (ret) {
1126 dev_err(dev, "Failed to enable regulator ldo\n");
1127 goto error_ldo;
1128 }
1129 }
1130
1131 if (!IS_ERR(aic32x4->supply_dv)) {
1132 ret = regulator_enable(aic32x4->supply_dv);
1133 if (ret) {
1134 dev_err(dev, "Failed to enable regulator dv\n");
1135 goto error_dv;
1136 }
1137 }
1138
1139 if (!IS_ERR(aic32x4->supply_av)) {
1140 ret = regulator_enable(aic32x4->supply_av);
1141 if (ret) {
1142 dev_err(dev, "Failed to enable regulator av\n");
1143 goto error_av;
1144 }
1145 }
1146
1147 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1148 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1149
1150 return 0;
1151
1152error_av:
1153 if (!IS_ERR(aic32x4->supply_dv))
1154 regulator_disable(aic32x4->supply_dv);
1155
1156error_dv:
1157 if (!IS_ERR(aic32x4->supply_ldo))
1158 regulator_disable(aic32x4->supply_ldo);
1159
1160error_ldo:
1161 regulator_disable(aic32x4->supply_iov);
1162 return ret;
1163}
1164
1165int aic32x4_probe(struct device *dev, struct regmap *regmap)
1166{
1167 struct aic32x4_priv *aic32x4;
1168 struct aic32x4_pdata *pdata = dev->platform_data;
1169 struct device_node *np = dev->of_node;
1170 int ret;
1171
1172 if (IS_ERR(regmap))
1173 return PTR_ERR(regmap);
1174
1175 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1176 GFP_KERNEL);
1177 if (aic32x4 == NULL)
1178 return -ENOMEM;
1179
1180 aic32x4->dev = dev;
1181 dev_set_drvdata(dev, aic32x4);
1182
1183 if (pdata) {
1184 aic32x4->power_cfg = pdata->power_cfg;
1185 aic32x4->swapdacs = pdata->swapdacs;
1186 aic32x4->micpga_routing = pdata->micpga_routing;
1187 aic32x4->rstn_gpio = pdata->rstn_gpio;
1188 } else if (np) {
1189 ret = aic32x4_parse_dt(aic32x4, np);
1190 if (ret) {
1191 dev_err(dev, "Failed to parse DT node\n");
1192 return ret;
1193 }
1194 } else {
1195 aic32x4->power_cfg = 0;
1196 aic32x4->swapdacs = false;
1197 aic32x4->micpga_routing = 0;
1198 aic32x4->rstn_gpio = -1;
1199 }
1200
1201 aic32x4->mclk = devm_clk_get(dev, "mclk");
1202 if (IS_ERR(aic32x4->mclk)) {
1203 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n");
1204 return PTR_ERR(aic32x4->mclk);
1205 }
1206
1207 if (gpio_is_valid(aic32x4->rstn_gpio)) {
1208 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1209 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1210 if (ret != 0)
1211 return ret;
1212 }
1213
1214 ret = aic32x4_setup_regulators(dev, aic32x4);
1215 if (ret) {
1216 dev_err(dev, "Failed to setup regulators\n");
1217 return ret;
1218 }
1219
1220 ret = devm_snd_soc_register_component(dev,
1221 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1222 if (ret) {
1223 dev_err(dev, "Failed to register component\n");
1224 aic32x4_disable_regulators(aic32x4);
1225 return ret;
1226 }
1227
1228 return 0;
1229}
1230EXPORT_SYMBOL(aic32x4_probe);
1231
1232int aic32x4_remove(struct device *dev)
1233{
1234 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1235
1236 aic32x4_disable_regulators(aic32x4);
1237
1238 return 0;
1239}
1240EXPORT_SYMBOL(aic32x4_remove);
1241
1242MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1243MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1244MODULE_LICENSE("GPL");
1245
