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24#include <linux/types.h>
25#include <linux/platform_device.h>
26#include <linux/io.h>
27#include <linux/slab.h>
28#include <linux/module.h>
29#include <linux/interrupt.h>
30#include <linux/pm_runtime.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <sound/core.h>
34#include <sound/asoundef.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/initval.h>
38#include <sound/control.h>
39#include <sound/jack.h>
40#include <drm/drm_edid.h>
41#include <drm/intel_lpe_audio.h>
42#include "intel_hdmi_audio.h"
43
44#define for_each_pipe(card_ctx, pipe) \
45 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
46#define for_each_port(card_ctx, port) \
47 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
48
49
50static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
51static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
52static bool single_port;
53
54module_param_named(index, hdmi_card_index, int, 0444);
55MODULE_PARM_DESC(index,
56 "Index value for INTEL Intel HDMI Audio controller.");
57module_param_named(id, hdmi_card_id, charp, 0444);
58MODULE_PARM_DESC(id,
59 "ID string for INTEL Intel HDMI Audio controller.");
60module_param(single_port, bool, 0444);
61MODULE_PARM_DESC(single_port,
62 "Single-port mode (for compatibility)");
63
64
65
66
67static const int eld_speaker_allocation_bits[] = {
68 [0] = FL | FR,
69 [1] = LFE,
70 [2] = FC,
71 [3] = RL | RR,
72 [4] = RC,
73 [5] = FLC | FRC,
74 [6] = RLC | RRC,
75
76 [7] = 0,
77};
78
79
80
81
82
83
84
85static struct cea_channel_speaker_allocation channel_allocations[] = {
86
87{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
88
89{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
90
91{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
92
93{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
94
95{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
96
97{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
98
99{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
100
101{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
102
103{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
104
105{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
106{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
107{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
108{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
109{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
110{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
111{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
112{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
113{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
114{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
115{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
116{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
117{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
118{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
119{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
120{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
121{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
122{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
123{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
124{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
125{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
126{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
127{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
128};
129
130static const struct channel_map_table map_tables[] = {
131 { SNDRV_CHMAP_FL, 0x00, FL },
132 { SNDRV_CHMAP_FR, 0x01, FR },
133 { SNDRV_CHMAP_RL, 0x04, RL },
134 { SNDRV_CHMAP_RR, 0x05, RR },
135 { SNDRV_CHMAP_LFE, 0x02, LFE },
136 { SNDRV_CHMAP_FC, 0x03, FC },
137 { SNDRV_CHMAP_RLC, 0x06, RLC },
138 { SNDRV_CHMAP_RRC, 0x07, RRC },
139 {}
140};
141
142
143static const struct snd_pcm_hardware had_pcm_hardware = {
144 .info = (SNDRV_PCM_INFO_INTERLEAVED |
145 SNDRV_PCM_INFO_MMAP |
146 SNDRV_PCM_INFO_MMAP_VALID |
147 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
148 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
149 SNDRV_PCM_FMTBIT_S24_LE |
150 SNDRV_PCM_FMTBIT_S32_LE),
151 .rates = SNDRV_PCM_RATE_32000 |
152 SNDRV_PCM_RATE_44100 |
153 SNDRV_PCM_RATE_48000 |
154 SNDRV_PCM_RATE_88200 |
155 SNDRV_PCM_RATE_96000 |
156 SNDRV_PCM_RATE_176400 |
157 SNDRV_PCM_RATE_192000,
158 .rate_min = HAD_MIN_RATE,
159 .rate_max = HAD_MAX_RATE,
160 .channels_min = HAD_MIN_CHANNEL,
161 .channels_max = HAD_MAX_CHANNEL,
162 .buffer_bytes_max = HAD_MAX_BUFFER,
163 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
164 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
165 .periods_min = HAD_MIN_PERIODS,
166 .periods_max = HAD_MAX_PERIODS,
167 .fifo_size = HAD_FIFO_SIZE,
168};
169
170
171
172
173
174static struct snd_pcm_substream *
175had_substream_get(struct snd_intelhad *intelhaddata)
176{
177 struct snd_pcm_substream *substream;
178 unsigned long flags;
179
180 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
181 substream = intelhaddata->stream_info.substream;
182 if (substream)
183 intelhaddata->stream_info.substream_refcount++;
184 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
185 return substream;
186}
187
188
189
190
191static void had_substream_put(struct snd_intelhad *intelhaddata)
192{
193 unsigned long flags;
194
195 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
196 intelhaddata->stream_info.substream_refcount--;
197 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
198}
199
200static u32 had_config_offset(int pipe)
201{
202 switch (pipe) {
203 default:
204 case 0:
205 return AUDIO_HDMI_CONFIG_A;
206 case 1:
207 return AUDIO_HDMI_CONFIG_B;
208 case 2:
209 return AUDIO_HDMI_CONFIG_C;
210 }
211}
212
213
214static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx,
215 int pipe, u32 reg)
216{
217 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg);
218}
219
220static void had_write_register_raw(struct snd_intelhad_card *card_ctx,
221 int pipe, u32 reg, u32 val)
222{
223 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg);
224}
225
226static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
227{
228 if (!ctx->connected)
229 *val = 0;
230 else
231 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg);
232}
233
234static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
235{
236 if (ctx->connected)
237 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val);
238}
239
240
241
242
243
244
245
246
247
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249
250
251
252
253
254
255static void had_enable_audio(struct snd_intelhad *intelhaddata,
256 bool enable)
257{
258
259 intelhaddata->aud_config.regx.aud_en = enable;
260 had_write_register(intelhaddata, AUD_CONFIG,
261 intelhaddata->aud_config.regval);
262}
263
264
265static void had_ack_irqs(struct snd_intelhad *ctx)
266{
267 u32 status_reg;
268
269 if (!ctx->connected)
270 return;
271 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
272 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
273 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
274 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
275}
276
277
278static void had_reset_audio(struct snd_intelhad *intelhaddata)
279{
280 had_write_register(intelhaddata, AUD_HDMI_STATUS,
281 AUD_HDMI_STATUSG_MASK_FUNCRST);
282 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
283}
284
285
286
287
288
289static int had_prog_status_reg(struct snd_pcm_substream *substream,
290 struct snd_intelhad *intelhaddata)
291{
292 union aud_ch_status_0 ch_stat0 = {.regval = 0};
293 union aud_ch_status_1 ch_stat1 = {.regval = 0};
294
295 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
296 IEC958_AES0_NONAUDIO) >> 1;
297 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
298 IEC958_AES3_CON_CLOCK) >> 4;
299
300 switch (substream->runtime->rate) {
301 case AUD_SAMPLE_RATE_32:
302 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
303 break;
304
305 case AUD_SAMPLE_RATE_44_1:
306 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
307 break;
308 case AUD_SAMPLE_RATE_48:
309 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
310 break;
311 case AUD_SAMPLE_RATE_88_2:
312 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
313 break;
314 case AUD_SAMPLE_RATE_96:
315 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
316 break;
317 case AUD_SAMPLE_RATE_176_4:
318 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
319 break;
320 case AUD_SAMPLE_RATE_192:
321 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
322 break;
323
324 default:
325
326 return -EINVAL;
327 }
328
329 had_write_register(intelhaddata,
330 AUD_CH_STATUS_0, ch_stat0.regval);
331
332 switch (substream->runtime->format) {
333 case SNDRV_PCM_FORMAT_S16_LE:
334 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
335 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
336 break;
337 case SNDRV_PCM_FORMAT_S24_LE:
338 case SNDRV_PCM_FORMAT_S32_LE:
339 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
340 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
341 break;
342 default:
343 return -EINVAL;
344 }
345
346 had_write_register(intelhaddata,
347 AUD_CH_STATUS_1, ch_stat1.regval);
348 return 0;
349}
350
351
352
353
354
355
356static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
357 struct snd_intelhad *intelhaddata)
358{
359 union aud_cfg cfg_val = {.regval = 0};
360 union aud_buf_config buf_cfg = {.regval = 0};
361 u8 channels;
362
363 had_prog_status_reg(substream, intelhaddata);
364
365 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
366 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
367 buf_cfg.regx.aud_delay = 0;
368 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
369
370 channels = substream->runtime->channels;
371 cfg_val.regx.num_ch = channels - 2;
372 if (channels <= 2)
373 cfg_val.regx.layout = LAYOUT0;
374 else
375 cfg_val.regx.layout = LAYOUT1;
376
377 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
378 cfg_val.regx.packet_mode = 1;
379
380 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
381 cfg_val.regx.left_align = 1;
382
383 cfg_val.regx.val_bit = 1;
384
385
386 if (intelhaddata->dp_output) {
387 cfg_val.regx.dp_modei = 1;
388 cfg_val.regx.set = 1;
389 }
390
391 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
392 intelhaddata->aud_config = cfg_val;
393 return 0;
394}
395
396
397
398
399static void init_channel_allocations(void)
400{
401 int i, j;
402 struct cea_channel_speaker_allocation *p;
403
404 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
405 p = channel_allocations + i;
406 p->channels = 0;
407 p->spk_mask = 0;
408 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
409 if (p->speakers[j]) {
410 p->channels++;
411 p->spk_mask |= p->speakers[j];
412 }
413 }
414}
415
416
417
418
419
420
421
422
423
424static int had_channel_allocation(struct snd_intelhad *intelhaddata,
425 int channels)
426{
427 int i;
428 int ca = 0;
429 int spk_mask = 0;
430
431
432
433
434 if (channels <= 2)
435 return 0;
436
437
438
439
440
441
442
443
444 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
445 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
446 spk_mask |= eld_speaker_allocation_bits[i];
447 }
448
449
450 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
451 if (channels == channel_allocations[i].channels &&
452 (spk_mask & channel_allocations[i].spk_mask) ==
453 channel_allocations[i].spk_mask) {
454 ca = channel_allocations[i].ca_index;
455 break;
456 }
457 }
458
459 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
460
461 return ca;
462}
463
464
465static int spk_to_chmap(int spk)
466{
467 const struct channel_map_table *t = map_tables;
468
469 for (; t->map; t++) {
470 if (t->spk_mask == spk)
471 return t->map;
472 }
473 return 0;
474}
475
476static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
477{
478 int i, c;
479 int spk_mask = 0;
480 struct snd_pcm_chmap_elem *chmap;
481 u8 eld_high, eld_high_mask = 0xF0;
482 u8 high_msb;
483
484 kfree(intelhaddata->chmap->chmap);
485 intelhaddata->chmap->chmap = NULL;
486
487 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
488 if (!chmap)
489 return;
490
491 dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
492 intelhaddata->eld[DRM_ELD_SPEAKER]);
493
494
495
496
497
498
499
500
501
502
503 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
504 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
505
506
507 for (i = 1; i < 4; i++) {
508 high_msb = eld_high & (0x80 >> i);
509 if (high_msb) {
510 intelhaddata->eld[DRM_ELD_SPEAKER] &=
511 high_msb | 0xF;
512 break;
513 }
514 }
515 }
516
517 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
518 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
519 spk_mask |= eld_speaker_allocation_bits[i];
520 }
521
522 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
523 if (spk_mask == channel_allocations[i].spk_mask) {
524 for (c = 0; c < channel_allocations[i].channels; c++) {
525 chmap->map[c] = spk_to_chmap(
526 channel_allocations[i].speakers[
527 (MAX_SPEAKERS - 1) - c]);
528 }
529 chmap->channels = channel_allocations[i].channels;
530 intelhaddata->chmap->chmap = chmap;
531 break;
532 }
533 }
534 if (i >= ARRAY_SIZE(channel_allocations))
535 kfree(chmap);
536}
537
538
539
540
541static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
542 struct snd_ctl_elem_info *uinfo)
543{
544 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
545 uinfo->count = HAD_MAX_CHANNEL;
546 uinfo->value.integer.min = 0;
547 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
548 return 0;
549}
550
551static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
552 struct snd_ctl_elem_value *ucontrol)
553{
554 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
555 struct snd_intelhad *intelhaddata = info->private_data;
556 int i;
557 const struct snd_pcm_chmap_elem *chmap;
558
559 memset(ucontrol->value.integer.value, 0,
560 sizeof(long) * HAD_MAX_CHANNEL);
561 mutex_lock(&intelhaddata->mutex);
562 if (!intelhaddata->chmap->chmap) {
563 mutex_unlock(&intelhaddata->mutex);
564 return 0;
565 }
566
567 chmap = intelhaddata->chmap->chmap;
568 for (i = 0; i < chmap->channels; i++)
569 ucontrol->value.integer.value[i] = chmap->map[i];
570 mutex_unlock(&intelhaddata->mutex);
571
572 return 0;
573}
574
575static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
576 struct snd_pcm *pcm)
577{
578 int err;
579
580 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
581 NULL, 0, (unsigned long)intelhaddata,
582 &intelhaddata->chmap);
583 if (err < 0)
584 return err;
585
586 intelhaddata->chmap->private_data = intelhaddata;
587 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
588 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
589 intelhaddata->chmap->chmap = NULL;
590 return 0;
591}
592
593
594
595
596
597static void had_prog_dip(struct snd_pcm_substream *substream,
598 struct snd_intelhad *intelhaddata)
599{
600 int i;
601 union aud_ctrl_st ctrl_state = {.regval = 0};
602 union aud_info_frame2 frame2 = {.regval = 0};
603 union aud_info_frame3 frame3 = {.regval = 0};
604 u8 checksum = 0;
605 u32 info_frame;
606 int channels;
607 int ca;
608
609 channels = substream->runtime->channels;
610
611 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
612
613 ca = had_channel_allocation(intelhaddata, channels);
614 if (intelhaddata->dp_output) {
615 info_frame = DP_INFO_FRAME_WORD1;
616 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
617 } else {
618 info_frame = HDMI_INFO_FRAME_WORD1;
619 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
620 frame3.regx.chnl_alloc = ca;
621
622
623 for (i = 0; i < BYTES_PER_WORD; i++)
624 checksum += (info_frame >> (i * 8)) & 0xff;
625 for (i = 0; i < BYTES_PER_WORD; i++)
626 checksum += (frame2.regval >> (i * 8)) & 0xff;
627 for (i = 0; i < BYTES_PER_WORD; i++)
628 checksum += (frame3.regval >> (i * 8)) & 0xff;
629
630 frame2.regx.chksum = -(checksum);
631 }
632
633 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
634 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
635 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
636
637
638 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
639 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
640
641 ctrl_state.regx.dip_freq = 1;
642 ctrl_state.regx.dip_en_sta = 1;
643 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
644}
645
646static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
647{
648 u32 maud_val;
649
650
651 if (link_rate == DP_2_7_GHZ) {
652 switch (aud_samp_freq) {
653 case AUD_SAMPLE_RATE_32:
654 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
655 break;
656
657 case AUD_SAMPLE_RATE_44_1:
658 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
659 break;
660
661 case AUD_SAMPLE_RATE_48:
662 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
663 break;
664
665 case AUD_SAMPLE_RATE_88_2:
666 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
667 break;
668
669 case AUD_SAMPLE_RATE_96:
670 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
671 break;
672
673 case AUD_SAMPLE_RATE_176_4:
674 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
675 break;
676
677 case HAD_MAX_RATE:
678 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
679 break;
680
681 default:
682 maud_val = -EINVAL;
683 break;
684 }
685 } else if (link_rate == DP_1_62_GHZ) {
686 switch (aud_samp_freq) {
687 case AUD_SAMPLE_RATE_32:
688 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
689 break;
690
691 case AUD_SAMPLE_RATE_44_1:
692 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
693 break;
694
695 case AUD_SAMPLE_RATE_48:
696 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
697 break;
698
699 case AUD_SAMPLE_RATE_88_2:
700 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
701 break;
702
703 case AUD_SAMPLE_RATE_96:
704 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
705 break;
706
707 case AUD_SAMPLE_RATE_176_4:
708 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
709 break;
710
711 case HAD_MAX_RATE:
712 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
713 break;
714
715 default:
716 maud_val = -EINVAL;
717 break;
718 }
719 } else
720 maud_val = -EINVAL;
721
722 return maud_val;
723}
724
725
726
727
728
729
730
731
732
733
734
735
736static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
737 u32 n_param, struct snd_intelhad *intelhaddata)
738{
739 u32 cts_val;
740 u64 dividend, divisor;
741
742 if (intelhaddata->dp_output) {
743
744 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
745 } else {
746
747 dividend = (u64)tmds * n_param*1000;
748 divisor = 128 * aud_samp_freq;
749 cts_val = div64_u64(dividend, divisor);
750 }
751 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
752 tmds, n_param, cts_val);
753 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
754}
755
756static int had_calculate_n_value(u32 aud_samp_freq)
757{
758 int n_val;
759
760
761 switch (aud_samp_freq) {
762 case AUD_SAMPLE_RATE_32:
763 n_val = 4096;
764 break;
765
766 case AUD_SAMPLE_RATE_44_1:
767 n_val = 6272;
768 break;
769
770 case AUD_SAMPLE_RATE_48:
771 n_val = 6144;
772 break;
773
774 case AUD_SAMPLE_RATE_88_2:
775 n_val = 12544;
776 break;
777
778 case AUD_SAMPLE_RATE_96:
779 n_val = 12288;
780 break;
781
782 case AUD_SAMPLE_RATE_176_4:
783 n_val = 25088;
784 break;
785
786 case HAD_MAX_RATE:
787 n_val = 24576;
788 break;
789
790 default:
791 n_val = -EINVAL;
792 break;
793 }
794 return n_val;
795}
796
797
798
799
800
801
802
803
804
805
806
807static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
808 struct snd_intelhad *intelhaddata)
809{
810 int n_val;
811
812 if (intelhaddata->dp_output) {
813
814
815
816
817
818
819
820
821 n_val = DP_NAUD_VAL;
822 } else
823 n_val = had_calculate_n_value(aud_samp_freq);
824
825 if (n_val < 0)
826 return n_val;
827
828 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
829 *n_param = n_val;
830 return 0;
831}
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873#define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
874#define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
875
876
877static void had_prog_bd(struct snd_pcm_substream *substream,
878 struct snd_intelhad *intelhaddata)
879{
880 int idx = intelhaddata->bd_head;
881 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
882 u32 addr = substream->runtime->dma_addr + ofs;
883
884 addr |= AUD_BUF_VALID;
885 if (!substream->runtime->no_period_wakeup)
886 addr |= AUD_BUF_INTR_EN;
887 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
888 had_write_register(intelhaddata, AUD_BUF_LEN(idx),
889 intelhaddata->period_bytes);
890
891
892 intelhaddata->bd_head++;
893 intelhaddata->bd_head %= intelhaddata->num_bds;
894 intelhaddata->pcmbuf_filled++;
895 intelhaddata->pcmbuf_filled %= substream->runtime->periods;
896}
897
898
899static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
900 int idx)
901{
902 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
903 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
904}
905
906
907static void had_init_ringbuf(struct snd_pcm_substream *substream,
908 struct snd_intelhad *intelhaddata)
909{
910 struct snd_pcm_runtime *runtime = substream->runtime;
911 int i, num_periods;
912
913 num_periods = runtime->periods;
914 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
915
916 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
917 intelhaddata->period_bytes =
918 frames_to_bytes(runtime, runtime->period_size);
919 WARN_ON(intelhaddata->period_bytes & 0x3f);
920
921 intelhaddata->bd_head = 0;
922 intelhaddata->pcmbuf_head = 0;
923 intelhaddata->pcmbuf_filled = 0;
924
925 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
926 if (i < intelhaddata->num_bds)
927 had_prog_bd(substream, intelhaddata);
928 else
929 had_invalidate_bd(intelhaddata, i);
930 }
931
932 intelhaddata->bd_head = 0;
933}
934
935
936static void had_advance_ringbuf(struct snd_pcm_substream *substream,
937 struct snd_intelhad *intelhaddata)
938{
939 int num_periods = substream->runtime->periods;
940
941
942 had_prog_bd(substream, intelhaddata);
943
944
945 intelhaddata->pcmbuf_head++;
946 intelhaddata->pcmbuf_head %= num_periods;
947}
948
949
950
951
952static int had_process_ringbuf(struct snd_pcm_substream *substream,
953 struct snd_intelhad *intelhaddata)
954{
955 int len, processed;
956 unsigned long flags;
957
958 processed = 0;
959 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
960 for (;;) {
961
962 had_read_register(intelhaddata,
963 AUD_BUF_LEN(intelhaddata->bd_head),
964 &len);
965 if (len < 0 || len > intelhaddata->period_bytes) {
966 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
967 len);
968 len = -EPIPE;
969 goto out;
970 }
971
972 if (len > 0)
973 break;
974
975
976 if (++processed >= intelhaddata->num_bds) {
977 len = -EPIPE;
978 goto out;
979 }
980 had_advance_ringbuf(substream, intelhaddata);
981 }
982
983 len = intelhaddata->period_bytes - len;
984 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
985 out:
986 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
987 return len;
988}
989
990
991static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
992{
993 struct snd_pcm_substream *substream;
994
995 substream = had_substream_get(intelhaddata);
996 if (!substream)
997 return;
998
999 if (!intelhaddata->connected) {
1000 snd_pcm_stop_xrun(substream);
1001 goto out;
1002 }
1003
1004
1005 if (had_process_ringbuf(substream, intelhaddata) < 0)
1006 snd_pcm_stop_xrun(substream);
1007 else
1008 snd_pcm_period_elapsed(substream);
1009
1010 out:
1011 had_substream_put(intelhaddata);
1012}
1013
1014
1015
1016
1017
1018static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
1019{
1020 int i;
1021 u32 val;
1022
1023 for (i = 0; i < 100; i++) {
1024
1025 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1026 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1027 return;
1028 udelay(100);
1029 cond_resched();
1030 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1031 }
1032 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1033}
1034
1035
1036
1037
1038
1039static void had_do_reset(struct snd_intelhad *intelhaddata)
1040{
1041 if (!intelhaddata->need_reset || !intelhaddata->connected)
1042 return;
1043
1044
1045 had_reset_audio(intelhaddata);
1046 wait_clear_underrun_bit(intelhaddata);
1047 intelhaddata->need_reset = false;
1048}
1049
1050
1051static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1052{
1053 struct snd_pcm_substream *substream;
1054
1055
1056 substream = had_substream_get(intelhaddata);
1057 if (substream) {
1058 snd_pcm_stop_xrun(substream);
1059 had_substream_put(intelhaddata);
1060 }
1061 intelhaddata->need_reset = true;
1062}
1063
1064
1065
1066
1067static int had_pcm_open(struct snd_pcm_substream *substream)
1068{
1069 struct snd_intelhad *intelhaddata;
1070 struct snd_pcm_runtime *runtime;
1071 int retval;
1072
1073 intelhaddata = snd_pcm_substream_chip(substream);
1074 runtime = substream->runtime;
1075
1076 pm_runtime_get_sync(intelhaddata->dev);
1077
1078
1079 runtime->hw = had_pcm_hardware;
1080
1081 retval = snd_pcm_hw_constraint_integer(runtime,
1082 SNDRV_PCM_HW_PARAM_PERIODS);
1083 if (retval < 0)
1084 goto error;
1085
1086
1087
1088
1089 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1090 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1091 if (retval < 0)
1092 goto error;
1093
1094 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1095 if (retval < 0)
1096 goto error;
1097
1098
1099 spin_lock_irq(&intelhaddata->had_spinlock);
1100 intelhaddata->stream_info.substream = substream;
1101 intelhaddata->stream_info.substream_refcount++;
1102 spin_unlock_irq(&intelhaddata->had_spinlock);
1103
1104 return retval;
1105 error:
1106 pm_runtime_mark_last_busy(intelhaddata->dev);
1107 pm_runtime_put_autosuspend(intelhaddata->dev);
1108 return retval;
1109}
1110
1111
1112
1113
1114static int had_pcm_close(struct snd_pcm_substream *substream)
1115{
1116 struct snd_intelhad *intelhaddata;
1117
1118 intelhaddata = snd_pcm_substream_chip(substream);
1119
1120
1121 spin_lock_irq(&intelhaddata->had_spinlock);
1122 intelhaddata->stream_info.substream = NULL;
1123 intelhaddata->stream_info.substream_refcount--;
1124 while (intelhaddata->stream_info.substream_refcount > 0) {
1125 spin_unlock_irq(&intelhaddata->had_spinlock);
1126 cpu_relax();
1127 spin_lock_irq(&intelhaddata->had_spinlock);
1128 }
1129 spin_unlock_irq(&intelhaddata->had_spinlock);
1130
1131 pm_runtime_mark_last_busy(intelhaddata->dev);
1132 pm_runtime_put_autosuspend(intelhaddata->dev);
1133 return 0;
1134}
1135
1136
1137
1138
1139static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1140 struct snd_pcm_hw_params *hw_params)
1141{
1142 struct snd_intelhad *intelhaddata;
1143 int buf_size, retval;
1144
1145 intelhaddata = snd_pcm_substream_chip(substream);
1146 buf_size = params_buffer_bytes(hw_params);
1147 retval = snd_pcm_lib_malloc_pages(substream, buf_size);
1148 if (retval < 0)
1149 return retval;
1150 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1151 __func__, buf_size);
1152 return retval;
1153}
1154
1155
1156
1157
1158static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1159{
1160 struct snd_intelhad *intelhaddata;
1161
1162 intelhaddata = snd_pcm_substream_chip(substream);
1163 had_do_reset(intelhaddata);
1164
1165 return snd_pcm_lib_free_pages(substream);
1166}
1167
1168
1169
1170
1171static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1172{
1173 int retval = 0;
1174 struct snd_intelhad *intelhaddata;
1175
1176 intelhaddata = snd_pcm_substream_chip(substream);
1177
1178 spin_lock(&intelhaddata->had_spinlock);
1179 switch (cmd) {
1180 case SNDRV_PCM_TRIGGER_START:
1181 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1182 case SNDRV_PCM_TRIGGER_RESUME:
1183
1184 had_ack_irqs(intelhaddata);
1185 had_enable_audio(intelhaddata, true);
1186 break;
1187
1188 case SNDRV_PCM_TRIGGER_STOP:
1189 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1190
1191 had_enable_audio(intelhaddata, false);
1192 intelhaddata->need_reset = true;
1193 break;
1194
1195 default:
1196 retval = -EINVAL;
1197 }
1198 spin_unlock(&intelhaddata->had_spinlock);
1199 return retval;
1200}
1201
1202
1203
1204
1205static int had_pcm_prepare(struct snd_pcm_substream *substream)
1206{
1207 int retval;
1208 u32 disp_samp_freq, n_param;
1209 u32 link_rate = 0;
1210 struct snd_intelhad *intelhaddata;
1211 struct snd_pcm_runtime *runtime;
1212
1213 intelhaddata = snd_pcm_substream_chip(substream);
1214 runtime = substream->runtime;
1215
1216 dev_dbg(intelhaddata->dev, "period_size=%d\n",
1217 (int)frames_to_bytes(runtime, runtime->period_size));
1218 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1219 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1220 (int)snd_pcm_lib_buffer_bytes(substream));
1221 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1222 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1223
1224 had_do_reset(intelhaddata);
1225
1226
1227 disp_samp_freq = intelhaddata->tmds_clock_speed;
1228
1229 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1230 if (retval) {
1231 dev_err(intelhaddata->dev,
1232 "programming N value failed %#x\n", retval);
1233 goto prep_end;
1234 }
1235
1236 if (intelhaddata->dp_output)
1237 link_rate = intelhaddata->link_rate;
1238
1239 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1240 n_param, intelhaddata);
1241
1242 had_prog_dip(substream, intelhaddata);
1243
1244 retval = had_init_audio_ctrl(substream, intelhaddata);
1245
1246
1247 had_init_ringbuf(substream, intelhaddata);
1248
1249
1250
1251
1252
1253
1254 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1255
1256prep_end:
1257 return retval;
1258}
1259
1260
1261
1262
1263static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1264{
1265 struct snd_intelhad *intelhaddata;
1266 int len;
1267
1268 intelhaddata = snd_pcm_substream_chip(substream);
1269
1270 if (!intelhaddata->connected)
1271 return SNDRV_PCM_POS_XRUN;
1272
1273 len = had_process_ringbuf(substream, intelhaddata);
1274 if (len < 0)
1275 return SNDRV_PCM_POS_XRUN;
1276 len = bytes_to_frames(substream->runtime, len);
1277
1278 len %= substream->runtime->buffer_size;
1279 return len;
1280}
1281
1282
1283
1284
1285static int had_pcm_mmap(struct snd_pcm_substream *substream,
1286 struct vm_area_struct *vma)
1287{
1288 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1289 return remap_pfn_range(vma, vma->vm_start,
1290 substream->dma_buffer.addr >> PAGE_SHIFT,
1291 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1292}
1293
1294
1295
1296
1297static const struct snd_pcm_ops had_pcm_ops = {
1298 .open = had_pcm_open,
1299 .close = had_pcm_close,
1300 .ioctl = snd_pcm_lib_ioctl,
1301 .hw_params = had_pcm_hw_params,
1302 .hw_free = had_pcm_hw_free,
1303 .prepare = had_pcm_prepare,
1304 .trigger = had_pcm_trigger,
1305 .pointer = had_pcm_pointer,
1306 .mmap = had_pcm_mmap,
1307};
1308
1309
1310static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1311{
1312 struct snd_pcm_substream *substream;
1313 int retval = 0;
1314 u32 disp_samp_freq, n_param;
1315 u32 link_rate = 0;
1316
1317 substream = had_substream_get(intelhaddata);
1318 if (!substream)
1319 return 0;
1320
1321
1322 had_enable_audio(intelhaddata, false);
1323
1324
1325 disp_samp_freq = intelhaddata->tmds_clock_speed;
1326
1327 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1328 if (retval) {
1329 dev_err(intelhaddata->dev,
1330 "programming N value failed %#x\n", retval);
1331 goto out;
1332 }
1333
1334 if (intelhaddata->dp_output)
1335 link_rate = intelhaddata->link_rate;
1336
1337 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1338 n_param, intelhaddata);
1339
1340
1341 had_enable_audio(intelhaddata, true);
1342
1343out:
1344 had_substream_put(intelhaddata);
1345 return retval;
1346}
1347
1348
1349static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1350{
1351 struct snd_pcm_substream *substream;
1352
1353 spin_lock_irq(&intelhaddata->had_spinlock);
1354 if (intelhaddata->connected) {
1355 dev_dbg(intelhaddata->dev, "Device already connected\n");
1356 spin_unlock_irq(&intelhaddata->had_spinlock);
1357 return;
1358 }
1359
1360
1361 had_enable_audio(intelhaddata, false);
1362
1363 intelhaddata->connected = true;
1364 dev_dbg(intelhaddata->dev,
1365 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1366 __func__, __LINE__);
1367 spin_unlock_irq(&intelhaddata->had_spinlock);
1368
1369 had_build_channel_allocation_map(intelhaddata);
1370
1371
1372 substream = had_substream_get(intelhaddata);
1373 if (substream) {
1374 snd_pcm_stop_xrun(substream);
1375 had_substream_put(intelhaddata);
1376 }
1377
1378 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1379}
1380
1381
1382static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1383{
1384 struct snd_pcm_substream *substream;
1385
1386 spin_lock_irq(&intelhaddata->had_spinlock);
1387 if (!intelhaddata->connected) {
1388 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1389 spin_unlock_irq(&intelhaddata->had_spinlock);
1390 return;
1391
1392 }
1393
1394
1395 had_enable_audio(intelhaddata, false);
1396
1397 intelhaddata->connected = false;
1398 dev_dbg(intelhaddata->dev,
1399 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1400 __func__, __LINE__);
1401 spin_unlock_irq(&intelhaddata->had_spinlock);
1402
1403 kfree(intelhaddata->chmap->chmap);
1404 intelhaddata->chmap->chmap = NULL;
1405
1406
1407 substream = had_substream_get(intelhaddata);
1408 if (substream) {
1409 snd_pcm_stop_xrun(substream);
1410 had_substream_put(intelhaddata);
1411 }
1412
1413 snd_jack_report(intelhaddata->jack, 0);
1414}
1415
1416
1417
1418
1419
1420static int had_iec958_info(struct snd_kcontrol *kcontrol,
1421 struct snd_ctl_elem_info *uinfo)
1422{
1423 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1424 uinfo->count = 1;
1425 return 0;
1426}
1427
1428static int had_iec958_get(struct snd_kcontrol *kcontrol,
1429 struct snd_ctl_elem_value *ucontrol)
1430{
1431 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1432
1433 mutex_lock(&intelhaddata->mutex);
1434 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1435 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1436 ucontrol->value.iec958.status[2] =
1437 (intelhaddata->aes_bits >> 16) & 0xff;
1438 ucontrol->value.iec958.status[3] =
1439 (intelhaddata->aes_bits >> 24) & 0xff;
1440 mutex_unlock(&intelhaddata->mutex);
1441 return 0;
1442}
1443
1444static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1445 struct snd_ctl_elem_value *ucontrol)
1446{
1447 ucontrol->value.iec958.status[0] = 0xff;
1448 ucontrol->value.iec958.status[1] = 0xff;
1449 ucontrol->value.iec958.status[2] = 0xff;
1450 ucontrol->value.iec958.status[3] = 0xff;
1451 return 0;
1452}
1453
1454static int had_iec958_put(struct snd_kcontrol *kcontrol,
1455 struct snd_ctl_elem_value *ucontrol)
1456{
1457 unsigned int val;
1458 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1459 int changed = 0;
1460
1461 val = (ucontrol->value.iec958.status[0] << 0) |
1462 (ucontrol->value.iec958.status[1] << 8) |
1463 (ucontrol->value.iec958.status[2] << 16) |
1464 (ucontrol->value.iec958.status[3] << 24);
1465 mutex_lock(&intelhaddata->mutex);
1466 if (intelhaddata->aes_bits != val) {
1467 intelhaddata->aes_bits = val;
1468 changed = 1;
1469 }
1470 mutex_unlock(&intelhaddata->mutex);
1471 return changed;
1472}
1473
1474static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1475 struct snd_ctl_elem_info *uinfo)
1476{
1477 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1478 uinfo->count = HDMI_MAX_ELD_BYTES;
1479 return 0;
1480}
1481
1482static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1483 struct snd_ctl_elem_value *ucontrol)
1484{
1485 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1486
1487 mutex_lock(&intelhaddata->mutex);
1488 memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1489 HDMI_MAX_ELD_BYTES);
1490 mutex_unlock(&intelhaddata->mutex);
1491 return 0;
1492}
1493
1494static const struct snd_kcontrol_new had_controls[] = {
1495 {
1496 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1497 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1498 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1499 .info = had_iec958_info,
1500 .get = had_iec958_mask_get,
1501 },
1502 {
1503 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1504 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1505 .info = had_iec958_info,
1506 .get = had_iec958_get,
1507 .put = had_iec958_put,
1508 },
1509 {
1510 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1511 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1512 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1513 .name = "ELD",
1514 .info = had_ctl_eld_info,
1515 .get = had_ctl_eld_get,
1516 },
1517};
1518
1519
1520
1521
1522static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1523{
1524 struct snd_intelhad_card *card_ctx = dev_id;
1525 u32 audio_stat[3] = {};
1526 int pipe, port;
1527
1528 for_each_pipe(card_ctx, pipe) {
1529
1530 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe,
1531 AUD_HDMI_STATUS) &
1532 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE);
1533
1534 if (audio_stat[pipe])
1535 had_write_register_raw(card_ctx, pipe,
1536 AUD_HDMI_STATUS, audio_stat[pipe]);
1537 }
1538
1539 for_each_port(card_ctx, port) {
1540 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1541 int pipe = ctx->pipe;
1542
1543 if (pipe < 0)
1544 continue;
1545
1546 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE)
1547 had_process_buffer_done(ctx);
1548 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN)
1549 had_process_buffer_underrun(ctx);
1550 }
1551
1552 return IRQ_HANDLED;
1553}
1554
1555
1556
1557
1558static void notify_audio_lpe(struct platform_device *pdev, int port)
1559{
1560 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1561 struct snd_intelhad *ctx;
1562
1563 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
1564 if (single_port)
1565 ctx->port = port;
1566
1567 schedule_work(&ctx->hdmi_audio_wq);
1568}
1569
1570
1571static void had_audio_wq(struct work_struct *work)
1572{
1573 struct snd_intelhad *ctx =
1574 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1575 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1576 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
1577
1578 pm_runtime_get_sync(ctx->dev);
1579 mutex_lock(&ctx->mutex);
1580 if (ppdata->pipe < 0) {
1581 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
1582 __func__, ctx->port);
1583
1584 memset(ctx->eld, 0, sizeof(ctx->eld));
1585
1586 ctx->dp_output = false;
1587 ctx->tmds_clock_speed = 0;
1588 ctx->link_rate = 0;
1589
1590
1591 had_process_hot_unplug(ctx);
1592
1593 ctx->pipe = -1;
1594 } else {
1595 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1596 __func__, ctx->port, ppdata->ls_clock);
1597
1598 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
1599
1600 ctx->dp_output = ppdata->dp_output;
1601 if (ctx->dp_output) {
1602 ctx->tmds_clock_speed = 0;
1603 ctx->link_rate = ppdata->ls_clock;
1604 } else {
1605 ctx->tmds_clock_speed = ppdata->ls_clock;
1606 ctx->link_rate = 0;
1607 }
1608
1609
1610
1611
1612
1613 had_process_hot_plug(ctx);
1614
1615 ctx->pipe = ppdata->pipe;
1616
1617
1618 had_process_mode_change(ctx);
1619 }
1620
1621 mutex_unlock(&ctx->mutex);
1622 pm_runtime_mark_last_busy(ctx->dev);
1623 pm_runtime_put_autosuspend(ctx->dev);
1624}
1625
1626
1627
1628
1629static int had_create_jack(struct snd_intelhad *ctx,
1630 struct snd_pcm *pcm)
1631{
1632 char hdmi_str[32];
1633 int err;
1634
1635 snprintf(hdmi_str, sizeof(hdmi_str),
1636 "HDMI/DP,pcm=%d", pcm->device);
1637
1638 err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
1639 SND_JACK_AVOUT, &ctx->jack,
1640 true, false);
1641 if (err < 0)
1642 return err;
1643 ctx->jack->private_data = ctx;
1644 return 0;
1645}
1646
1647
1648
1649
1650
1651static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1652{
1653 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1654
1655 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
1656
1657 return 0;
1658}
1659
1660static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1661{
1662 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1663
1664 pm_runtime_mark_last_busy(dev);
1665
1666 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
1667
1668 return 0;
1669}
1670
1671
1672static void hdmi_lpe_audio_free(struct snd_card *card)
1673{
1674 struct snd_intelhad_card *card_ctx = card->private_data;
1675 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
1676 int port;
1677
1678 spin_lock_irq(&pdata->lpe_audio_slock);
1679 pdata->notify_audio_lpe = NULL;
1680 spin_unlock_irq(&pdata->lpe_audio_slock);
1681
1682 for_each_port(card_ctx, port) {
1683 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1684
1685 cancel_work_sync(&ctx->hdmi_audio_wq);
1686 }
1687
1688 if (card_ctx->mmio_start)
1689 iounmap(card_ctx->mmio_start);
1690 if (card_ctx->irq >= 0)
1691 free_irq(card_ctx->irq, card_ctx);
1692}
1693
1694
1695
1696
1697
1698
1699
1700static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1701{
1702 struct snd_card *card;
1703 struct snd_intelhad_card *card_ctx;
1704 struct snd_intelhad *ctx;
1705 struct snd_pcm *pcm;
1706 struct intel_hdmi_lpe_audio_pdata *pdata;
1707 int irq;
1708 struct resource *res_mmio;
1709 int port, ret;
1710
1711 pdata = pdev->dev.platform_data;
1712 if (!pdata) {
1713 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1714 return -EINVAL;
1715 }
1716
1717
1718 irq = platform_get_irq(pdev, 0);
1719 if (irq < 0) {
1720 dev_err(&pdev->dev, "Could not get irq resource: %d\n", irq);
1721 return irq;
1722 }
1723
1724 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1725 if (!res_mmio) {
1726 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1727 return -ENXIO;
1728 }
1729
1730
1731 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1732 THIS_MODULE, sizeof(*card_ctx), &card);
1733 if (ret)
1734 return ret;
1735
1736 card_ctx = card->private_data;
1737 card_ctx->dev = &pdev->dev;
1738 card_ctx->card = card;
1739 strcpy(card->driver, INTEL_HAD);
1740 strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1741 strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1742
1743 card_ctx->irq = -1;
1744
1745 card->private_free = hdmi_lpe_audio_free;
1746
1747 platform_set_drvdata(pdev, card_ctx);
1748
1749 card_ctx->num_pipes = pdata->num_pipes;
1750 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1751
1752 for_each_port(card_ctx, port) {
1753 ctx = &card_ctx->pcm_ctx[port];
1754 ctx->card_ctx = card_ctx;
1755 ctx->dev = card_ctx->dev;
1756 ctx->port = single_port ? -1 : port;
1757 ctx->pipe = -1;
1758
1759 spin_lock_init(&ctx->had_spinlock);
1760 mutex_init(&ctx->mutex);
1761 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1762 }
1763
1764 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1765 __func__, (unsigned int)res_mmio->start,
1766 (unsigned int)res_mmio->end);
1767
1768 card_ctx->mmio_start = ioremap_nocache(res_mmio->start,
1769 (size_t)(resource_size(res_mmio)));
1770 if (!card_ctx->mmio_start) {
1771 dev_err(&pdev->dev, "Could not get ioremap\n");
1772 ret = -EACCES;
1773 goto err;
1774 }
1775
1776
1777 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1778 pdev->name, card_ctx);
1779 if (ret < 0) {
1780 dev_err(&pdev->dev, "request_irq failed\n");
1781 goto err;
1782 }
1783
1784 card_ctx->irq = irq;
1785
1786
1787 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1788 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1789
1790 init_channel_allocations();
1791
1792 card_ctx->num_pipes = pdata->num_pipes;
1793 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1794
1795 for_each_port(card_ctx, port) {
1796 int i;
1797
1798 ctx = &card_ctx->pcm_ctx[port];
1799 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
1800 MAX_CAP_STREAMS, &pcm);
1801 if (ret)
1802 goto err;
1803
1804
1805 pcm->private_data = ctx;
1806 pcm->info_flags = 0;
1807 strlcpy(pcm->name, card->shortname, strlen(card->shortname));
1808
1809 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1810
1811
1812
1813
1814 snd_pcm_lib_preallocate_pages_for_all(pcm,
1815 SNDRV_DMA_TYPE_DEV_UC,
1816 card->dev,
1817 HAD_DEFAULT_BUFFER, HAD_MAX_BUFFER);
1818
1819
1820 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1821 struct snd_kcontrol *kctl;
1822
1823 kctl = snd_ctl_new1(&had_controls[i], ctx);
1824 if (!kctl) {
1825 ret = -ENOMEM;
1826 goto err;
1827 }
1828
1829 kctl->id.device = pcm->device;
1830
1831 ret = snd_ctl_add(card, kctl);
1832 if (ret < 0)
1833 goto err;
1834 }
1835
1836
1837 ret = had_register_chmap_ctls(ctx, pcm);
1838 if (ret < 0)
1839 goto err;
1840
1841 ret = had_create_jack(ctx, pcm);
1842 if (ret < 0)
1843 goto err;
1844 }
1845
1846 ret = snd_card_register(card);
1847 if (ret)
1848 goto err;
1849
1850 spin_lock_irq(&pdata->lpe_audio_slock);
1851 pdata->notify_audio_lpe = notify_audio_lpe;
1852 spin_unlock_irq(&pdata->lpe_audio_slock);
1853
1854 pm_runtime_use_autosuspend(&pdev->dev);
1855 pm_runtime_mark_last_busy(&pdev->dev);
1856
1857 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1858 for_each_port(card_ctx, port) {
1859 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1860
1861 schedule_work(&ctx->hdmi_audio_wq);
1862 }
1863
1864 return 0;
1865
1866err:
1867 snd_card_free(card);
1868 return ret;
1869}
1870
1871
1872
1873
1874
1875
1876static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1877{
1878 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1879
1880 snd_card_free(card_ctx->card);
1881 return 0;
1882}
1883
1884static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1885 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1886};
1887
1888static struct platform_driver hdmi_lpe_audio_driver = {
1889 .driver = {
1890 .name = "hdmi-lpe-audio",
1891 .pm = &hdmi_lpe_audio_pm,
1892 },
1893 .probe = hdmi_lpe_audio_probe,
1894 .remove = hdmi_lpe_audio_remove,
1895};
1896
1897module_platform_driver(hdmi_lpe_audio_driver);
1898MODULE_ALIAS("platform:hdmi_lpe_audio");
1899
1900MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1901MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1902MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1903MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1904MODULE_DESCRIPTION("Intel HDMI Audio driver");
1905MODULE_LICENSE("GPL v2");
1906MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
1907