linux/arch/arm/mach-s3c/mach-jive.c
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   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Copyright 2007 Simtec Electronics
   4//      Ben Dooks <ben@simtec.co.uk>
   5//
   6// http://armlinux.simtec.co.uk/
   7
   8#include <linux/kernel.h>
   9#include <linux/types.h>
  10#include <linux/interrupt.h>
  11#include <linux/list.h>
  12#include <linux/timer.h>
  13#include <linux/init.h>
  14#include <linux/gpio.h>
  15#include <linux/gpio/machine.h>
  16#include <linux/syscore_ops.h>
  17#include <linux/serial_core.h>
  18#include <linux/serial_s3c.h>
  19#include <linux/platform_device.h>
  20#include <linux/i2c.h>
  21
  22#include <video/ili9320.h>
  23
  24#include <linux/spi/spi.h>
  25#include <linux/spi/spi_gpio.h>
  26
  27#include <asm/mach/arch.h>
  28#include <asm/mach/map.h>
  29#include <asm/mach/irq.h>
  30
  31#include <linux/platform_data/mtd-nand-s3c2410.h>
  32#include <linux/platform_data/i2c-s3c2410.h>
  33
  34#include "hardware-s3c24xx.h"
  35#include "regs-gpio.h"
  36#include <linux/platform_data/fb-s3c2410.h>
  37#include "gpio-samsung.h"
  38
  39#include <asm/mach-types.h>
  40
  41#include <linux/mtd/mtd.h>
  42#include <linux/mtd/rawnand.h>
  43#include <linux/mtd/nand_ecc.h>
  44#include <linux/mtd/partitions.h>
  45
  46#include "gpio-cfg.h"
  47#include "devs.h"
  48#include "cpu.h"
  49#include "pm.h"
  50#include <linux/platform_data/usb-s3c2410_udc.h>
  51
  52#include "s3c24xx.h"
  53#include "s3c2412-power.h"
  54
  55static struct map_desc jive_iodesc[] __initdata = {
  56};
  57
  58#define UCON S3C2410_UCON_DEFAULT
  59#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
  60#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  61
  62static struct s3c2410_uartcfg jive_uartcfgs[] = {
  63        [0] = {
  64                .hwport      = 0,
  65                .flags       = 0,
  66                .ucon        = UCON,
  67                .ulcon       = ULCON,
  68                .ufcon       = UFCON,
  69        },
  70        [1] = {
  71                .hwport      = 1,
  72                .flags       = 0,
  73                .ucon        = UCON,
  74                .ulcon       = ULCON,
  75                .ufcon       = UFCON,
  76        },
  77        [2] = {
  78                .hwport      = 2,
  79                .flags       = 0,
  80                .ucon        = UCON,
  81                .ulcon       = ULCON,
  82                .ufcon       = UFCON,
  83        }
  84};
  85
  86/* Jive flash assignment
  87 *
  88 * 0x00000000-0x00028000 : uboot
  89 * 0x00028000-0x0002c000 : uboot env
  90 * 0x0002c000-0x00030000 : spare
  91 * 0x00030000-0x00200000 : zimage A
  92 * 0x00200000-0x01600000 : cramfs A
  93 * 0x01600000-0x017d0000 : zimage B
  94 * 0x017d0000-0x02bd0000 : cramfs B
  95 * 0x02bd0000-0x03fd0000 : yaffs
  96 */
  97static struct mtd_partition __initdata jive_imageA_nand_part[] = {
  98
  99#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 100        /* Don't allow access to the bootloader from linux */
 101        {
 102                .name           = "uboot",
 103                .offset         = 0,
 104                .size           = (160 * SZ_1K),
 105                .mask_flags     = MTD_WRITEABLE, /* force read-only */
 106        },
 107
 108        /* spare */
 109        {
 110                .name           = "spare",
 111                .offset         = (176 * SZ_1K),
 112                .size           = (16 * SZ_1K),
 113        },
 114#endif
 115
 116        /* booted images */
 117        {
 118                .name           = "kernel (ro)",
 119                .offset         = (192 * SZ_1K),
 120                .size           = (SZ_2M) - (192 * SZ_1K),
 121                .mask_flags     = MTD_WRITEABLE, /* force read-only */
 122        }, {
 123                .name           = "root (ro)",
 124                .offset         = (SZ_2M),
 125                .size           = (20 * SZ_1M),
 126                .mask_flags     = MTD_WRITEABLE, /* force read-only */
 127        },
 128
 129        /* yaffs */
 130        {
 131                .name           = "yaffs",
 132                .offset         = (44 * SZ_1M),
 133                .size           = (20 * SZ_1M),
 134        },
 135
 136        /* bootloader environment */
 137        {
 138                .name           = "env",
 139                .offset         = (160 * SZ_1K),
 140                .size           = (16 * SZ_1K),
 141        },
 142
 143        /* upgrade images */
 144        {
 145                .name           = "zimage",
 146                .offset         = (22 * SZ_1M),
 147                .size           = (2 * SZ_1M) - (192 * SZ_1K),
 148        }, {
 149                .name           = "cramfs",
 150                .offset         = (24 * SZ_1M) - (192*SZ_1K),
 151                .size           = (20 * SZ_1M),
 152        },
 153};
 154
 155static struct mtd_partition __initdata jive_imageB_nand_part[] = {
 156
 157#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
 158        /* Don't allow access to the bootloader from linux */
 159        {
 160                .name           = "uboot",
 161                .offset         = 0,
 162                .size           = (160 * SZ_1K),
 163                .mask_flags     = MTD_WRITEABLE, /* force read-only */
 164        },
 165
 166        /* spare */
 167        {
 168                .name           = "spare",
 169                .offset         = (176 * SZ_1K),
 170                .size           = (16 * SZ_1K),
 171        },
 172#endif
 173
 174        /* booted images */
 175        {
 176                .name           = "kernel (ro)",
 177                .offset         = (22 * SZ_1M),
 178                .size           = (2 * SZ_1M) - (192 * SZ_1K),
 179                .mask_flags     = MTD_WRITEABLE, /* force read-only */
 180        },
 181        {
 182                .name           = "root (ro)",
 183                .offset         = (24 * SZ_1M) - (192 * SZ_1K),
 184                .size           = (20 * SZ_1M),
 185                .mask_flags     = MTD_WRITEABLE, /* force read-only */
 186        },
 187
 188        /* yaffs */
 189        {
 190                .name           = "yaffs",
 191                .offset         = (44 * SZ_1M),
 192                .size           = (20 * SZ_1M),
 193        },
 194
 195        /* bootloader environment */
 196        {
 197                .name           = "env",
 198                .offset         = (160 * SZ_1K),
 199                .size           = (16 * SZ_1K),
 200        },
 201
 202        /* upgrade images */
 203        {
 204                .name           = "zimage",
 205                .offset         = (192 * SZ_1K),
 206                .size           = (2 * SZ_1M) - (192 * SZ_1K),
 207        }, {
 208                .name           = "cramfs",
 209                .offset         = (2 * SZ_1M),
 210                .size           = (20 * SZ_1M),
 211        },
 212};
 213
 214static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
 215        [0] = {
 216                .name           = "flash",
 217                .nr_chips       = 1,
 218                .nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
 219                .partitions     = jive_imageA_nand_part,
 220        },
 221};
 222
 223static struct s3c2410_platform_nand __initdata jive_nand_info = {
 224        /* set taken from osiris nand timings, possibly still conservative */
 225        .tacls          = 30,
 226        .twrph0         = 55,
 227        .twrph1         = 40,
 228        .sets           = jive_nand_sets,
 229        .nr_sets        = ARRAY_SIZE(jive_nand_sets),
 230        .engine_type    = NAND_ECC_ENGINE_TYPE_SOFT,
 231};
 232
 233static int __init jive_mtdset(char *options)
 234{
 235        struct s3c2410_nand_set *nand = &jive_nand_sets[0];
 236        unsigned long set;
 237
 238        if (options == NULL || options[0] == '\0')
 239                return 0;
 240
 241        if (kstrtoul(options, 10, &set)) {
 242                printk(KERN_ERR "failed to parse mtdset=%s\n", options);
 243                return 0;
 244        }
 245
 246        switch (set) {
 247        case 1:
 248                nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
 249                nand->partitions = jive_imageB_nand_part;
 250        case 0:
 251                /* this is already setup in the nand info */
 252                break;
 253        default:
 254                printk(KERN_ERR "Unknown mtd set %ld specified,"
 255                       "using default.", set);
 256        }
 257
 258        return 0;
 259}
 260
 261/* parse the mtdset= option given to the kernel command line */
 262__setup("mtdset=", jive_mtdset);
 263
 264/* LCD timing and setup */
 265
 266#define LCD_XRES         (240)
 267#define LCD_YRES         (320)
 268#define LCD_LEFT_MARGIN  (12)
 269#define LCD_RIGHT_MARGIN (12)
 270#define LCD_LOWER_MARGIN (12)
 271#define LCD_UPPER_MARGIN (12)
 272#define LCD_VSYNC        (2)
 273#define LCD_HSYNC        (2)
 274
 275#define LCD_REFRESH      (60)
 276
 277#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
 278#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
 279
 280static struct s3c2410fb_display jive_vgg2432a4_display[] = {
 281        [0] = {
 282                .width          = LCD_XRES,
 283                .height         = LCD_YRES,
 284                .xres           = LCD_XRES,
 285                .yres           = LCD_YRES,
 286                .left_margin    = LCD_LEFT_MARGIN,
 287                .right_margin   = LCD_RIGHT_MARGIN,
 288                .upper_margin   = LCD_UPPER_MARGIN,
 289                .lower_margin   = LCD_LOWER_MARGIN,
 290                .hsync_len      = LCD_HSYNC,
 291                .vsync_len      = LCD_VSYNC,
 292
 293                .pixclock       = (1000000000000LL /
 294                                   (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
 295
 296                .bpp            = 16,
 297                .type           = (S3C2410_LCDCON1_TFT16BPP |
 298                                   S3C2410_LCDCON1_TFT),
 299
 300                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
 301                                   S3C2410_LCDCON5_INVVLINE |
 302                                   S3C2410_LCDCON5_INVVFRAME |
 303                                   S3C2410_LCDCON5_INVVDEN |
 304                                   S3C2410_LCDCON5_PWREN),
 305        },
 306};
 307
 308/* todo - put into gpio header */
 309
 310#define S3C2410_GPCCON_MASK(x)  (3 << ((x) * 2))
 311#define S3C2410_GPDCON_MASK(x)  (3 << ((x) * 2))
 312
 313static struct s3c2410fb_mach_info jive_lcd_config = {
 314        .displays        = jive_vgg2432a4_display,
 315        .num_displays    = ARRAY_SIZE(jive_vgg2432a4_display),
 316        .default_display = 0,
 317
 318        /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
 319         * and disable the pull down resistors on pins we are using for LCD
 320         * data. */
 321
 322        .gpcup          = (0xf << 1) | (0x3f << 10),
 323        .gpcup_reg      = S3C2410_GPCUP,
 324
 325        .gpccon         = (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
 326                           S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
 327                           S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
 328                           S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
 329                           S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),
 330
 331        .gpccon_mask    = (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
 332                           S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
 333                           S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
 334                           S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
 335                           S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
 336
 337        .gpccon_reg     = S3C2410_GPCCON,
 338
 339        .gpdup          = (0x3f << 2) | (0x3f << 10),
 340
 341        .gpdup_reg      = S3C2410_GPDUP,
 342
 343        .gpdcon         = (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
 344                           S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
 345                           S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
 346                           S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
 347                           S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
 348                           S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
 349
 350        .gpdcon_mask    = (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
 351                           S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
 352                           S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
 353                           S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
 354                           S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
 355                           S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
 356
 357        .gpdcon_reg     = S3C2410_GPDCON,
 358};
 359
 360/* ILI9320 support. */
 361
 362static void jive_lcm_reset(unsigned int set)
 363{
 364        printk(KERN_DEBUG "%s(%d)\n", __func__, set);
 365
 366        gpio_set_value(S3C2410_GPG(13), set);
 367}
 368
 369#undef LCD_UPPER_MARGIN
 370#define LCD_UPPER_MARGIN 2
 371
 372static struct ili9320_platdata jive_lcm_config = {
 373        .hsize          = LCD_XRES,
 374        .vsize          = LCD_YRES,
 375
 376        .reset          = jive_lcm_reset,
 377        .suspend        = ILI9320_SUSPEND_DEEP,
 378
 379        .entry_mode     = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
 380        .display2       = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
 381                           ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
 382        .display3       = 0x0,
 383        .display4       = 0x0,
 384        .rgb_if1        = (ILI9320_RGBIF1_RIM_RGB18 |
 385                           ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
 386        .rgb_if2        = ILI9320_RGBIF2_DPL,
 387        .interface2     = 0x0,
 388        .interface3     = 0x3,
 389        .interface4     = (ILI9320_INTERFACE4_RTNE(16) |
 390                           ILI9320_INTERFACE4_DIVE(1)),
 391        .interface5     = 0x0,
 392        .interface6     = 0x0,
 393};
 394
 395/* LCD SPI support */
 396
 397static struct spi_gpio_platform_data jive_lcd_spi = {
 398        .num_chipselect = 1,
 399};
 400
 401static struct platform_device jive_device_lcdspi = {
 402        .name           = "spi_gpio",
 403        .id             = 1,
 404        .dev.platform_data = &jive_lcd_spi,
 405};
 406
 407static struct gpiod_lookup_table jive_lcdspi_gpiod_table = {
 408        .dev_id         = "spi_gpio",
 409        .table          = {
 410                GPIO_LOOKUP("GPIOG", 8,
 411                            "sck", GPIO_ACTIVE_HIGH),
 412                GPIO_LOOKUP("GPIOB", 8,
 413                            "mosi", GPIO_ACTIVE_HIGH),
 414                GPIO_LOOKUP("GPIOB", 7,
 415                            "cs", GPIO_ACTIVE_HIGH),
 416                { },
 417        },
 418};
 419
 420/* WM8750 audio code SPI definition */
 421
 422static struct spi_gpio_platform_data jive_wm8750_spi = {
 423        .num_chipselect = 1,
 424};
 425
 426static struct platform_device jive_device_wm8750 = {
 427        .name           = "spi_gpio",
 428        .id             = 2,
 429        .dev.platform_data = &jive_wm8750_spi,
 430};
 431
 432static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
 433        .dev_id         = "spi_gpio",
 434        .table          = {
 435                GPIO_LOOKUP("GPIOB", 4,
 436                            "sck", GPIO_ACTIVE_HIGH),
 437                GPIO_LOOKUP("GPIOB", 9,
 438                            "mosi", GPIO_ACTIVE_HIGH),
 439                GPIO_LOOKUP("GPIOH", 10,
 440                            "cs", GPIO_ACTIVE_HIGH),
 441                { },
 442        },
 443};
 444
 445/* JIVE SPI devices. */
 446
 447static struct spi_board_info __initdata jive_spi_devs[] = {
 448        [0] = {
 449                .modalias       = "VGG2432A4",
 450                .bus_num        = 1,
 451                .chip_select    = 0,
 452                .mode           = SPI_MODE_3,   /* CPOL=1, CPHA=1 */
 453                .max_speed_hz   = 100000,
 454                .platform_data  = &jive_lcm_config,
 455        }, {
 456                .modalias       = "WM8750",
 457                .bus_num        = 2,
 458                .chip_select    = 0,
 459                .mode           = SPI_MODE_0,   /* CPOL=0, CPHA=0 */
 460                .max_speed_hz   = 100000,
 461        },
 462};
 463
 464/* I2C bus and device configuration. */
 465
 466static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
 467        .frequency      = 80 * 1000,
 468        .flags          = S3C_IICFLG_FILTER,
 469        .sda_delay      = 2,
 470};
 471
 472static struct i2c_board_info jive_i2c_devs[] __initdata = {
 473        [0] = {
 474                I2C_BOARD_INFO("lis302dl", 0x1c),
 475                .irq    = IRQ_EINT14,
 476        },
 477};
 478
 479/* The platform devices being used. */
 480
 481static struct platform_device *jive_devices[] __initdata = {
 482        &s3c_device_ohci,
 483        &s3c_device_rtc,
 484        &s3c_device_wdt,
 485        &s3c_device_i2c0,
 486        &s3c_device_lcd,
 487        &jive_device_lcdspi,
 488        &jive_device_wm8750,
 489        &s3c_device_nand,
 490        &s3c_device_usbgadget,
 491        &s3c2412_device_dma,
 492};
 493
 494static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
 495        .vbus_pin       = S3C2410_GPG(1),               /* detect is on GPG1 */
 496};
 497
 498/* Jive power management device */
 499
 500#ifdef CONFIG_PM
 501static int jive_pm_suspend(void)
 502{
 503        /* Write the magic value u-boot uses to check for resume into
 504         * the INFORM0 register, and ensure INFORM1 is set to the
 505         * correct address to resume from. */
 506
 507        __raw_writel(0x2BED, S3C2412_INFORM0);
 508        __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
 509
 510        return 0;
 511}
 512
 513static void jive_pm_resume(void)
 514{
 515        __raw_writel(0x0, S3C2412_INFORM0);
 516}
 517
 518#else
 519#define jive_pm_suspend NULL
 520#define jive_pm_resume NULL
 521#endif
 522
 523static struct syscore_ops jive_pm_syscore_ops = {
 524        .suspend        = jive_pm_suspend,
 525        .resume         = jive_pm_resume,
 526};
 527
 528static void __init jive_map_io(void)
 529{
 530        s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
 531        s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
 532        s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
 533}
 534
 535static void __init jive_init_time(void)
 536{
 537        s3c2412_init_clocks(12000000);
 538        s3c24xx_timer_init();
 539}
 540
 541static void jive_power_off(void)
 542{
 543        printk(KERN_INFO "powering system down...\n");
 544
 545        gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
 546        gpio_free(S3C2410_GPC(5));
 547}
 548
 549static void __init jive_machine_init(void)
 550{
 551        /* register system core operations for managing low level suspend */
 552
 553        register_syscore_ops(&jive_pm_syscore_ops);
 554
 555        /* write our sleep configurations for the IO. Pull down all unused
 556         * IO, ensure that we have turned off all peripherals we do not
 557         * need, and configure the ones we do need. */
 558
 559        /* Port B sleep */
 560
 561        __raw_writel(S3C2412_SLPCON_IN(0)   |
 562                     S3C2412_SLPCON_PULL(1) |
 563                     S3C2412_SLPCON_HIGH(2) |
 564                     S3C2412_SLPCON_PULL(3) |
 565                     S3C2412_SLPCON_PULL(4) |
 566                     S3C2412_SLPCON_PULL(5) |
 567                     S3C2412_SLPCON_PULL(6) |
 568                     S3C2412_SLPCON_HIGH(7) |
 569                     S3C2412_SLPCON_PULL(8) |
 570                     S3C2412_SLPCON_PULL(9) |
 571                     S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
 572
 573        /* Port C sleep */
 574
 575        __raw_writel(S3C2412_SLPCON_PULL(0) |
 576                     S3C2412_SLPCON_PULL(1) |
 577                     S3C2412_SLPCON_PULL(2) |
 578                     S3C2412_SLPCON_PULL(3) |
 579                     S3C2412_SLPCON_PULL(4) |
 580                     S3C2412_SLPCON_PULL(5) |
 581                     S3C2412_SLPCON_LOW(6)  |
 582                     S3C2412_SLPCON_PULL(6) |
 583                     S3C2412_SLPCON_PULL(7) |
 584                     S3C2412_SLPCON_PULL(8) |
 585                     S3C2412_SLPCON_PULL(9) |
 586                     S3C2412_SLPCON_PULL(10) |
 587                     S3C2412_SLPCON_PULL(11) |
 588                     S3C2412_SLPCON_PULL(12) |
 589                     S3C2412_SLPCON_PULL(13) |
 590                     S3C2412_SLPCON_PULL(14) |
 591                     S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
 592
 593        /* Port D sleep */
 594
 595        __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
 596
 597        /* Port F sleep */
 598
 599        __raw_writel(S3C2412_SLPCON_LOW(0)  |
 600                     S3C2412_SLPCON_LOW(1)  |
 601                     S3C2412_SLPCON_LOW(2)  |
 602                     S3C2412_SLPCON_EINT(3) |
 603                     S3C2412_SLPCON_EINT(4) |
 604                     S3C2412_SLPCON_EINT(5) |
 605                     S3C2412_SLPCON_EINT(6) |
 606                     S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
 607
 608        /* Port G sleep */
 609
 610        __raw_writel(S3C2412_SLPCON_IN(0)    |
 611                     S3C2412_SLPCON_IN(1)    |
 612                     S3C2412_SLPCON_IN(2)    |
 613                     S3C2412_SLPCON_IN(3)    |
 614                     S3C2412_SLPCON_IN(4)    |
 615                     S3C2412_SLPCON_IN(5)    |
 616                     S3C2412_SLPCON_IN(6)    |
 617                     S3C2412_SLPCON_IN(7)    |
 618                     S3C2412_SLPCON_PULL(8)  |
 619                     S3C2412_SLPCON_PULL(9)  |
 620                     S3C2412_SLPCON_IN(10)   |
 621                     S3C2412_SLPCON_PULL(11) |
 622                     S3C2412_SLPCON_PULL(12) |
 623                     S3C2412_SLPCON_PULL(13) |
 624                     S3C2412_SLPCON_IN(14)   |
 625                     S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
 626
 627        /* Port H sleep */
 628
 629        __raw_writel(S3C2412_SLPCON_PULL(0) |
 630                     S3C2412_SLPCON_PULL(1) |
 631                     S3C2412_SLPCON_PULL(2) |
 632                     S3C2412_SLPCON_PULL(3) |
 633                     S3C2412_SLPCON_PULL(4) |
 634                     S3C2412_SLPCON_PULL(5) |
 635                     S3C2412_SLPCON_PULL(6) |
 636                     S3C2412_SLPCON_IN(7)   |
 637                     S3C2412_SLPCON_IN(8)   |
 638                     S3C2412_SLPCON_PULL(9) |
 639                     S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
 640
 641        /* initialise the power management now we've setup everything. */
 642
 643        s3c_pm_init();
 644
 645        /** TODO - check that this is after the cmdline option! */
 646        s3c_nand_set_platdata(&jive_nand_info);
 647
 648        gpio_request(S3C2410_GPG(13), "lcm reset");
 649        gpio_direction_output(S3C2410_GPG(13), 0);
 650
 651        gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
 652        gpio_free(S3C2410_GPB(6));
 653
 654        /* Turn off suspend on both USB ports, and switch the
 655         * selectable USB port to USB device mode. */
 656
 657        s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
 658                              S3C2410_MISCCR_USBSUSPND0 |
 659                              S3C2410_MISCCR_USBSUSPND1, 0x0);
 660
 661        s3c24xx_udc_set_platdata(&jive_udc_cfg);
 662        s3c24xx_fb_set_platdata(&jive_lcd_config);
 663
 664        spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
 665
 666        s3c_i2c0_set_platdata(&jive_i2c_cfg);
 667        i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
 668
 669        pm_power_off = jive_power_off;
 670
 671        gpiod_add_lookup_table(&jive_lcdspi_gpiod_table);
 672        gpiod_add_lookup_table(&jive_wm8750_gpiod_table);
 673        platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
 674}
 675
 676MACHINE_START(JIVE, "JIVE")
 677        /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
 678        .atag_offset    = 0x100,
 679
 680        .init_irq       = s3c2412_init_irq,
 681        .map_io         = jive_map_io,
 682        .init_machine   = jive_machine_init,
 683        .init_time      = jive_init_time,
 684MACHINE_END
 685