LXR linux/arch/m68k/bvme6000/config.c

   1/*
   2 *  arch/m68k/bvme6000/config.c
   3 *
   4 *  Copyright (C) 1997 Richard Hirst [richard@sleepie.demon.co.uk]
   5 *
   6 * Based on:
   7 *
   8 *  linux/amiga/config.c
   9 *
  10 *  Copyright (C) 1993 Hamish Macdonald
  11 *
  12 * This file is subject to the terms and conditions of the GNU General Public
  13 * License.  See the file README.legal in the main directory of this archive
  14 * for more details.
  15 */
  16
  17#include <linux/types.h>
  18#include <linux/kernel.h>
  19#include <linux/mm.h>
  20#include <linux/tty.h>
  21#include <linux/clocksource.h>
  22#include <linux/console.h>
  23#include <linux/linkage.h>
  24#include <linux/init.h>
  25#include <linux/major.h>
  26#include <linux/genhd.h>
  27#include <linux/rtc.h>
  28#include <linux/interrupt.h>
  29#include <linux/bcd.h>
  30
  31#include <asm/bootinfo.h>
  32#include <asm/bootinfo-vme.h>
  33#include <asm/byteorder.h>
  34#include <asm/setup.h>
  35#include <asm/irq.h>
  36#include <asm/traps.h>
  37#include <asm/machdep.h>
  38#include <asm/bvme6000hw.h>
  39
  40static void bvme6000_get_model(char *model);
  41extern void bvme6000_sched_init(irq_handler_t handler);
  42extern int bvme6000_hwclk (int, struct rtc_time *);
  43extern void bvme6000_reset (void);
  44void bvme6000_set_vectors (void);
  45
  46
  47int __init bvme6000_parse_bootinfo(const struct bi_record *bi)
  48{
  49        if (be16_to_cpu(bi->tag) == BI_VME_TYPE)
  50                return 0;
  51        else
  52                return 1;
  53}
  54
  55void bvme6000_reset(void)
  56{
  57        volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
  58
  59        pr_info("\r\n\nCalled bvme6000_reset\r\n"
  60                "\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r\r");
  61        /* The string of returns is to delay the reset until the whole
  62         * message is output. */
  63        /* Enable the watchdog, via PIT port C bit 4 */
  64
  65        pit->pcddr      |= 0x10;        /* WDOG enable */
  66
  67        while(1)
  68                ;
  69}
  70
  71static void bvme6000_get_model(char *model)
  72{
  73    sprintf(model, "BVME%d000", m68k_cputype == CPU_68060 ? 6 : 4);
  74}
  75
  76/*
  77 * This function is called during kernel startup to initialize
  78 * the bvme6000 IRQ handling routines.
  79 */
  80static void __init bvme6000_init_IRQ(void)
  81{
  82        m68k_setup_user_interrupt(VEC_USER, 192);
  83}
  84
  85void __init config_bvme6000(void)
  86{
  87    volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
  88
  89    /* Board type is only set by newer versions of vmelilo/tftplilo */
  90    if (!vme_brdtype) {
  91        if (m68k_cputype == CPU_68060)
  92            vme_brdtype = VME_TYPE_BVME6000;
  93        else
  94            vme_brdtype = VME_TYPE_BVME4000;
  95    }
  96#if 0
  97    /* Call bvme6000_set_vectors() so ABORT will work, along with BVMBug
  98     * debugger.  Note trap_init() will splat the abort vector, but
  99     * bvme6000_init_IRQ() will put it back again.  Hopefully. */
 100
 101    bvme6000_set_vectors();
 102#endif
 103
 104    mach_max_dma_address = 0xffffffff;
 105    mach_sched_init      = bvme6000_sched_init;
 106    mach_init_IRQ        = bvme6000_init_IRQ;
 107    mach_hwclk           = bvme6000_hwclk;
 108    mach_reset           = bvme6000_reset;
 109    mach_get_model       = bvme6000_get_model;
 110
 111    pr_info("Board is %sconfigured as a System Controller\n",
 112            *config_reg_ptr & BVME_CONFIG_SW1 ? "" : "not ");
 113
 114    /* Now do the PIT configuration */
 115
 116    pit->pgcr   = 0x00; /* Unidirectional 8 bit, no handshake for now */
 117    pit->psrr   = 0x18; /* PIACK and PIRQ functions enabled */
 118    pit->pacr   = 0x00; /* Sub Mode 00, H2 i/p, no DMA */
 119    pit->padr   = 0x00; /* Just to be tidy! */
 120    pit->paddr  = 0x00; /* All inputs for now (safest) */
 121    pit->pbcr   = 0x80; /* Sub Mode 1x, H4 i/p, no DMA */
 122    pit->pbdr   = 0xbc | (*config_reg_ptr & BVME_CONFIG_SW1 ? 0 : 0x40);
 123                        /* PRI, SYSCON?, Level3, SCC clks from xtal */
 124    pit->pbddr  = 0xf3; /* Mostly outputs */
 125    pit->pcdr   = 0x01; /* PA transceiver disabled */
 126    pit->pcddr  = 0x03; /* WDOG disable */
 127
 128    /* Disable snooping for Ethernet and VME accesses */
 129
 130    bvme_acr_addrctl = 0;
 131}
 132
 133
 134irqreturn_t bvme6000_abort_int (int irq, void *dev_id)
 135{
 136        unsigned long *new = (unsigned long *)vectors;
 137        unsigned long *old = (unsigned long *)0xf8000000;
 138
 139        /* Wait for button release */
 140        while (*(volatile unsigned char *)BVME_LOCAL_IRQ_STAT & BVME_ABORT_STATUS)
 141                ;
 142
 143        *(new+4) = *(old+4);            /* Illegal instruction */
 144        *(new+9) = *(old+9);            /* Trace */
 145        *(new+47) = *(old+47);          /* Trap #15 */
 146        *(new+0x1f) = *(old+0x1f);      /* ABORT switch */
 147        return IRQ_HANDLED;
 148}
 149
 150static u64 bvme6000_read_clk(struct clocksource *cs);
 151
 152static struct clocksource bvme6000_clk = {
 153        .name   = "rtc",
 154        .rating = 250,
 155        .read   = bvme6000_read_clk,
 156        .mask   = CLOCKSOURCE_MASK(32),
 157        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 158};
 159
 160static u32 clk_total, clk_offset;
 161
 162#define RTC_TIMER_CLOCK_FREQ 8000000
 163#define RTC_TIMER_CYCLES     (RTC_TIMER_CLOCK_FREQ / HZ)
 164#define RTC_TIMER_COUNT      ((RTC_TIMER_CYCLES / 2) - 1)
 165
 166static irqreturn_t bvme6000_timer_int (int irq, void *dev_id)
 167{
 168    irq_handler_t timer_routine = dev_id;
 169    unsigned long flags;
 170    volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
 171    unsigned char msr;
 172
 173    local_irq_save(flags);
 174    msr = rtc->msr & 0xc0;
 175    rtc->msr = msr | 0x20;              /* Ack the interrupt */
 176    clk_total += RTC_TIMER_CYCLES;
 177    clk_offset = 0;
 178    timer_routine(0, NULL);
 179    local_irq_restore(flags);
 180
 181    return IRQ_HANDLED;
 182}
 183
 184/*
 185 * Set up the RTC timer 1 to mode 2, so T1 output toggles every 5ms
 186 * (40000 x 125ns).  It will interrupt every 10ms, when T1 goes low.
 187 * So, when reading the elapsed time, you should read timer1,
 188 * subtract it from 39999, and then add 40000 if T1 is high.
 189 * That gives you the number of 125ns ticks in to the 10ms period,
 190 * so divide by 8 to get the microsecond result.
 191 */
 192
 193void bvme6000_sched_init (irq_handler_t timer_routine)
 194{
 195    volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
 196    unsigned char msr = rtc->msr & 0xc0;
 197
 198    rtc->msr = 0;       /* Ensure timer registers accessible */
 199
 200    if (request_irq(BVME_IRQ_RTC, bvme6000_timer_int, IRQF_TIMER, "timer",
 201                    timer_routine))
 202        panic ("Couldn't register timer int");
 203
 204    rtc->t1cr_omr = 0x04;       /* Mode 2, ext clk */
 205    rtc->t1msb = RTC_TIMER_COUNT >> 8;
 206    rtc->t1lsb = RTC_TIMER_COUNT & 0xff;
 207    rtc->irr_icr1 &= 0xef;      /* Route timer 1 to INTR pin */
 208    rtc->msr = 0x40;            /* Access int.cntrl, etc */
 209    rtc->pfr_icr0 = 0x80;       /* Just timer 1 ints enabled */
 210    rtc->irr_icr1 = 0;
 211    rtc->t1cr_omr = 0x0a;       /* INTR+T1 active lo, push-pull */
 212    rtc->t0cr_rtmr &= 0xdf;     /* Stop timers in standby */
 213    rtc->msr = 0;               /* Access timer 1 control */
 214    rtc->t1cr_omr = 0x05;       /* Mode 2, ext clk, GO */
 215
 216    rtc->msr = msr;
 217
 218    clocksource_register_hz(&bvme6000_clk, RTC_TIMER_CLOCK_FREQ);
 219
 220    if (request_irq(BVME_IRQ_ABORT, bvme6000_abort_int, 0,
 221                                "abort", bvme6000_abort_int))
 222        panic ("Couldn't register abort int");
 223}
 224
 225
 226/*
 227 * NOTE:  Don't accept any readings within 5us of rollover, as
 228 * the T1INT bit may be a little slow getting set.  There is also
 229 * a fault in the chip, meaning that reads may produce invalid
 230 * results...
 231 */
 232
 233static u64 bvme6000_read_clk(struct clocksource *cs)
 234{
 235    unsigned long flags;
 236    volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
 237    volatile PitRegsPtr pit = (PitRegsPtr)BVME_PIT_BASE;
 238    unsigned char msr, msb;
 239    unsigned char t1int, t1op;
 240    u32 v = 800000, ov;
 241
 242    local_irq_save(flags);
 243
 244    msr = rtc->msr & 0xc0;
 245    rtc->msr = 0;       /* Ensure timer registers accessible */
 246
 247    do {
 248        ov = v;
 249        t1int = rtc->msr & 0x20;
 250        t1op  = pit->pcdr & 0x04;
 251        rtc->t1cr_omr |= 0x40;          /* Latch timer1 */
 252        msb = rtc->t1msb;               /* Read timer1 */
 253        v = (msb << 8) | rtc->t1lsb;    /* Read timer1 */
 254    } while (t1int != (rtc->msr & 0x20) ||
 255                t1op != (pit->pcdr & 0x04) ||
 256                        abs(ov-v) > 80 ||
 257                                v > RTC_TIMER_COUNT - (RTC_TIMER_COUNT / 100));
 258
 259    v = RTC_TIMER_COUNT - v;
 260    if (!t1op)                          /* If in second half cycle.. */
 261        v += RTC_TIMER_CYCLES / 2;
 262    if (msb > 0 && t1int)
 263        clk_offset = RTC_TIMER_CYCLES;
 264    rtc->msr = msr;
 265
 266    v += clk_offset + clk_total;
 267
 268    local_irq_restore(flags);
 269
 270    return v;
 271}
 272
 273/*
 274 * Looks like op is non-zero for setting the clock, and zero for
 275 * reading the clock.
 276 *
 277 *  struct hwclk_time {
 278 *         unsigned        sec;       0..59
 279 *         unsigned        min;       0..59
 280 *         unsigned        hour;      0..23
 281 *         unsigned        day;       1..31
 282 *         unsigned        mon;       0..11
 283 *         unsigned        year;      00...
 284 *         int             wday;      0..6, 0 is Sunday, -1 means unknown/don't set
 285 * };
 286 */
 287
 288int bvme6000_hwclk(int op, struct rtc_time *t)
 289{
 290        volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
 291        unsigned char msr = rtc->msr & 0xc0;
 292
 293        rtc->msr = 0x40;        /* Ensure clock and real-time-mode-register
 294                                 * are accessible */
 295        if (op)
 296        {       /* Write.... */
 297                rtc->t0cr_rtmr = t->tm_year%4;
 298                rtc->bcd_tenms = 0;
 299                rtc->bcd_sec = bin2bcd(t->tm_sec);
 300                rtc->bcd_min = bin2bcd(t->tm_min);
 301                rtc->bcd_hr  = bin2bcd(t->tm_hour);
 302                rtc->bcd_dom = bin2bcd(t->tm_mday);
 303                rtc->bcd_mth = bin2bcd(t->tm_mon + 1);
 304                rtc->bcd_year = bin2bcd(t->tm_year%100);
 305                if (t->tm_wday >= 0)
 306                        rtc->bcd_dow = bin2bcd(t->tm_wday+1);
 307                rtc->t0cr_rtmr = t->tm_year%4 | 0x08;
 308        }
 309        else
 310        {       /* Read....  */
 311                do {
 312                        t->tm_sec  = bcd2bin(rtc->bcd_sec);
 313                        t->tm_min  = bcd2bin(rtc->bcd_min);
 314                        t->tm_hour = bcd2bin(rtc->bcd_hr);
 315                        t->tm_mday = bcd2bin(rtc->bcd_dom);
 316                        t->tm_mon  = bcd2bin(rtc->bcd_mth)-1;
 317                        t->tm_year = bcd2bin(rtc->bcd_year);
 318                        if (t->tm_year < 70)
 319                                t->tm_year += 100;
 320                        t->tm_wday = bcd2bin(rtc->bcd_dow)-1;
 321                } while (t->tm_sec != bcd2bin(rtc->bcd_sec));
 322        }
 323
 324        rtc->msr = msr;
 325
 326        return 0;
 327}
 328