1/* 2 * PCI Register definitions for the MIPS System Controller. 3 * 4 * Copyright (C) 2002, 2005 MIPS Technologies, Inc. All rights reserved. 5 * Authors: Carsten Langgaard <carstenl@mips.com> 6 * Maciej W. Rozycki <macro@mips.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H 13#define __ASM_MIPS_BOARDS_MSC01_PCI_H 14 15/* 16 * Register offset addresses 17 */ 18 19#define MSC01_PCI_ID_OFS 0x0000 20#define MSC01_PCI_SC2PMBASL_OFS 0x0208 21#define MSC01_PCI_SC2PMMSKL_OFS 0x0218 22#define MSC01_PCI_SC2PMMAPL_OFS 0x0228 23#define MSC01_PCI_SC2PIOBASL_OFS 0x0248 24#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 25#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 26#define MSC01_PCI_P2SCMSKL_OFS 0x0308 27#define MSC01_PCI_P2SCMAPL_OFS 0x0318 28#define MSC01_PCI_INTCFG_OFS 0x0600 29#define MSC01_PCI_INTSTAT_OFS 0x0608 30#define MSC01_PCI_CFGADDR_OFS 0x0610 31#define MSC01_PCI_CFGDATA_OFS 0x0618 32#define MSC01_PCI_IACK_OFS 0x0620 33#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */ 34#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */ 35#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */ 36#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */ 37#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */ 38#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */ 39#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */ 40#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */ 41#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */ 42#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */ 43#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */ 44#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */ 45#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */ 46#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */ 47#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */ 48#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */ 49#define MSC01_PCI_BAR0_OFS 0x2220 50#define MSC01_PCI_CFG_OFS 0x2380 51#define MSC01_PCI_SWAP_OFS 0x2388 52 53 54/***************************************************************************** 55 * Register encodings 56 ****************************************************************************/ 57 58#define MSC01_PCI_ID_ID_SHF 16 59#define MSC01_PCI_ID_ID_MSK 0x00ff0000 60#define MSC01_PCI_ID_ID_HOSTBRIDGE 82 61#define MSC01_PCI_ID_MAR_SHF 8 62#define MSC01_PCI_ID_MAR_MSK 0x0000ff00 63#define MSC01_PCI_ID_MIR_SHF 0 64#define MSC01_PCI_ID_MIR_MSK 0x000000ff 65 66#define MSC01_PCI_SC2PMBASL_BAS_SHF 24 67#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000 68 69#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24 70#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 71 72#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24 73#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000 74 75#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24 76#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000 77 78#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24 79#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 80 81#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24 82#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000 83 84#define MSC01_PCI_P2SCMSKL_MSK_SHF 24 85#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000 86 87#define MSC01_PCI_P2SCMAPL_MAP_SHF 24 88#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 89 90#define MSC01_PCI_INTCFG_RST_SHF 10 91#define MSC01_PCI_INTCFG_RST_MSK 0x00000400 92#define MSC01_PCI_INTCFG_RST_BIT 0x00000400 93#define MSC01_PCI_INTCFG_MWE_SHF 9 94#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 95#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 96#define MSC01_PCI_INTCFG_DTO_SHF 8 97#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 98#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 99#define MSC01_PCI_INTCFG_MA_SHF 7 100#define MSC01_PCI_INTCFG_MA_MSK 0x00000080 101#define MSC01_PCI_INTCFG_MA_BIT 0x00000080 102#define MSC01_PCI_INTCFG_TA_SHF 6 103#define MSC01_PCI_INTCFG_TA_MSK 0x00000040 104#define MSC01_PCI_INTCFG_TA_BIT 0x00000040 105#define MSC01_PCI_INTCFG_RTY_SHF 5 106#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 107#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 108#define MSC01_PCI_INTCFG_MWP_SHF 4 109#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 110#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 111#define MSC01_PCI_INTCFG_MRP_SHF 3 112#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 113#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 114#define MSC01_PCI_INTCFG_SWP_SHF 2 115#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 116#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 117#define MSC01_PCI_INTCFG_SRP_SHF 1 118#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 119#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 120#define MSC01_PCI_INTCFG_SE_SHF 0 121#define MSC01_PCI_INTCFG_SE_MSK 0x00000001 122#define MSC01_PCI_INTCFG_SE_BIT 0x00000001 123 124#define MSC01_PCI_INTSTAT_RST_SHF 10 125#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 126#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 127#define MSC01_PCI_INTSTAT_MWE_SHF 9 128#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 129#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 130#define MSC01_PCI_INTSTAT_DTO_SHF 8 131#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 132#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 133#define MSC01_PCI_INTSTAT_MA_SHF 7 134#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 135#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 136#define MSC01_PCI_INTSTAT_TA_SHF 6 137#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 138#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 139#define MSC01_PCI_INTSTAT_RTY_SHF 5 140#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 141#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 142#define MSC01_PCI_INTSTAT_MWP_SHF 4 143#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 144#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 145#define MSC01_PCI_INTSTAT_MRP_SHF 3 146#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 147#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 148#define MSC01_PCI_INTSTAT_SWP_SHF 2 149#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 150#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 151#define MSC01_PCI_INTSTAT_SRP_SHF 1 152#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 153#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 154#define MSC01_PCI_INTSTAT_SE_SHF 0 155#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 156#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 157 158#define MSC01_PCI_CFGADDR_BNUM_SHF 16 159#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 160#define MSC01_PCI_CFGADDR_DNUM_SHF 11 161#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800 162#define MSC01_PCI_CFGADDR_FNUM_SHF 8 163#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700 164#define MSC01_PCI_CFGADDR_RNUM_SHF 2 165#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc 166 167#define MSC01_PCI_CFGDATA_DATA_SHF 0 168#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff 169 170/* The defines below are ONLY valid for a MEM bar! */ 171#define MSC01_PCI_BAR0_SIZE_SHF 4 172#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 173#define MSC01_PCI_BAR0_P_SHF 3 174#define MSC01_PCI_BAR0_P_MSK 0x00000008 175#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK 176#define MSC01_PCI_BAR0_D_SHF 1 177#define MSC01_PCI_BAR0_D_MSK 0x00000006 178#define MSC01_PCI_BAR0_T_SHF 0 179#define MSC01_PCI_BAR0_T_MSK 0x00000001 180#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK 181 182 183#define MSC01_PCI_CFG_RA_SHF 17 184#define MSC01_PCI_CFG_RA_MSK 0x00020000 185#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK 186#define MSC01_PCI_CFG_G_SHF 16 187#define MSC01_PCI_CFG_G_MSK 0x00010000 188#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK 189#define MSC01_PCI_CFG_EN_SHF 15 190#define MSC01_PCI_CFG_EN_MSK 0x00008000 191#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK 192#define MSC01_PCI_CFG_MAXRTRY_SHF 0 193#define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff 194 195#define MSC01_PCI_SWAP_IO_SHF 18 196#define MSC01_PCI_SWAP_IO_MSK 0x000c0000 197#define MSC01_PCI_SWAP_MEM_SHF 16 198#define MSC01_PCI_SWAP_MEM_MSK 0x00030000 199#define MSC01_PCI_SWAP_BAR0_SHF 0 200#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003 201#define MSC01_PCI_SWAP_NOSWAP 0 202#define MSC01_PCI_SWAP_BYTESWAP 1 203 204/* 205 * MIPS System controller PCI register base. 206 * 207 * FIXME - are these macros specific to Malta and co or to the MSC? If the 208 * latter, they should be moved elsewhere. 209 */ 210#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 211#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000 212 213extern unsigned long _pcictrl_msc; 214 215#define MSC01_PCI_REG_BASE _pcictrl_msc 216 217#define MSC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) 218#define MSC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) 219 220/* 221 * Registers absolute addresses 222 */ 223 224#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) 225#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) 226#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) 227#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) 228#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) 229#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) 230#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) 231#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) 232#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) 233#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) 234#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) 235#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) 236#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) 237#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) 238#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) 239#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) 240#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS) 241#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS) 242#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS) 243#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS) 244#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS) 245#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS) 246#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS) 247#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS) 248#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS) 249#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 250#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 251#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 252#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 253#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) 254#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) 255#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) 256#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) 257 258#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */ 259