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8#ifndef _ASM_POWERPC_OPAL_H
9#define _ASM_POWERPC_OPAL_H
10
11#include <asm/opal-api.h>
12
13#ifndef __ASSEMBLY__
14
15#include <linux/notifier.h>
16
17
18#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
19
20
21#define OPAL_BUSY_DELAY_MS 10
22
23
24extern struct kobject *opal_kobj;
25
26
27extern struct device_node *opal_node;
28
29
30int64_t opal_invalid_call(void);
31int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
32int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
33 uint64_t bdf);
34int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
35 uint64_t lpcr);
36int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
37 uint64_t addr, uint64_t PE_mask);
38int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
39 uint64_t PE_handle);
40int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
41 uint64_t rate_phys, uint32_t size);
42
43int64_t opal_console_write(int64_t term_number, __be64 *length,
44 const uint8_t *buffer);
45int64_t opal_console_read(int64_t term_number, __be64 *length,
46 uint8_t *buffer);
47int64_t opal_console_write_buffer_space(int64_t term_number,
48 __be64 *length);
49int64_t opal_console_flush(int64_t term_number);
50int64_t opal_rtc_read(__be32 *year_month_day,
51 __be64 *hour_minute_second_millisecond);
52int64_t opal_rtc_write(uint32_t year_month_day,
53 uint64_t hour_minute_second_millisecond);
54int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
55int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
56 uint32_t hour_min);
57int64_t opal_cec_power_down(uint64_t request);
58int64_t opal_cec_reboot(void);
59int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
60int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
61int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
62int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
63int64_t opal_poll_events(__be64 *outstanding_event_mask);
64int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
65 uint64_t tce_mem_size);
66int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
67 uint64_t tce_mem_size);
68int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
69 uint64_t offset, uint8_t *data);
70int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
71 uint64_t offset, __be16 *data);
72int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
73 uint64_t offset, __be32 *data);
74int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
75 uint64_t offset, uint8_t data);
76int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
77 uint64_t offset, uint16_t data);
78int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
79 uint64_t offset, uint32_t data);
80int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
81int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
82int64_t opal_register_exception_handler(uint64_t opal_exception,
83 uint64_t handler_address,
84 uint64_t glue_cache_line);
85int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
86 uint8_t *freeze_state,
87 __be16 *pci_error_type,
88 __be64 *phb_status);
89int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
90 uint64_t eeh_action_token);
91int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
92 uint64_t eeh_action_token);
93int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
94 uint32_t func, uint64_t addr, uint64_t mask);
95int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
96
97
98
99int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
100 uint16_t window_num, uint16_t enable);
101int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
102 uint16_t window_num,
103 uint64_t starting_real_address,
104 uint64_t starting_pci_address,
105 uint64_t size);
106int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
107 uint16_t window_type, uint16_t window_num,
108 uint16_t segment_num);
109int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
110 uint64_t ivt_addr, uint64_t ivt_len,
111 uint64_t reject_array_addr,
112 uint64_t peltv_addr);
113int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
114 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
115 uint8_t pe_action);
116int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
117 uint8_t state);
118int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
119int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
120 uint32_t state);
121int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
122 uint8_t *p_bit, uint8_t *q_bit);
123int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
124 uint8_t p_bit, uint8_t q_bit);
125int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
126int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
127 uint32_t xive_num);
128int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
129 __be32 *interrupt_source_number);
130int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
131 uint8_t msi_range, __be32 *msi_address,
132 __be32 *message_data);
133int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
134 uint32_t xive_num, uint8_t msi_range,
135 __be64 *msi_address, __be32 *message_data);
136int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
137int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
138int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
139int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
140 uint16_t tce_levels, uint64_t tce_table_addr,
141 uint64_t tce_table_size, uint64_t tce_page_size);
142int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
143 uint16_t dma_window_number, uint64_t pci_start_addr,
144 uint64_t pci_mem_size);
145int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
146
147int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
148 uint64_t diag_buffer_len);
149int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
150 uint64_t diag_buffer_len);
151int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
152 uint64_t diag_buffer_len);
153int64_t opal_pci_fence_phb(uint64_t phb_id);
154int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
155int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
156int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
157int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
158int64_t opal_get_dpo_status(__be64 *dpo_timeout);
159int64_t opal_set_system_attention_led(uint8_t led_action);
160int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
161 __be16 *pci_error_type, __be16 *severity);
162int64_t opal_pci_poll(uint64_t id);
163int64_t opal_return_cpu(void);
164int64_t opal_check_token(uint64_t token);
165int64_t opal_reinit_cpus(uint64_t flags);
166
167int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
168int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
169
170int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
171 uint32_t addr, uint32_t data, uint32_t sz);
172int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
173 uint32_t addr, __be32 *data, uint32_t sz);
174
175int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
176int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
177int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
178int64_t opal_send_ack_elog(uint64_t log_id);
179void opal_resend_pending_logs(void);
180
181int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
182int64_t opal_manage_flash(uint8_t op);
183int64_t opal_update_flash(uint64_t blk_list);
184int64_t opal_dump_init(uint8_t dump_type);
185int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
186int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
187int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
188int64_t opal_dump_ack(uint32_t dump_id);
189int64_t opal_dump_resend_notification(void);
190
191int64_t opal_get_msg(uint64_t buffer, uint64_t size);
192int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
193 uint64_t num_lines);
194int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
195int64_t opal_sync_host_reboot(void);
196int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
197 uint64_t length);
198int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
199 uint64_t length);
200int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
201int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
202int64_t opal_handle_hmi(void);
203int64_t opal_handle_hmi2(__be64 *out_flags);
204int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
205int64_t opal_unregister_dump_region(uint32_t id);
206int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
207int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
208int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
209int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
210int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
211int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
212 uint64_t msg_len);
213int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
214 uint64_t *msg_len);
215int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
216 struct opal_i2c_request *oreq);
217int64_t opal_prd_msg(struct opal_prd_msg *msg);
218int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
219 __be64 *led_value, __be64 *max_led_type);
220int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
221 const u64 led_value, __be64 *max_led_type);
222
223int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
224 uint64_t size, uint64_t token);
225int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
226 uint64_t size, uint64_t token);
227int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
228 uint64_t token);
229int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
230int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
231int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
232int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
233 uint64_t data);
234int64_t opal_pci_poll2(uint64_t id, uint64_t data);
235
236int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
237int64_t opal_int_set_cppr(uint8_t cppr);
238int64_t opal_int_eoi(uint32_t xirr);
239int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
240int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
241 uint32_t pe_num, uint32_t tce_size,
242 uint64_t dma_addr, uint32_t npages);
243int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
244int64_t opal_xive_reset(uint64_t version);
245int64_t opal_xive_get_irq_info(uint32_t girq,
246 __be64 *out_flags,
247 __be64 *out_eoi_page,
248 __be64 *out_trig_page,
249 __be32 *out_esb_shift,
250 __be32 *out_src_chip);
251int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
252 uint8_t *out_prio, __be32 *out_lirq);
253int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
254 uint32_t lirq);
255int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
256 __be64 *out_qpage,
257 __be64 *out_qsize,
258 __be64 *out_qeoi_page,
259 __be32 *out_escalate_irq,
260 __be64 *out_qflags);
261int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
262 uint64_t qpage,
263 uint64_t qsize,
264 uint64_t qflags);
265int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
266int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
267int64_t opal_xive_free_vp_block(uint64_t vp);
268int64_t opal_xive_get_vp_info(uint64_t vp,
269 __be64 *out_flags,
270 __be64 *out_cam_value,
271 __be64 *out_report_cl_pair,
272 __be32 *out_chip_id);
273int64_t opal_xive_set_vp_info(uint64_t vp,
274 uint64_t flags,
275 uint64_t report_cl_pair);
276int64_t opal_xive_allocate_irq_raw(uint32_t chip_id);
277int64_t opal_xive_free_irq(uint32_t girq);
278int64_t opal_xive_sync(uint32_t type, uint32_t id);
279int64_t opal_xive_dump(uint32_t type, uint32_t id);
280int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
281 __be32 *out_qtoggle,
282 __be32 *out_qindex);
283int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
284 uint32_t qtoggle,
285 uint32_t qindex);
286int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
287
288int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
289 uint64_t cpu_pir);
290int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
291int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
292
293int opal_get_powercap(u32 handle, int token, u32 *pcap);
294int opal_set_powercap(u32 handle, int token, u32 pcap);
295int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
296int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
297int opal_sensor_group_clear(u32 group_hndl, int token);
298int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
299int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
300
301int opal_secvar_get(const char *key, uint64_t key_len, u8 *data,
302 uint64_t *data_size);
303int opal_secvar_get_next(const char *key, uint64_t *key_len,
304 uint64_t key_buf_size);
305int opal_secvar_enqueue_update(const char *key, uint64_t key_len, u8 *data,
306 uint64_t data_size);
307
308s64 opal_mpipl_update(enum opal_mpipl_ops op, u64 src, u64 dest, u64 size);
309s64 opal_mpipl_register_tag(enum opal_mpipl_tags tag, u64 addr);
310s64 opal_mpipl_query_tag(enum opal_mpipl_tags tag, u64 *addr);
311
312s64 opal_signal_system_reset(s32 cpu);
313s64 opal_quiesce(u64 shutdown_type, s32 cpu);
314
315
316extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
317 int depth, void *data);
318extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
319 const char *uname, int depth, void *data);
320extern void opal_configure_cores(void);
321
322extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
323extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
324extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
325extern int opal_flush_chars(uint32_t vtermno, bool wait);
326extern int opal_flush_console(uint32_t vtermno);
327
328extern void hvc_opal_init_early(void);
329
330extern int opal_notifier_register(struct notifier_block *nb);
331extern int opal_notifier_unregister(struct notifier_block *nb);
332
333extern int opal_message_notifier_register(enum opal_msg_type msg_type,
334 struct notifier_block *nb);
335extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
336 struct notifier_block *nb);
337extern void opal_notifier_enable(void);
338extern void opal_notifier_disable(void);
339extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
340
341extern int opal_async_get_token_interruptible(void);
342extern int opal_async_release_token(int token);
343extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
344extern int opal_async_wait_response_interruptible(uint64_t token,
345 struct opal_msg *msg);
346extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
347extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
348extern int sensor_group_enable(u32 grp_hndl, bool enable);
349
350struct rtc_time;
351extern time64_t opal_get_boot_time(void);
352extern void opal_nvram_init(void);
353extern void opal_flash_update_init(void);
354extern void opal_flash_update_print_message(void);
355extern int opal_elog_init(void);
356extern void opal_platform_dump_init(void);
357extern void opal_sys_param_init(void);
358extern void opal_msglog_init(void);
359extern void opal_msglog_sysfs_init(void);
360extern int opal_async_comp_init(void);
361extern int opal_sensor_init(void);
362extern int opal_hmi_handler_init(void);
363extern int opal_event_init(void);
364int opal_power_control_init(void);
365
366extern int opal_machine_check(struct pt_regs *regs);
367extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
368extern int opal_hmi_exception_early(struct pt_regs *regs);
369extern int opal_hmi_exception_early2(struct pt_regs *regs);
370extern int opal_handle_hmi_exception(struct pt_regs *regs);
371
372extern void opal_shutdown(void);
373extern int opal_resync_timebase(void);
374
375extern void opal_lpc_init(void);
376
377extern void opal_kmsg_init(void);
378
379extern int opal_event_request(unsigned int opal_event_nr);
380
381struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
382 unsigned long vmalloc_size);
383void opal_free_sg_list(struct opal_sg_list *sg);
384
385extern int opal_error_code(int rc);
386
387ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
388
389static inline int opal_get_async_rc(struct opal_msg msg)
390{
391 if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
392 return OPAL_PARAMETER;
393 else
394 return be64_to_cpu(msg.params[1]);
395}
396
397void opal_wake_poller(void);
398
399void opal_powercap_init(void);
400void opal_psr_init(void);
401void opal_sensor_groups_init(void);
402
403#endif
404
405#endif
406
