1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * 6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 8 * Adapted for Power Macintosh by Paul Mackerras. 9 * Low-level exception handlers and MMU support 10 * rewritten by Paul Mackerras. 11 * Copyright (C) 1996 Paul Mackerras. 12 * 13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 15 * 16 * This file contains the entry point for the 64-bit kernel along 17 * with some early initialization code common to all 64-bit powerpc 18 * variants. 19 */ 20 21#include <linux/threads.h> 22#include <linux/init.h> 23#include <asm/reg.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/ppc_asm.h> 27#include <asm/head-64.h> 28#include <asm/asm-offsets.h> 29#include <asm/bug.h> 30#include <asm/cputable.h> 31#include <asm/setup.h> 32#include <asm/hvcall.h> 33#include <asm/thread_info.h> 34#include <asm/firmware.h> 35#include <asm/page_64.h> 36#include <asm/irqflags.h> 37#include <asm/kvm_book3s_asm.h> 38#include <asm/ptrace.h> 39#include <asm/hw_irq.h> 40#include <asm/cputhreads.h> 41#include <asm/ppc-opcode.h> 42#include <asm/export.h> 43#include <asm/feature-fixups.h> 44 45/* The physical memory is laid out such that the secondary processor 46 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 47 * using the layout described in exceptions-64s.S 48 */ 49 50/* 51 * Entering into this code we make the following assumptions: 52 * 53 * For pSeries or server processors: 54 * 1. The MMU is off & open firmware is running in real mode. 55 * 2. The primary CPU enters at __start. 56 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary 57 * CPUs will enter as directed by "start-cpu" RTAS call, which is 58 * generic_secondary_smp_init, with PIR in r3. 59 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as 60 * directed by the "start-cpu" RTS call, with PIR in r3. 61 * -or- For OPAL entry: 62 * 1. The MMU is off, processor in HV mode. 63 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base 64 * in r8, and entry in r9 for debugging purposes. 65 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which 66 * is at generic_secondary_smp_init, with PIR in r3. 67 * 68 * For Book3E processors: 69 * 1. The MMU is on running in AS0 in a state defined in ePAPR 70 * 2. The kernel is entered at __start 71 */ 72 73OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) 74USE_FIXED_SECTION(first_256B) 75 /* 76 * Offsets are relative from the start of fixed section, and 77 * first_256B starts at 0. Offsets are a bit easier to use here 78 * than the fixed section entry macros. 79 */ 80 . = 0x0 81_GLOBAL(__start) 82 /* NOP this out unconditionally */ 83BEGIN_FTR_SECTION 84 FIXUP_ENDIAN 85 b __start_initialization_multiplatform 86END_FTR_SECTION(0, 1) 87 88 /* Catch branch to 0 in real mode */ 89 trap 90 91 /* Secondary processors spin on this value until it becomes non-zero. 92 * When non-zero, it contains the real address of the function the cpu 93 * should jump to. 94 */ 95 .balign 8 96 .globl __secondary_hold_spinloop 97__secondary_hold_spinloop: 98 .8byte 0x0 99 100 /* Secondary processors write this value with their cpu # */ 101 /* after they enter the spin loop immediately below. */ 102 .globl __secondary_hold_acknowledge 103__secondary_hold_acknowledge: 104 .8byte 0x0 105 106#ifdef CONFIG_RELOCATABLE 107 /* This flag is set to 1 by a loader if the kernel should run 108 * at the loaded address instead of the linked address. This 109 * is used by kexec-tools to keep the the kdump kernel in the 110 * crash_kernel region. The loader is responsible for 111 * observing the alignment requirement. 112 */ 113 114#ifdef CONFIG_RELOCATABLE_TEST 115#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ 116#else 117#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ 118#endif 119 120 /* Do not move this variable as kexec-tools knows about it. */ 121 . = 0x5c 122 .globl __run_at_load 123__run_at_load: 124DEFINE_FIXED_SYMBOL(__run_at_load) 125 .long RUN_AT_LOAD_DEFAULT 126#endif 127 128 . = 0x60 129/* 130 * The following code is used to hold secondary processors 131 * in a spin loop after they have entered the kernel, but 132 * before the bulk of the kernel has been relocated. This code 133 * is relocated to physical address 0x60 before prom_init is run. 134 * All of it must fit below the first exception vector at 0x100. 135 * Use .globl here not _GLOBAL because we want __secondary_hold 136 * to be the actual text address, not a descriptor. 137 */ 138 .globl __secondary_hold 139__secondary_hold: 140 FIXUP_ENDIAN 141#ifndef CONFIG_PPC_BOOK3E 142 mfmsr r24 143 ori r24,r24,MSR_RI 144 mtmsrd r24 /* RI on */ 145#endif 146 /* Grab our physical cpu number */ 147 mr r24,r3 148 /* stash r4 for book3e */ 149 mr r25,r4 150 151 /* Tell the master cpu we're here */ 152 /* Relocation is off & we are located at an address less */ 153 /* than 0x100, so only need to grab low order offset. */ 154 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0) 155 sync 156 157 li r26,0 158#ifdef CONFIG_PPC_BOOK3E 159 tovirt(r26,r26) 160#endif 161 /* All secondary cpus wait here until told to start. */ 162100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26) 163 cmpdi 0,r12,0 164 beq 100b 165 166#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) 167#ifdef CONFIG_PPC_BOOK3E 168 tovirt(r12,r12) 169#endif 170 mtctr r12 171 mr r3,r24 172 /* 173 * it may be the case that other platforms have r4 right to 174 * begin with, this gives us some safety in case it is not 175 */ 176#ifdef CONFIG_PPC_BOOK3E 177 mr r4,r25 178#else 179 li r4,0 180#endif 181 /* Make sure that patched code is visible */ 182 isync 183 bctr 184#else 1850: trap 186 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 187#endif 188CLOSE_FIXED_SECTION(first_256B) 189 190/* This value is used to mark exception frames on the stack. */ 191 .section ".toc","aw" 192exception_marker: 193 .tc ID_72656773_68657265[TC],0x7265677368657265 194 .previous 195 196/* 197 * On server, we include the exception vectors code here as it 198 * relies on absolute addressing which is only possible within 199 * this compilation unit 200 */ 201#ifdef CONFIG_PPC_BOOK3S 202#include "exceptions-64s.S" 203#else 204OPEN_TEXT_SECTION(0x100) 205#endif 206 207USE_TEXT_SECTION() 208 209#ifdef CONFIG_PPC_BOOK3E 210/* 211 * The booting_thread_hwid holds the thread id we want to boot in cpu 212 * hotplug case. It is set by cpu hotplug code, and is invalid by default. 213 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] 214 * bit field. 215 */ 216 .globl booting_thread_hwid 217booting_thread_hwid: 218 .long INVALID_THREAD_HWID 219 .align 3 220/* 221 * start a thread in the same core 222 * input parameters: 223 * r3 = the thread physical id 224 * r4 = the entry point where thread starts 225 */ 226_GLOBAL(book3e_start_thread) 227 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) 228 cmpwi r3, 0 229 beq 10f 230 cmpwi r3, 1 231 beq 11f 232 /* If the thread id is invalid, just exit. */ 233 b 13f 23410: 235 MTTMR(TMRN_IMSR0, 5) 236 MTTMR(TMRN_INIA0, 4) 237 b 12f 23811: 239 MTTMR(TMRN_IMSR1, 5) 240 MTTMR(TMRN_INIA1, 4) 24112: 242 isync 243 li r6, 1 244 sld r6, r6, r3 245 mtspr SPRN_TENS, r6 24613: 247 blr 248 249/* 250 * stop a thread in the same core 251 * input parameter: 252 * r3 = the thread physical id 253 */ 254_GLOBAL(book3e_stop_thread) 255 cmpwi r3, 0 256 beq 10f 257 cmpwi r3, 1 258 beq 10f 259 /* If the thread id is invalid, just exit. */ 260 b 13f 26110: 262 li r4, 1 263 sld r4, r4, r3 264 mtspr SPRN_TENC, r4 26513: 266 blr 267 268_GLOBAL(fsl_secondary_thread_init) 269 mfspr r4,SPRN_BUCSR 270 271 /* Enable branch prediction */ 272 lis r3,BUCSR_INIT@h 273 ori r3,r3,BUCSR_INIT@l 274 mtspr SPRN_BUCSR,r3 275 isync 276 277 /* 278 * Fix PIR to match the linear numbering in the device tree. 279 * 280 * On e6500, the reset value of PIR uses the low three bits for 281 * the thread within a core, and the upper bits for the core 282 * number. There are two threads per core, so shift everything 283 * but the low bit right by two bits so that the cpu numbering is 284 * continuous. 285 * 286 * If the old value of BUCSR is non-zero, this thread has run 287 * before. Thus, we assume we are coming from kexec or a similar 288 * scenario, and PIR is already set to the correct value. This 289 * is a bit of a hack, but there are limited opportunities for 290 * getting information into the thread and the alternatives 291 * seemed like they'd be overkill. We can't tell just by looking 292 * at the old PIR value which state it's in, since the same value 293 * could be valid for one thread out of reset and for a different 294 * thread in Linux. 295 */ 296 297 mfspr r3, SPRN_PIR 298 cmpwi r4,0 299 bne 1f 300 rlwimi r3, r3, 30, 2, 30 301 mtspr SPRN_PIR, r3 3021: 303 mr r24,r3 304 305 /* turn on 64-bit mode */ 306 bl enable_64b_mode 307 308 /* get a valid TOC pointer, wherever we're mapped at */ 309 bl relative_toc 310 tovirt(r2,r2) 311 312 /* Book3E initialization */ 313 mr r3,r24 314 bl book3e_secondary_thread_init 315 b generic_secondary_common_init 316 317#endif /* CONFIG_PPC_BOOK3E */ 318 319/* 320 * On pSeries and most other platforms, secondary processors spin 321 * in the following code. 322 * At entry, r3 = this processor's number (physical cpu id) 323 * 324 * On Book3E, r4 = 1 to indicate that the initial TLB entry for 325 * this core already exists (setup via some other mechanism such 326 * as SCOM before entry). 327 */ 328_GLOBAL(generic_secondary_smp_init) 329 FIXUP_ENDIAN 330 mr r24,r3 331 mr r25,r4 332 333 /* turn on 64-bit mode */ 334 bl enable_64b_mode 335 336 /* get a valid TOC pointer, wherever we're mapped at */ 337 bl relative_toc 338 tovirt(r2,r2) 339 340#ifdef CONFIG_PPC_BOOK3E 341 /* Book3E initialization */ 342 mr r3,r24 343 mr r4,r25 344 bl book3e_secondary_core_init 345 346/* 347 * After common core init has finished, check if the current thread is the 348 * one we wanted to boot. If not, start the specified thread and stop the 349 * current thread. 350 */ 351 LOAD_REG_ADDR(r4, booting_thread_hwid) 352 lwz r3, 0(r4) 353 li r5, INVALID_THREAD_HWID 354 cmpw r3, r5 355 beq 20f 356 357 /* 358 * The value of booting_thread_hwid has been stored in r3, 359 * so make it invalid. 360 */ 361 stw r5, 0(r4) 362 363 /* 364 * Get the current thread id and check if it is the one we wanted. 365 * If not, start the one specified in booting_thread_hwid and stop 366 * the current thread. 367 */ 368 mfspr r8, SPRN_TIR 369 cmpw r3, r8 370 beq 20f 371 372 /* start the specified thread */ 373 LOAD_REG_ADDR(r5, fsl_secondary_thread_init) 374 ld r4, 0(r5) 375 bl book3e_start_thread 376 377 /* stop the current thread */ 378 mr r3, r8 379 bl book3e_stop_thread 38010: 381 b 10b 38220: 383#endif 384 385generic_secondary_common_init: 386 /* Set up a paca value for this processor. Since we have the 387 * physical cpu id in r24, we need to search the pacas to find 388 * which logical id maps to our physical one. 389 */ 390#ifndef CONFIG_SMP 391 b kexec_wait /* wait for next kernel if !SMP */ 392#else 393 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ 394 ld r8,0(r8) /* Get base vaddr of array */ 395 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ 396 lwz r7,0(r7) /* also the max paca allocated */ 397 li r5,0 /* logical cpu id */ 3981: 399 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ 400 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ 401 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ 402 cmpw r6,r24 /* Compare to our id */ 403 beq 2f 404 addi r5,r5,1 405 cmpw r5,r7 /* Check if more pacas exist */ 406 blt 1b 407 408 mr r3,r24 /* not found, copy phys to r3 */ 409 b kexec_wait /* next kernel might do better */ 410 4112: SET_PACA(r13) 412#ifdef CONFIG_PPC_BOOK3E 413 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ 414 mtspr SPRN_SPRG_TLB_EXFRAME,r12 415#endif 416 417 /* From now on, r24 is expected to be logical cpuid */ 418 mr r24,r5 419 420 /* See if we need to call a cpu state restore handler */ 421 LOAD_REG_ADDR(r23, cur_cpu_spec) 422 ld r23,0(r23) 423 ld r12,CPU_SPEC_RESTORE(r23) 424 cmpdi 0,r12,0 425 beq 3f 426#ifdef PPC64_ELF_ABI_v1 427 ld r12,0(r12) 428#endif 429 mtctr r12 430 bctrl 431 4323: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ 433 lwarx r4,0,r3 434 subi r4,r4,1 435 stwcx. r4,0,r3 436 bne 3b 437 isync 438 4394: HMT_LOW 440 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ 441 /* start. */ 442 cmpwi 0,r23,0 443 beq 4b /* Loop until told to go */ 444 445 sync /* order paca.run and cur_cpu_spec */ 446 isync /* In case code patching happened */ 447 448 /* Create a temp kernel stack for use before relocation is on. */ 449 ld r1,PACAEMERGSP(r13) 450 subi r1,r1,STACK_FRAME_OVERHEAD 451 452 b __secondary_start 453#endif /* SMP */ 454 455/* 456 * Turn the MMU off. 457 * Assumes we're mapped EA == RA if the MMU is on. 458 */ 459#ifdef CONFIG_PPC_BOOK3S 460__mmu_off: 461 mfmsr r3 462 andi. r0,r3,MSR_IR|MSR_DR 463 beqlr 464 mflr r4 465 andc r3,r3,r0 466 mtspr SPRN_SRR0,r4 467 mtspr SPRN_SRR1,r3 468 sync 469 rfid 470 b . /* prevent speculative execution */ 471#endif 472 473 474/* 475 * Here is our main kernel entry point. We support currently 2 kind of entries 476 * depending on the value of r5. 477 * 478 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content 479 * in r3...r7 480 * 481 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the 482 * DT block, r4 is a physical pointer to the kernel itself 483 * 484 */ 485__start_initialization_multiplatform: 486 /* Make sure we are running in 64 bits mode */ 487 bl enable_64b_mode 488 489 /* Get TOC pointer (current runtime address) */ 490 bl relative_toc 491 492 /* find out where we are now */ 493 bcl 20,31,$+4 4940: mflr r26 /* r26 = runtime addr here */ 495 addis r26,r26,(_stext - 0b)@ha 496 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ 497 498 /* 499 * Are we booted from a PROM Of-type client-interface ? 500 */ 501 cmpldi cr0,r5,0 502 beq 1f 503 b __boot_from_prom /* yes -> prom */ 5041: 505 /* Save parameters */ 506 mr r31,r3 507 mr r30,r4 508#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 509 /* Save OPAL entry */ 510 mr r28,r8 511 mr r29,r9 512#endif 513 514#ifdef CONFIG_PPC_BOOK3E 515 bl start_initialization_book3e 516 b __after_prom_start 517#else 518 /* Setup some critical 970 SPRs before switching MMU off */ 519 mfspr r0,SPRN_PVR 520 srwi r0,r0,16 521 cmpwi r0,0x39 /* 970 */ 522 beq 1f 523 cmpwi r0,0x3c /* 970FX */ 524 beq 1f 525 cmpwi r0,0x44 /* 970MP */ 526 beq 1f 527 cmpwi r0,0x45 /* 970GX */ 528 bne 2f 5291: bl __cpu_preinit_ppc970 5302: 531 532 /* Switch off MMU if not already off */ 533 bl __mmu_off 534 b __after_prom_start 535#endif /* CONFIG_PPC_BOOK3E */ 536 537__REF 538__boot_from_prom: 539#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE 540 /* Save parameters */ 541 mr r31,r3 542 mr r30,r4 543 mr r29,r5 544 mr r28,r6 545 mr r27,r7 546 547 /* 548 * Align the stack to 16-byte boundary 549 * Depending on the size and layout of the ELF sections in the initial 550 * boot binary, the stack pointer may be unaligned on PowerMac 551 */ 552 rldicr r1,r1,0,59 553 554#ifdef CONFIG_RELOCATABLE 555 /* Relocate code for where we are now */ 556 mr r3,r26 557 bl relocate 558#endif 559 560 /* Restore parameters */ 561 mr r3,r31 562 mr r4,r30 563 mr r5,r29 564 mr r6,r28 565 mr r7,r27 566 567 /* Do all of the interaction with OF client interface */ 568 mr r8,r26 569 bl prom_init 570#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ 571 572 /* We never return. We also hit that trap if trying to boot 573 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ 574 trap 575 .previous 576 577__after_prom_start: 578#ifdef CONFIG_RELOCATABLE 579 /* process relocations for the final address of the kernel */ 580 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ 581 sldi r25,r25,32 582#if defined(CONFIG_PPC_BOOK3E) 583 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 584#endif 585 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 586#if defined(CONFIG_PPC_BOOK3E) 587 tophys(r26,r26) 588#endif 589 cmplwi cr0,r7,1 /* flagged to stay where we are ? */ 590 bne 1f 591 add r25,r25,r26 5921: mr r3,r25 593 bl relocate 594#if defined(CONFIG_PPC_BOOK3E) 595 /* IVPR needs to be set after relocation. */ 596 bl init_core_book3e 597#endif 598#endif 599 600/* 601 * We need to run with _stext at physical address PHYSICAL_START. 602 * This will leave some code in the first 256B of 603 * real memory, which are reserved for software use. 604 * 605 * Note: This process overwrites the OF exception vectors. 606 */ 607 li r3,0 /* target addr */ 608#ifdef CONFIG_PPC_BOOK3E 609 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ 610#endif 611 mr. r4,r26 /* In some cases the loader may */ 612#if defined(CONFIG_PPC_BOOK3E) 613 tovirt(r4,r4) 614#endif 615 beq 9f /* have already put us at zero */ 616 li r6,0x100 /* Start offset, the first 0x100 */ 617 /* bytes were copied earlier. */ 618 619#ifdef CONFIG_RELOCATABLE 620/* 621 * Check if the kernel has to be running as relocatable kernel based on the 622 * variable __run_at_load, if it is set the kernel is treated as relocatable 623 * kernel, otherwise it will be moved to PHYSICAL_START 624 */ 625#if defined(CONFIG_PPC_BOOK3E) 626 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ 627#endif 628 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) 629 cmplwi cr0,r7,1 630 bne 3f 631 632#ifdef CONFIG_PPC_BOOK3E 633 LOAD_REG_ADDR(r5, __end_interrupts) 634 LOAD_REG_ADDR(r11, _stext) 635 sub r5,r5,r11 636#else 637 /* just copy interrupts */ 638 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) 639#endif 640 b 5f 6413: 642#endif 643 /* # bytes of memory to copy */ 644 lis r5,(ABS_ADDR(copy_to_here))@ha 645 addi r5,r5,(ABS_ADDR(copy_to_here))@l 646 647 bl copy_and_flush /* copy the first n bytes */ 648 /* this includes the code being */ 649 /* executed here. */ 650 /* Jump to the copy of this code that we just made */ 651 addis r8,r3,(ABS_ADDR(4f))@ha 652 addi r12,r8,(ABS_ADDR(4f))@l 653 mtctr r12 654 bctr 655 656.balign 8 657p_end: .8byte _end - copy_to_here 658 6594: 660 /* 661 * Now copy the rest of the kernel up to _end, add 662 * _end - copy_to_here to the copy limit and run again. 663 */ 664 addis r8,r26,(ABS_ADDR(p_end))@ha 665 ld r8,(ABS_ADDR(p_end))@l(r8) 666 add r5,r5,r8 6675: bl copy_and_flush /* copy the rest */ 668 6699: b start_here_multiplatform 670 671/* 672 * Copy routine used to copy the kernel to start at physical address 0 673 * and flush and invalidate the caches as needed. 674 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset 675 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. 676 * 677 * Note: this routine *only* clobbers r0, r6 and lr 678 */ 679_GLOBAL(copy_and_flush) 680 addi r5,r5,-8 681 addi r6,r6,-8 6824: li r0,8 /* Use the smallest common */ 683 /* denominator cache line */ 684 /* size. This results in */ 685 /* extra cache line flushes */ 686 /* but operation is correct. */ 687 /* Can't get cache line size */ 688 /* from NACA as it is being */ 689 /* moved too. */ 690 691 mtctr r0 /* put # words/line in ctr */ 6923: addi r6,r6,8 /* copy a cache line */ 693 ldx r0,r6,r4 694 stdx r0,r6,r3 695 bdnz 3b 696 dcbst r6,r3 /* write it to memory */ 697 sync 698 icbi r6,r3 /* flush the icache line */ 699 cmpld 0,r6,r5 700 blt 4b 701 sync 702 addi r5,r5,8 703 addi r6,r6,8 704 isync 705 blr 706 707.align 8 708copy_to_here: 709 710#ifdef CONFIG_SMP 711#ifdef CONFIG_PPC_PMAC 712/* 713 * On PowerMac, secondary processors starts from the reset vector, which 714 * is temporarily turned into a call to one of the functions below. 715 */ 716 .section ".text"; 717 .align 2 ; 718 719 .globl __secondary_start_pmac_0 720__secondary_start_pmac_0: 721 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ 722 li r24,0 723 b 1f 724 li r24,1 725 b 1f 726 li r24,2 727 b 1f 728 li r24,3 7291: 730 731_GLOBAL(pmac_secondary_start) 732 /* turn on 64-bit mode */ 733 bl enable_64b_mode 734 735 li r0,0 736 mfspr r3,SPRN_HID4 737 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ 738 sync 739 mtspr SPRN_HID4,r3 740 isync 741 sync 742 slbia 743 744 /* get TOC pointer (real address) */ 745 bl relative_toc 746 tovirt(r2,r2) 747 748 /* Copy some CPU settings from CPU 0 */ 749 bl __restore_cpu_ppc970 750 751 /* pSeries do that early though I don't think we really need it */ 752 mfmsr r3 753 ori r3,r3,MSR_RI 754 mtmsrd r3 /* RI on */ 755 756 /* Set up a paca value for this processor. */ 757 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ 758 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ 759 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ 760 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ 761 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ 762 763 /* Mark interrupts soft and hard disabled (they might be enabled 764 * in the PACA when doing hotplug) 765 */ 766 li r0,IRQS_DISABLED 767 stb r0,PACAIRQSOFTMASK(r13) 768 li r0,PACA_IRQ_HARD_DIS 769 stb r0,PACAIRQHAPPENED(r13) 770 771 /* Create a temp kernel stack for use before relocation is on. */ 772 ld r1,PACAEMERGSP(r13) 773 subi r1,r1,STACK_FRAME_OVERHEAD 774 775 b __secondary_start 776 777#endif /* CONFIG_PPC_PMAC */ 778 779/* 780 * This function is called after the master CPU has released the 781 * secondary processors. The execution environment is relocation off. 782 * The paca for this processor has the following fields initialized at 783 * this point: 784 * 1. Processor number 785 * 2. Segment table pointer (virtual address) 786 * On entry the following are set: 787 * r1 = stack pointer (real addr of temp stack) 788 * r24 = cpu# (in Linux terms) 789 * r13 = paca virtual address 790 * SPRG_PACA = paca virtual address 791 */ 792 .section ".text"; 793 .align 2 ; 794 795 .globl __secondary_start 796__secondary_start: 797 /* Set thread priority to MEDIUM */ 798 HMT_MEDIUM 799 800 /* 801 * Do early setup for this CPU, in particular initialising the MMU so we 802 * can turn it on below. This is a call to C, which is OK, we're still 803 * running on the emergency stack. 804 */ 805 bl early_setup_secondary 806 807 /* 808 * The primary has initialized our kernel stack for us in the paca, grab 809 * it and put it in r1. We must *not* use it until we turn on the MMU 810 * below, because it may not be inside the RMO. 811 */ 812 ld r1, PACAKSAVE(r13) 813 814 /* Clear backchain so we get nice backtraces */ 815 li r7,0 816 mtlr r7 817 818 /* Mark interrupts soft and hard disabled (they might be enabled 819 * in the PACA when doing hotplug) 820 */ 821 li r7,IRQS_DISABLED 822 stb r7,PACAIRQSOFTMASK(r13) 823 li r0,PACA_IRQ_HARD_DIS 824 stb r0,PACAIRQHAPPENED(r13) 825 826 /* enable MMU and jump to start_secondary */ 827 LOAD_REG_ADDR(r3, start_secondary_prolog) 828 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) 829 830 mtspr SPRN_SRR0,r3 831 mtspr SPRN_SRR1,r4 832 RFI 833 b . /* prevent speculative execution */ 834 835/* 836 * Running with relocation on at this point. All we want to do is 837 * zero the stack back-chain pointer and get the TOC virtual address 838 * before going into C code. 839 */ 840start_secondary_prolog: 841 ld r2,PACATOC(r13) 842 li r3,0 843 std r3,0(r1) /* Zero the stack frame pointer */ 844 bl start_secondary 845 b . 846/* 847 * Reset stack pointer and call start_secondary 848 * to continue with online operation when woken up 849 * from cede in cpu offline. 850 */ 851_GLOBAL(start_secondary_resume) 852 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ 853 li r3,0 854 std r3,0(r1) /* Zero the stack frame pointer */ 855 bl start_secondary 856 b . 857#endif 858 859/* 860 * This subroutine clobbers r11 and r12 861 */ 862enable_64b_mode: 863 mfmsr r11 /* grab the current MSR */ 864#ifdef CONFIG_PPC_BOOK3E 865 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 866 mtmsr r11 867#else /* CONFIG_PPC_BOOK3E */ 868 li r12,(MSR_64BIT | MSR_ISF)@highest 869 sldi r12,r12,48 870 or r11,r11,r12 871 mtmsrd r11 872 isync 873#endif 874 blr 875 876/* 877 * This puts the TOC pointer into r2, offset by 0x8000 (as expected 878 * by the toolchain). It computes the correct value for wherever we 879 * are running at the moment, using position-independent code. 880 * 881 * Note: The compiler constructs pointers using offsets from the 882 * TOC in -mcmodel=medium mode. After we relocate to 0 but before 883 * the MMU is on we need our TOC to be a virtual address otherwise 884 * these pointers will be real addresses which may get stored and 885 * accessed later with the MMU on. We use tovirt() at the call 886 * sites to handle this. 887 */ 888_GLOBAL(relative_toc) 889 mflr r0 890 bcl 20,31,$+4 8910: mflr r11 892 ld r2,(p_toc - 0b)(r11) 893 add r2,r2,r11 894 mtlr r0 895 blr 896 897.balign 8 898p_toc: .8byte __toc_start + 0x8000 - 0b 899 900/* 901 * This is where the main kernel code starts. 902 */ 903__REF 904start_here_multiplatform: 905 /* set up the TOC */ 906 bl relative_toc 907 tovirt(r2,r2) 908 909 /* Clear out the BSS. It may have been done in prom_init, 910 * already but that's irrelevant since prom_init will soon 911 * be detached from the kernel completely. Besides, we need 912 * to clear it now for kexec-style entry. 913 */ 914 LOAD_REG_ADDR(r11,__bss_stop) 915 LOAD_REG_ADDR(r8,__bss_start) 916 sub r11,r11,r8 /* bss size */ 917 addi r11,r11,7 /* round up to an even double word */ 918 srdi. r11,r11,3 /* shift right by 3 */ 919 beq 4f 920 addi r8,r8,-8 921 li r0,0 922 mtctr r11 /* zero this many doublewords */ 9233: stdu r0,8(r8) 924 bdnz 3b 9254: 926 927#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL 928 /* Setup OPAL entry */ 929 LOAD_REG_ADDR(r11, opal) 930 std r28,0(r11); 931 std r29,8(r11); 932#endif 933 934#ifndef CONFIG_PPC_BOOK3E 935 mfmsr r6 936 ori r6,r6,MSR_RI 937 mtmsrd r6 /* RI on */ 938#endif 939 940#ifdef CONFIG_RELOCATABLE 941 /* Save the physical address we're running at in kernstart_addr */ 942 LOAD_REG_ADDR(r4, kernstart_addr) 943 clrldi r0,r25,2 944 std r0,0(r4) 945#endif 946 947 /* set up a stack pointer */ 948 LOAD_REG_ADDR(r3,init_thread_union) 949 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) 950 add r1,r3,r1 951 li r0,0 952 stdu r0,-STACK_FRAME_OVERHEAD(r1) 953 954 /* 955 * Do very early kernel initializations, including initial hash table 956 * and SLB setup before we turn on relocation. 957 */ 958 959 /* Restore parameters passed from prom_init/kexec */ 960 mr r3,r31 961 LOAD_REG_ADDR(r12, DOTSYM(early_setup)) 962 mtctr r12 963 bctrl /* also sets r13 and SPRG_PACA */ 964 965 LOAD_REG_ADDR(r3, start_here_common) 966 ld r4,PACAKMSR(r13) 967 mtspr SPRN_SRR0,r3 968 mtspr SPRN_SRR1,r4 969 RFI 970 b . /* prevent speculative execution */ 971 972 /* This is where all platforms converge execution */ 973 974start_here_common: 975 /* relocation is on at this point */ 976 std r1,PACAKSAVE(r13) 977 978 /* Load the TOC (virtual address) */ 979 ld r2,PACATOC(r13) 980 981 /* Mark interrupts soft and hard disabled (they might be enabled 982 * in the PACA when doing hotplug) 983 */ 984 li r0,IRQS_DISABLED 985 stb r0,PACAIRQSOFTMASK(r13) 986 li r0,PACA_IRQ_HARD_DIS 987 stb r0,PACAIRQHAPPENED(r13) 988 989 /* Generic kernel entry */ 990 bl start_kernel 991 992 /* Not reached */ 993 trap 994 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0 995 .previous 996 997/* 998 * We put a few things here that have to be page-aligned. 999 * This stuff goes at the beginning of the bss, which is page-aligned. 1000 */
1001 .section ".bss" 1002/* 1003 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. 1004 * We will need to find a better way to fix this 1005 */ 1006 .align 16 1007 1008 .globl swapper_pg_dir 1009swapper_pg_dir: 1010 .space PGD_TABLE_SIZE 1011 1012 .globl empty_zero_page 1013empty_zero_page: 1014 .space PAGE_SIZE 1015EXPORT_SYMBOL(empty_zero_page) 1016