LXR linux/arch/x86/kernel/cpu/feat

   1// SPDX-License-Identifier: GPL-2.0
   2#include <linux/tboot.h>
   3
   4#include <asm/cpufeature.h>
   5#include <asm/msr-index.h>
   6#include <asm/processor.h>
   7#include <asm/vmx.h>
   8#include "cpu.h"
   9
  10#undef pr_fmt
  11#define pr_fmt(fmt)     "x86/cpu: " fmt
  12
  13#ifdef CONFIG_X86_VMX_FEATURE_NAMES
  14enum vmx_feature_leafs {
  15        MISC_FEATURES = 0,
  16        PRIMARY_CTLS,
  17        SECONDARY_CTLS,
  18        NR_VMX_FEATURE_WORDS,
  19};
  20
  21#define VMX_F(x) BIT(VMX_FEATURE_##x & 0x1f)
  22
  23static void init_vmx_capabilities(struct cpuinfo_x86 *c)
  24{
  25        u32 supported, funcs, ept, vpid, ign;
  26
  27        BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS);
  28
  29        /*
  30         * The high bits contain the allowed-1 settings, i.e. features that can
  31         * be turned on.  The low bits contain the allowed-0 settings, i.e.
  32         * features that can be turned off.  Ignore the allowed-0 settings,
  33         * if a feature can be turned on then it's supported.
  34         *
  35         * Use raw rdmsr() for primary processor controls and pin controls MSRs
  36         * as they exist on any CPU that supports VMX, i.e. we want the WARN if
  37         * the RDMSR faults.
  38         */
  39        rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported);
  40        c->vmx_capability[PRIMARY_CTLS] = supported;
  41
  42        rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);
  43        c->vmx_capability[SECONDARY_CTLS] = supported;
  44
  45        rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported);
  46        rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs);
  47
  48        /*
  49         * Except for EPT+VPID, which enumerates support for both in a single
  50         * MSR, low for EPT, high for VPID.
  51         */
  52        rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, &ept, &vpid);
  53
  54        /* Pin, EPT, VPID and VM-Func are merged into a single word. */
  55        WARN_ON_ONCE(supported >> 16);
  56        WARN_ON_ONCE(funcs >> 4);
  57        c->vmx_capability[MISC_FEATURES] = (supported & 0xffff) |
  58                                           ((vpid & 0x1) << 16) |
  59                                           ((funcs & 0xf) << 28);
  60
  61        /* EPT bits are full on scattered and must be manually handled. */
  62        if (ept & VMX_EPT_EXECUTE_ONLY_BIT)
  63                c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_EXECUTE_ONLY);
  64        if (ept & VMX_EPT_AD_BIT)
  65                c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_AD);
  66        if (ept & VMX_EPT_1GB_PAGE_BIT)
  67                c->vmx_capability[MISC_FEATURES] |= VMX_F(EPT_1GB);
  68
  69        /* Synthetic APIC features that are aggregates of multiple features. */
  70        if ((c->vmx_capability[PRIMARY_CTLS] & VMX_F(VIRTUAL_TPR)) &&
  71            (c->vmx_capability[SECONDARY_CTLS] & VMX_F(VIRT_APIC_ACCESSES)))
  72                c->vmx_capability[MISC_FEATURES] |= VMX_F(FLEXPRIORITY);
  73
  74        if ((c->vmx_capability[PRIMARY_CTLS] & VMX_F(VIRTUAL_TPR)) &&
  75            (c->vmx_capability[SECONDARY_CTLS] & VMX_F(APIC_REGISTER_VIRT)) &&
  76            (c->vmx_capability[SECONDARY_CTLS] & VMX_F(VIRT_INTR_DELIVERY)) &&
  77            (c->vmx_capability[MISC_FEATURES] & VMX_F(POSTED_INTR)))
  78                c->vmx_capability[MISC_FEATURES] |= VMX_F(APICV);
  79
  80        /* Set the synthetic cpufeatures to preserve /proc/cpuinfo's ABI. */
  81        if (c->vmx_capability[PRIMARY_CTLS] & VMX_F(VIRTUAL_TPR))
  82                set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
  83        if (c->vmx_capability[MISC_FEATURES] & VMX_F(FLEXPRIORITY))
  84                set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
  85        if (c->vmx_capability[MISC_FEATURES] & VMX_F(VIRTUAL_NMIS))
  86                set_cpu_cap(c, X86_FEATURE_VNMI);
  87        if (c->vmx_capability[SECONDARY_CTLS] & VMX_F(EPT))
  88                set_cpu_cap(c, X86_FEATURE_EPT);
  89        if (c->vmx_capability[MISC_FEATURES] & VMX_F(EPT_AD))
  90                set_cpu_cap(c, X86_FEATURE_EPT_AD);
  91        if (c->vmx_capability[MISC_FEATURES] & VMX_F(VPID))
  92                set_cpu_cap(c, X86_FEATURE_VPID);
  93}
  94#endif /* CONFIG_X86_VMX_FEATURE_NAMES */
  95
  96void init_ia32_feat_ctl(struct cpuinfo_x86 *c)
  97{
  98        bool tboot = tboot_enabled();
  99        u64 msr;
 100
 101        if (rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr)) {
 102                clear_cpu_cap(c, X86_FEATURE_VMX);
 103                return;
 104        }
 105
 106        if (msr & FEAT_CTL_LOCKED)
 107                goto update_caps;
 108
 109        /*
 110         * Ignore whatever value BIOS left in the MSR to avoid enabling random
 111         * features or faulting on the WRMSR.
 112         */
 113        msr = FEAT_CTL_LOCKED;
 114
 115        /*
 116         * Enable VMX if and only if the kernel may do VMXON at some point,
 117         * i.e. KVM is enabled, to avoid unnecessarily adding an attack vector
 118         * for the kernel, e.g. using VMX to hide malicious code.
 119         */
 120        if (cpu_has(c, X86_FEATURE_VMX) && IS_ENABLED(CONFIG_KVM_INTEL)) {
 121                msr |= FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX;
 122
 123                if (tboot)
 124                        msr |= FEAT_CTL_VMX_ENABLED_INSIDE_SMX;
 125        }
 126
 127        wrmsrl(MSR_IA32_FEAT_CTL, msr);
 128
 129update_caps:
 130        set_cpu_cap(c, X86_FEATURE_MSR_IA32_FEAT_CTL);
 131
 132        if (!cpu_has(c, X86_FEATURE_VMX))
 133                return;
 134
 135        if ( (tboot && !(msr & FEAT_CTL_VMX_ENABLED_INSIDE_SMX)) ||
 136            (!tboot && !(msr & FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX))) {
 137                if (IS_ENABLED(CONFIG_KVM_INTEL))
 138                        pr_err_once("VMX (%s TXT) disabled by BIOS\n",
 139                                    tboot ? "inside" : "outside");
 140                clear_cpu_cap(c, X86_FEATURE_VMX);
 141        } else {
 142#ifdef CONFIG_X86_VMX_FEATURE_NAMES
 143                init_vmx_capabilities(c);
 144#endif
 145        }
 146}
 147