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12#ifndef _ASM_X86_KVM_X86_EMULATE_H
13#define _ASM_X86_KVM_X86_EMULATE_H
14
15#include <asm/desc_defs.h>
16
17struct x86_emulate_ctxt;
18enum x86_intercept;
19enum x86_intercept_stage;
20
21struct x86_exception {
22 u8 vector;
23 bool error_code_valid;
24 u16 error_code;
25 bool nested_page_fault;
26 u64 address;
27 u8 async_page_fault;
28};
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34
35struct x86_instruction_info {
36 u8 intercept;
37 u8 rep_prefix;
38 u8 modrm_mod;
39 u8 modrm_reg;
40 u8 modrm_rm;
41 u64 src_val;
42 u64 dst_val;
43 u8 src_bytes;
44 u8 dst_bytes;
45 u8 ad_bytes;
46 u64 next_rip;
47};
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79
80#define X86EMUL_CONTINUE 0
81
82#define X86EMUL_UNHANDLEABLE 1
83
84#define X86EMUL_PROPAGATE_FAULT 2
85#define X86EMUL_RETRY_INSTR 3
86#define X86EMUL_CMPXCHG_FAILED 4
87#define X86EMUL_IO_NEEDED 5
88#define X86EMUL_INTERCEPTED 6
89
90struct x86_emulate_ops {
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95
96 ulong (*read_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg);
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103 void (*write_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val);
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111
112 int (*read_std)(struct x86_emulate_ctxt *ctxt,
113 unsigned long addr, void *val,
114 unsigned int bytes,
115 struct x86_exception *fault, bool system);
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123
124 int (*read_phys)(struct x86_emulate_ctxt *ctxt, unsigned long addr,
125 void *val, unsigned int bytes);
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135 int (*write_std)(struct x86_emulate_ctxt *ctxt,
136 unsigned long addr, void *val, unsigned int bytes,
137 struct x86_exception *fault, bool system);
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144
145 int (*fetch)(struct x86_emulate_ctxt *ctxt,
146 unsigned long addr, void *val, unsigned int bytes,
147 struct x86_exception *fault);
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154
155 int (*read_emulated)(struct x86_emulate_ctxt *ctxt,
156 unsigned long addr, void *val, unsigned int bytes,
157 struct x86_exception *fault);
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166 int (*write_emulated)(struct x86_emulate_ctxt *ctxt,
167 unsigned long addr, const void *val,
168 unsigned int bytes,
169 struct x86_exception *fault);
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178
179 int (*cmpxchg_emulated)(struct x86_emulate_ctxt *ctxt,
180 unsigned long addr,
181 const void *old,
182 const void *new,
183 unsigned int bytes,
184 struct x86_exception *fault);
185 void (*invlpg)(struct x86_emulate_ctxt *ctxt, ulong addr);
186
187 int (*pio_in_emulated)(struct x86_emulate_ctxt *ctxt,
188 int size, unsigned short port, void *val,
189 unsigned int count);
190
191 int (*pio_out_emulated)(struct x86_emulate_ctxt *ctxt,
192 int size, unsigned short port, const void *val,
193 unsigned int count);
194
195 bool (*get_segment)(struct x86_emulate_ctxt *ctxt, u16 *selector,
196 struct desc_struct *desc, u32 *base3, int seg);
197 void (*set_segment)(struct x86_emulate_ctxt *ctxt, u16 selector,
198 struct desc_struct *desc, u32 base3, int seg);
199 unsigned long (*get_cached_segment_base)(struct x86_emulate_ctxt *ctxt,
200 int seg);
201 void (*get_gdt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
202 void (*get_idt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
203 void (*set_gdt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
204 void (*set_idt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
205 ulong (*get_cr)(struct x86_emulate_ctxt *ctxt, int cr);
206 int (*set_cr)(struct x86_emulate_ctxt *ctxt, int cr, ulong val);
207 int (*cpl)(struct x86_emulate_ctxt *ctxt);
208 int (*get_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong *dest);
209 int (*set_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong value);
210 u64 (*get_smbase)(struct x86_emulate_ctxt *ctxt);
211 void (*set_smbase)(struct x86_emulate_ctxt *ctxt, u64 smbase);
212 int (*set_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 data);
213 int (*get_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 *pdata);
214 int (*check_pmc)(struct x86_emulate_ctxt *ctxt, u32 pmc);
215 int (*read_pmc)(struct x86_emulate_ctxt *ctxt, u32 pmc, u64 *pdata);
216 void (*halt)(struct x86_emulate_ctxt *ctxt);
217 void (*wbinvd)(struct x86_emulate_ctxt *ctxt);
218 int (*fix_hypercall)(struct x86_emulate_ctxt *ctxt);
219 int (*intercept)(struct x86_emulate_ctxt *ctxt,
220 struct x86_instruction_info *info,
221 enum x86_intercept_stage stage);
222
223 bool (*get_cpuid)(struct x86_emulate_ctxt *ctxt, u32 *eax, u32 *ebx,
224 u32 *ecx, u32 *edx, bool exact_only);
225 bool (*guest_has_long_mode)(struct x86_emulate_ctxt *ctxt);
226 bool (*guest_has_movbe)(struct x86_emulate_ctxt *ctxt);
227 bool (*guest_has_fxsr)(struct x86_emulate_ctxt *ctxt);
228
229 void (*set_nmi_mask)(struct x86_emulate_ctxt *ctxt, bool masked);
230
231 unsigned (*get_hflags)(struct x86_emulate_ctxt *ctxt);
232 void (*set_hflags)(struct x86_emulate_ctxt *ctxt, unsigned hflags);
233 int (*pre_leave_smm)(struct x86_emulate_ctxt *ctxt,
234 const char *smstate);
235 void (*post_leave_smm)(struct x86_emulate_ctxt *ctxt);
236 int (*set_xcr)(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr);
237};
238
239typedef u32 __attribute__((vector_size(16))) sse128_t;
240
241
242struct operand {
243 enum { OP_REG, OP_MEM, OP_MEM_STR, OP_IMM, OP_XMM, OP_MM, OP_NONE } type;
244 unsigned int bytes;
245 unsigned int count;
246 union {
247 unsigned long orig_val;
248 u64 orig_val64;
249 };
250 union {
251 unsigned long *reg;
252 struct segmented_address {
253 ulong ea;
254 unsigned seg;
255 } mem;
256 unsigned xmm;
257 unsigned mm;
258 } addr;
259 union {
260 unsigned long val;
261 u64 val64;
262 char valptr[sizeof(sse128_t)];
263 sse128_t vec_val;
264 u64 mm_val;
265 void *data;
266 };
267};
268
269struct fetch_cache {
270 u8 data[15];
271 u8 *ptr;
272 u8 *end;
273};
274
275struct read_cache {
276 u8 data[1024];
277 unsigned long pos;
278 unsigned long end;
279};
280
281
282enum x86emul_mode {
283 X86EMUL_MODE_REAL,
284 X86EMUL_MODE_VM86,
285 X86EMUL_MODE_PROT16,
286 X86EMUL_MODE_PROT32,
287 X86EMUL_MODE_PROT64,
288};
289
290
291#define X86EMUL_GUEST_MASK (1 << 5)
292#define X86EMUL_SMM_MASK (1 << 6)
293#define X86EMUL_SMM_INSIDE_NMI_MASK (1 << 7)
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298
299struct fastop;
300
301typedef void (*fastop_t)(struct fastop *);
302
303struct x86_emulate_ctxt {
304 void *vcpu;
305 const struct x86_emulate_ops *ops;
306
307
308 unsigned long eflags;
309 unsigned long eip;
310
311 enum x86emul_mode mode;
312
313
314 int interruptibility;
315
316 bool perm_ok;
317 bool ud;
318 bool tf;
319
320 bool have_exception;
321 struct x86_exception exception;
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323
324 bool gpa_available;
325 gpa_t gpa_val;
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332 u8 opcode_len;
333 u8 b;
334 u8 intercept;
335 u8 op_bytes;
336 u8 ad_bytes;
337 union {
338 int (*execute)(struct x86_emulate_ctxt *ctxt);
339 fastop_t fop;
340 };
341 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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347 bool rip_relative;
348 u8 rex_prefix;
349 u8 lock_prefix;
350 u8 rep_prefix;
351
352 u32 regs_valid;
353
354 u32 regs_dirty;
355
356 u8 modrm;
357 u8 modrm_mod;
358 u8 modrm_reg;
359 u8 modrm_rm;
360 u8 modrm_seg;
361 u8 seg_override;
362 u64 d;
363 unsigned long _eip;
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365
366 struct operand src;
367 struct operand src2;
368 struct operand dst;
369 struct operand memop;
370 unsigned long _regs[NR_VCPU_REGS];
371 struct operand *memopp;
372 struct fetch_cache fetch;
373 struct read_cache io_read;
374 struct read_cache mem_read;
375};
376
377
378#define REPE_PREFIX 0xf3
379#define REPNE_PREFIX 0xf2
380
381
382#define X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx 0x68747541
383#define X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163
384#define X86EMUL_CPUID_VENDOR_AuthenticAMD_edx 0x69746e65
385
386#define X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx 0x69444d41
387#define X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx 0x21726574
388#define X86EMUL_CPUID_VENDOR_AMDisbetterI_edx 0x74656273
389
390#define X86EMUL_CPUID_VENDOR_HygonGenuine_ebx 0x6f677948
391#define X86EMUL_CPUID_VENDOR_HygonGenuine_ecx 0x656e6975
392#define X86EMUL_CPUID_VENDOR_HygonGenuine_edx 0x6e65476e
393
394#define X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 0x756e6547
395#define X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 0x6c65746e
396#define X86EMUL_CPUID_VENDOR_GenuineIntel_edx 0x49656e69
397
398#define X86EMUL_CPUID_VENDOR_CentaurHauls_ebx 0x746e6543
399#define X86EMUL_CPUID_VENDOR_CentaurHauls_ecx 0x736c7561
400#define X86EMUL_CPUID_VENDOR_CentaurHauls_edx 0x48727561
401
402static inline bool is_guest_vendor_intel(u32 ebx, u32 ecx, u32 edx)
403{
404 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
405 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
406 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
407}
408
409static inline bool is_guest_vendor_amd(u32 ebx, u32 ecx, u32 edx)
410{
411 return (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
412 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
413 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) ||
414 (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
415 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
416 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx);
417}
418
419static inline bool is_guest_vendor_hygon(u32 ebx, u32 ecx, u32 edx)
420{
421 return ebx == X86EMUL_CPUID_VENDOR_HygonGenuine_ebx &&
422 ecx == X86EMUL_CPUID_VENDOR_HygonGenuine_ecx &&
423 edx == X86EMUL_CPUID_VENDOR_HygonGenuine_edx;
424}
425
426enum x86_intercept_stage {
427 X86_ICTP_NONE = 0,
428 X86_ICPT_PRE_EXCEPT,
429 X86_ICPT_POST_EXCEPT,
430 X86_ICPT_POST_MEMACCESS,
431};
432
433enum x86_intercept {
434 x86_intercept_none,
435 x86_intercept_cr_read,
436 x86_intercept_cr_write,
437 x86_intercept_clts,
438 x86_intercept_lmsw,
439 x86_intercept_smsw,
440 x86_intercept_dr_read,
441 x86_intercept_dr_write,
442 x86_intercept_lidt,
443 x86_intercept_sidt,
444 x86_intercept_lgdt,
445 x86_intercept_sgdt,
446 x86_intercept_lldt,
447 x86_intercept_sldt,
448 x86_intercept_ltr,
449 x86_intercept_str,
450 x86_intercept_rdtsc,
451 x86_intercept_rdpmc,
452 x86_intercept_pushf,
453 x86_intercept_popf,
454 x86_intercept_cpuid,
455 x86_intercept_rsm,
456 x86_intercept_iret,
457 x86_intercept_intn,
458 x86_intercept_invd,
459 x86_intercept_pause,
460 x86_intercept_hlt,
461 x86_intercept_invlpg,
462 x86_intercept_invlpga,
463 x86_intercept_vmrun,
464 x86_intercept_vmload,
465 x86_intercept_vmsave,
466 x86_intercept_vmmcall,
467 x86_intercept_stgi,
468 x86_intercept_clgi,
469 x86_intercept_skinit,
470 x86_intercept_rdtscp,
471 x86_intercept_icebp,
472 x86_intercept_wbinvd,
473 x86_intercept_monitor,
474 x86_intercept_mwait,
475 x86_intercept_rdmsr,
476 x86_intercept_wrmsr,
477 x86_intercept_in,
478 x86_intercept_ins,
479 x86_intercept_out,
480 x86_intercept_outs,
481 x86_intercept_xsetbv,
482
483 nr_x86_intercepts
484};
485
486
487#if defined(CONFIG_X86_32)
488#define X86EMUL_MODE_HOST X86EMUL_MODE_PROT32
489#elif defined(CONFIG_X86_64)
490#define X86EMUL_MODE_HOST X86EMUL_MODE_PROT64
491#endif
492
493int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len);
494bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt);
495#define EMULATION_FAILED -1
496#define EMULATION_OK 0
497#define EMULATION_RESTART 1
498#define EMULATION_INTERCEPTED 2
499void init_decode_cache(struct x86_emulate_ctxt *ctxt);
500int x86_emulate_insn(struct x86_emulate_ctxt *ctxt);
501int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
502 u16 tss_selector, int idt_index, int reason,
503 bool has_error_code, u32 error_code);
504int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq);
505void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt);
506void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt);
507bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt);
508
509#endif
510