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15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "owl-common.h"
19#include "owl-composite.h"
20#include "owl-divider.h"
21#include "owl-factor.h"
22#include "owl-fixed-factor.h"
23#include "owl-gate.h"
24#include "owl-mux.h"
25#include "owl-pll.h"
26#include "owl-reset.h"
27
28#include <dt-bindings/clock/actions,s500-cmu.h>
29#include <dt-bindings/reset/actions,s500-reset.h>
30
31#define CMU_COREPLL (0x0000)
32#define CMU_DEVPLL (0x0004)
33#define CMU_DDRPLL (0x0008)
34#define CMU_NANDPLL (0x000C)
35#define CMU_DISPLAYPLL (0x0010)
36#define CMU_AUDIOPLL (0x0014)
37#define CMU_TVOUTPLL (0x0018)
38#define CMU_BUSCLK (0x001C)
39#define CMU_SENSORCLK (0x0020)
40#define CMU_LCDCLK (0x0024)
41#define CMU_DSICLK (0x0028)
42#define CMU_CSICLK (0x002C)
43#define CMU_DECLK (0x0030)
44#define CMU_BISPCLK (0x0034)
45#define CMU_BUSCLK1 (0x0038)
46#define CMU_VDECLK (0x0040)
47#define CMU_VCECLK (0x0044)
48#define CMU_NANDCCLK (0x004C)
49#define CMU_SD0CLK (0x0050)
50#define CMU_SD1CLK (0x0054)
51#define CMU_SD2CLK (0x0058)
52#define CMU_UART0CLK (0x005C)
53#define CMU_UART1CLK (0x0060)
54#define CMU_UART2CLK (0x0064)
55#define CMU_PWM4CLK (0x0068)
56#define CMU_PWM5CLK (0x006C)
57#define CMU_PWM0CLK (0x0070)
58#define CMU_PWM1CLK (0x0074)
59#define CMU_PWM2CLK (0x0078)
60#define CMU_PWM3CLK (0x007C)
61#define CMU_USBPLL (0x0080)
62#define CMU_ETHERNETPLL (0x0084)
63#define CMU_CVBSPLL (0x0088)
64#define CMU_LENSCLK (0x008C)
65#define CMU_GPU3DCLK (0x0090)
66#define CMU_CORECTL (0x009C)
67#define CMU_DEVCLKEN0 (0x00A0)
68#define CMU_DEVCLKEN1 (0x00A4)
69#define CMU_DEVRST0 (0x00A8)
70#define CMU_DEVRST1 (0x00AC)
71#define CMU_UART3CLK (0x00B0)
72#define CMU_UART4CLK (0x00B4)
73#define CMU_UART5CLK (0x00B8)
74#define CMU_UART6CLK (0x00BC)
75#define CMU_SSCLK (0x00C0)
76#define CMU_DIGITALDEBUG (0x00D0)
77#define CMU_ANALOGDEBUG (0x00D4)
78#define CMU_COREPLLDEBUG (0x00D8)
79#define CMU_DEVPLLDEBUG (0x00DC)
80#define CMU_DDRPLLDEBUG (0x00E0)
81#define CMU_NANDPLLDEBUG (0x00E4)
82#define CMU_DISPLAYPLLDEBUG (0x00E8)
83#define CMU_TVOUTPLLDEBUG (0x00EC)
84#define CMU_DEEPCOLORPLLDEBUG (0x00F4)
85#define CMU_AUDIOPLL_ETHPLLDEBUG (0x00F8)
86#define CMU_CVBSPLLDEBUG (0x00FC)
87
88#define OWL_S500_COREPLL_DELAY (150)
89#define OWL_S500_DDRPLL_DELAY (63)
90#define OWL_S500_DEVPLL_DELAY (28)
91#define OWL_S500_NANDPLL_DELAY (44)
92#define OWL_S500_DISPLAYPLL_DELAY (57)
93#define OWL_S500_ETHERNETPLL_DELAY (25)
94#define OWL_S500_AUDIOPLL_DELAY (100)
95
96static const struct clk_pll_table clk_audio_pll_table[] = {
97 { 0, 45158400 }, { 1, 49152000 },
98 { 0, 0 },
99};
100
101
102static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
103static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
104static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
105static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
106static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
107static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
108static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED);
109
110static const char * const dev_clk_mux_p[] = { "hosc", "dev_pll_clk" };
111static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
112static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
113static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
114static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
115static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
116static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
117static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
118static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
119static const char * const hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
120static const char * const nand_clk_mux_p[] = { "nand_pll_clk", "display_pll_clk", "dev_clk", "ddr_pll_clk" };
121
122static struct clk_factor_table sd_factor_table[] = {
123
124 { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
125 { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
126 { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
127 { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
128 { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
129 { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
130 { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
131 { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
132
133
134 { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
135 { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
136 { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
137 { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
138 { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
139 { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
140 { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
141 { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
142 { 0, 0, 0 },
143};
144
145static struct clk_factor_table bisp_factor_table[] = {
146 { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
147 { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
148 { 0, 0, 0 },
149};
150
151static struct clk_factor_table ahb_factor_table[] = {
152 { 1, 1, 2 }, { 2, 1, 3 },
153 { 0, 0, 0 },
154};
155
156static struct clk_div_table rmii_ref_div_table[] = {
157 { 0, 4 }, { 1, 10 },
158 { 0, 0 },
159};
160
161static struct clk_div_table i2s_div_table[] = {
162 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
163 { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
164 { 8, 24 },
165 { 0, 0 },
166};
167
168static struct clk_div_table nand_div_table[] = {
169 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
170 { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
171 { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
172 { 0, 0 },
173};
174
175
176static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
177static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
178
179
180static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
181static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
182static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
183static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
184static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
185static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
186static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
187static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
188
189
190static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
191static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
192static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
193
194
195static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
196static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
197static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
198
199
200static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
201 OWL_MUX_HW(CMU_VCECLK, 4, 2),
202 OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
203 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
204 0);
205
206static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
207 OWL_MUX_HW(CMU_VDECLK, 4, 2),
208 OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
209 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
210 0);
211
212static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
213 OWL_MUX_HW(CMU_BISPCLK, 4, 1),
214 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
215 OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
216 0);
217
218static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
219 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
220 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
221 OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table),
222 CLK_IGNORE_UNUSED);
223
224static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
225 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
226 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
227 OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table),
228 CLK_IGNORE_UNUSED);
229
230static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
231 OWL_MUX_HW(CMU_SD0CLK, 9, 1),
232 OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
233 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
234 0);
235
236static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
237 OWL_MUX_HW(CMU_SD1CLK, 9, 1),
238 OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
239 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
240 0);
241
242static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
243 OWL_MUX_HW(CMU_SD2CLK, 9, 1),
244 OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
245 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
246 0);
247
248static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p,
249 OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
250 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
251 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
252 0);
253
254static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p,
255 OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
256 OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
257 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
258 0);
259
260static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p,
261 OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
262 OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
263 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
264 0);
265
266static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p,
267 OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
268 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
269 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
270 0);
271
272static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p,
273 OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
274 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
275 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
276 0);
277
278static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p,
279 OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
280 OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
281 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
282 0);
283
284static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
285 OWL_MUX_HW(CMU_DECLK, 12, 1),
286 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
287 0);
288
289static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk",
290 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
291 1, 5, 0);
292
293static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk",
294 OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
295 1, 5, 0);
296
297static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk",
298 OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
299 1, 5, 0);
300
301static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
302 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
303 1, 5, 0);
304
305static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
306 OWL_MUX_HW(CMU_UART0CLK, 16, 1),
307 OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
308 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
309 CLK_IGNORE_UNUSED);
310
311static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
312 OWL_MUX_HW(CMU_UART1CLK, 16, 1),
313 OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
314 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
315 CLK_IGNORE_UNUSED);
316
317static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
318 OWL_MUX_HW(CMU_UART2CLK, 16, 1),
319 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
320 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
321 CLK_IGNORE_UNUSED);
322
323static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
324 OWL_MUX_HW(CMU_UART3CLK, 16, 1),
325 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
326 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
327 CLK_IGNORE_UNUSED);
328
329static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
330 OWL_MUX_HW(CMU_UART4CLK, 16, 1),
331 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
332 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
333 CLK_IGNORE_UNUSED);
334
335static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
336 OWL_MUX_HW(CMU_UART5CLK, 16, 1),
337 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
338 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
339 CLK_IGNORE_UNUSED);
340
341static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
342 OWL_MUX_HW(CMU_UART6CLK, 16, 1),
343 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
344 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
345 CLK_IGNORE_UNUSED);
346
347static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
348 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
349 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
350 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
351 0);
352
353static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
354 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
355 OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
356 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
357 0);
358
359static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
360 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
361 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
362 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
363 0);
364
365static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p,
366 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
367 OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
368 OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
369 0);
370
371static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p,
372 OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
373 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
374 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
375 CLK_SET_RATE_PARENT);
376
377static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p,
378 OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
379 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
380 OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),
381 CLK_SET_RATE_PARENT);
382
383static struct owl_clk_common *s500_clks[] = {
384 ðernet_pll_clk.common,
385 &core_pll_clk.common,
386 &ddr_pll_clk.common,
387 &dev_pll_clk.common,
388 &nand_pll_clk.common,
389 &audio_pll_clk.common,
390 &display_pll_clk.common,
391 &dev_clk.common,
392 &timer_clk.common,
393 &i2c0_clk.common,
394 &i2c1_clk.common,
395 &i2c2_clk.common,
396 &i2c3_clk.common,
397 &uart0_clk.common,
398 &uart1_clk.common,
399 &uart2_clk.common,
400 &uart3_clk.common,
401 &uart4_clk.common,
402 &uart5_clk.common,
403 &uart6_clk.common,
404 &pwm0_clk.common,
405 &pwm1_clk.common,
406 &pwm2_clk.common,
407 &pwm3_clk.common,
408 &pwm4_clk.common,
409 &pwm5_clk.common,
410 &sensor0_clk.common,
411 &sensor1_clk.common,
412 &sd0_clk.common,
413 &sd1_clk.common,
414 &sd2_clk.common,
415 &bisp_clk.common,
416 &ahb_clk.common,
417 &ahbprediv_clk.common,
418 &h_clk.common,
419 &spi0_clk.common,
420 &spi1_clk.common,
421 &spi2_clk.common,
422 &spi3_clk.common,
423 &rmii_ref_clk.common,
424 &de_clk.common,
425 &de1_clk.common,
426 &de2_clk.common,
427 &i2srx_clk.common,
428 &i2stx_clk.common,
429 &hdmia_clk.common,
430 &hdmi_clk.common,
431 &vce_clk.common,
432 &vde_clk.common,
433 &spdif_clk.common,
434 &nand_clk.common,
435 &ecc_clk.common,
436 &apb_clk.common,
437 &dmac_clk.common,
438 &gpio_clk.common,
439};
440
441static struct clk_hw_onecell_data s500_hw_clks = {
442 .hws = {
443 [CLK_ETHERNET_PLL] = ðernet_pll_clk.common.hw,
444 [CLK_CORE_PLL] = &core_pll_clk.common.hw,
445 [CLK_DDR_PLL] = &ddr_pll_clk.common.hw,
446 [CLK_NAND_PLL] = &nand_pll_clk.common.hw,
447 [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw,
448 [CLK_DEV_PLL] = &dev_pll_clk.common.hw,
449 [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw,
450 [CLK_TIMER] = &timer_clk.common.hw,
451 [CLK_DEV] = &dev_clk.common.hw,
452 [CLK_DE] = &de_clk.common.hw,
453 [CLK_DE1] = &de1_clk.common.hw,
454 [CLK_DE2] = &de2_clk.common.hw,
455 [CLK_I2C0] = &i2c0_clk.common.hw,
456 [CLK_I2C1] = &i2c1_clk.common.hw,
457 [CLK_I2C2] = &i2c2_clk.common.hw,
458 [CLK_I2C3] = &i2c3_clk.common.hw,
459 [CLK_I2SRX] = &i2srx_clk.common.hw,
460 [CLK_I2STX] = &i2stx_clk.common.hw,
461 [CLK_UART0] = &uart0_clk.common.hw,
462 [CLK_UART1] = &uart1_clk.common.hw,
463 [CLK_UART2] = &uart2_clk.common.hw,
464 [CLK_UART3] = &uart3_clk.common.hw,
465 [CLK_UART4] = &uart4_clk.common.hw,
466 [CLK_UART5] = &uart5_clk.common.hw,
467 [CLK_UART6] = &uart6_clk.common.hw,
468 [CLK_PWM0] = &pwm0_clk.common.hw,
469 [CLK_PWM1] = &pwm1_clk.common.hw,
470 [CLK_PWM2] = &pwm2_clk.common.hw,
471 [CLK_PWM3] = &pwm3_clk.common.hw,
472 [CLK_PWM4] = &pwm4_clk.common.hw,
473 [CLK_PWM5] = &pwm5_clk.common.hw,
474 [CLK_SENSOR0] = &sensor0_clk.common.hw,
475 [CLK_SENSOR1] = &sensor1_clk.common.hw,
476 [CLK_SD0] = &sd0_clk.common.hw,
477 [CLK_SD1] = &sd1_clk.common.hw,
478 [CLK_SD2] = &sd2_clk.common.hw,
479 [CLK_BISP] = &bisp_clk.common.hw,
480 [CLK_SPI0] = &spi0_clk.common.hw,
481 [CLK_SPI1] = &spi1_clk.common.hw,
482 [CLK_SPI2] = &spi2_clk.common.hw,
483 [CLK_SPI3] = &spi3_clk.common.hw,
484 [CLK_AHB] = &ahb_clk.common.hw,
485 [CLK_H] = &h_clk.common.hw,
486 [CLK_AHBPREDIV] = &ahbprediv_clk.common.hw,
487 [CLK_RMII_REF] = &rmii_ref_clk.common.hw,
488 [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw,
489 [CLK_HDMI] = &hdmi_clk.common.hw,
490 [CLK_VDE] = &vde_clk.common.hw,
491 [CLK_VCE] = &vce_clk.common.hw,
492 [CLK_SPDIF] = &spdif_clk.common.hw,
493 [CLK_NAND] = &nand_clk.common.hw,
494 [CLK_ECC] = &ecc_clk.common.hw,
495 [CLK_APB] = &apb_clk.common.hw,
496 [CLK_DMAC] = &dmac_clk.common.hw,
497 [CLK_GPIO] = &gpio_clk.common.hw,
498 },
499 .num = CLK_NR_CLKS,
500};
501
502static const struct owl_reset_map s500_resets[] = {
503 [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
504 [RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
505 [RESET_DDR] = { CMU_DEVRST0, BIT(2) },
506 [RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
507 [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
508 [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
509 [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
510 [RESET_DE] = { CMU_DEVRST0, BIT(7) },
511 [RESET_LCD] = { CMU_DEVRST0, BIT(8) },
512 [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
513 [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
514 [RESET_CSI] = { CMU_DEVRST0, BIT(11) },
515 [RESET_BISP] = { CMU_DEVRST0, BIT(12) },
516 [RESET_KEY] = { CMU_DEVRST0, BIT(14) },
517 [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
518 [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
519 [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
520 [RESET_VDE] = { CMU_DEVRST0, BIT(19) },
521 [RESET_VCE] = { CMU_DEVRST0, BIT(20) },
522 [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
523 [RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
524 [RESET_LENS] = { CMU_DEVRST0, BIT(26) },
525 [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
526 [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
527 [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
528 [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
529 [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
530 [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
531 [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
532 [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
533 [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
534 [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
535 [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
536 [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
537 [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
538 [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
539 [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
540 [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
541 [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
542 [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
543 [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
544 [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
545 [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
546 [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
547 [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
548 [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
549 [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
550 [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
551 [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
552 [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
553 [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
554 [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
555 [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
556 [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
557};
558
559static struct owl_clk_desc s500_clk_desc = {
560 .clks = s500_clks,
561 .num_clks = ARRAY_SIZE(s500_clks),
562
563 .hw_clks = &s500_hw_clks,
564
565 .resets = s500_resets,
566 .num_resets = ARRAY_SIZE(s500_resets),
567};
568
569static int s500_clk_probe(struct platform_device *pdev)
570{
571 struct owl_clk_desc *desc;
572 struct owl_reset *reset;
573 int ret;
574
575 desc = &s500_clk_desc;
576 owl_clk_regmap_init(pdev, desc);
577
578 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
579 if (!reset)
580 return -ENOMEM;
581
582 reset->rcdev.of_node = pdev->dev.of_node;
583 reset->rcdev.ops = &owl_reset_ops;
584 reset->rcdev.nr_resets = desc->num_resets;
585 reset->reset_map = desc->resets;
586 reset->regmap = desc->regmap;
587
588 ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
589 if (ret)
590 dev_err(&pdev->dev, "Failed to register reset controller\n");
591
592 return owl_clk_probe(&pdev->dev, desc->hw_clks);
593}
594
595static const struct of_device_id s500_clk_of_match[] = {
596 { .compatible = "actions,s500-cmu", },
597 { }
598};
599
600static struct platform_driver s500_clk_driver = {
601 .probe = s500_clk_probe,
602 .driver = {
603 .name = "s500-cmu",
604 .of_match_table = s500_clk_of_match,
605 },
606};
607
608static int __init s500_clk_init(void)
609{
610 return platform_driver_register(&s500_clk_driver);
611}
612core_initcall(s500_clk_init);
613
