1
2
3
4
5
6
7
8
9
10#include <linux/kernel.h>
11#include <linux/list.h>
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk/ti.h>
15#include <dt-bindings/clock/dra7.h>
16
17#include "clock.h"
18
19#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
20#define DRA7_DPLL_USB_DEFFREQ 960000000
21
22static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
23 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
24 { 0 },
25};
26
27static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
28 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
29 { 0 },
30};
31
32static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
33 "dpll_abe_m2x2_ck",
34 "dpll_core_h22x2_ck",
35 NULL,
36};
37
38static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
40 { 0 },
41};
42
43static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
44 { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },
45 { 0 },
46};
47
48static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
49 "per_abe_x1_gfclk2_div",
50 "video1_clk2_div",
51 "video2_clk2_div",
52 "hdmi_clk2_div",
53 NULL,
54};
55
56static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
57 "abe_24m_fclk",
58 "abe_sys_clk_div",
59 "func_24m_clk",
60 "atl_clkin3_ck",
61 "atl_clkin2_ck",
62 "atl_clkin1_ck",
63 "atl_clkin0_ck",
64 "sys_clkin2",
65 "ref_clkin0_ck",
66 "ref_clkin1_ck",
67 "ref_clkin2_ck",
68 "ref_clkin3_ck",
69 "mlb_clk",
70 "mlbp_clk",
71 NULL,
72};
73
74static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
75 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
78 { 0 },
79};
80
81static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
82 "timer_sys_clk_div",
83 "sys_32k_ck",
84 "sys_clkin2",
85 "ref_clkin0_ck",
86 "ref_clkin1_ck",
87 "ref_clkin2_ck",
88 "ref_clkin3_ck",
89 "abe_giclk_div",
90 "video1_div_clk",
91 "video2_div_clk",
92 "hdmi_div_clk",
93 "clkoutmux0_clk_mux",
94 NULL,
95};
96
97static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
99 { 0 },
100};
101
102static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
104 { 0 },
105};
106
107static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
109 { 0 },
110};
111
112static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
114 { 0 },
115};
116
117static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
118 "func_48m_fclk",
119 "dpll_per_m2x2_ck",
120 NULL,
121};
122
123static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
125 { 0 },
126};
127
128static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
129 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
130 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
131 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
132 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
133 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
134 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
135 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
136 { 0 },
137};
138
139static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
140 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
141 { 0 },
142};
143
144static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
145 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
146 { 0 },
147};
148
149static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
150 "l3_iclk_div",
151 "core_iss_main_clk",
152 NULL,
153};
154
155static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
157 { 0 },
158};
159
160static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
161 { DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
162 { DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
163 { DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
164 { 0 },
165};
166
167static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {
168 { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
169 { 0 },
170};
171
172static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
173 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
174 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
175 { 0 },
176};
177
178static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
179 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
180 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
181 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
182 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
183 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
184 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
185 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
186 { 0 },
187};
188
189static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
190 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
191 { 0 },
192};
193
194static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
195 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
196 { 0 },
197};
198
199static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
200 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
201 { 0 },
202};
203
204static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
205 "sys_32k_ck",
206 "video1_clkin_ck",
207 "video2_clkin_ck",
208 "hdmi_clkin_ck",
209 NULL,
210};
211
212static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
213 "l3_iclk_div",
214 "dpll_abe_m2_ck",
215 "atl-clkctrl:0000:24",
216 NULL,
217};
218
219static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
220 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
221 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
222 { 0 },
223};
224
225static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
226 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
227 { 0 },
228};
229
230static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
231 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
232 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
233 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
234 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
235 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
236 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
237 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
238 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
239 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
240 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
241 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
242 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
243 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
244 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
245 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
246 { 0 },
247};
248
249static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
250 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
251 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
252 { 0 },
253};
254
255static const char * const dra7_dss_dss_clk_parents[] __initconst = {
256 "dpll_per_h12x2_ck",
257 NULL,
258};
259
260static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
261 "func_48m_fclk",
262 NULL,
263};
264
265static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
266 "hdmi_dpll_clk_mux",
267 NULL,
268};
269
270static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
271 "sys_32k_ck",
272 NULL,
273};
274
275static const char * const dra7_dss_video1_clk_parents[] __initconst = {
276 "video1_dpll_clk_mux",
277 NULL,
278};
279
280static const char * const dra7_dss_video2_clk_parents[] __initconst = {
281 "video2_dpll_clk_mux",
282 NULL,
283};
284
285static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
286 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
287 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
288 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
289 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
290 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
291 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
292 { 0 },
293};
294
295static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
296 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
297 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
298 { 0 },
299};
300
301static const char * const dra7_gpu_core_mux_parents[] __initconst = {
302 "dpll_core_h14x2_ck",
303 "dpll_per_h14x2_ck",
304 "dpll_gpu_m2_ck",
305 NULL,
306};
307
308static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
309 "dpll_core_h14x2_ck",
310 "dpll_per_h14x2_ck",
311 "dpll_gpu_m2_ck",
312 NULL,
313};
314
315static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {
316 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
317 { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
318 { 0 },
319};
320
321static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {
322 { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", },
323 { 0 },
324};
325
326static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
327 "func_128m_clk",
328 "dpll_per_m2x2_ck",
329 NULL,
330};
331
332static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
333 "l3init-clkctrl:0008:24",
334 NULL,
335};
336
337static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
338 .max_div = 4,
339 .flags = CLK_DIVIDER_POWER_OF_TWO,
340};
341
342static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
343 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
344 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
345 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
346 { 0 },
347};
348
349static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
350 "l3init-clkctrl:0010:24",
351 NULL,
352};
353
354static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
355 .max_div = 4,
356 .flags = CLK_DIVIDER_POWER_OF_TWO,
357};
358
359static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
360 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
361 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
362 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
363 { 0 },
364};
365
366static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
367 "l3init_960m_gfclk",
368 NULL,
369};
370
371static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
372 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
373 { 0 },
374};
375
376static const char * const dra7_sata_ref_clk_parents[] __initconst = {
377 "sys_clkin1",
378 NULL,
379};
380
381static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
382 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
383 { 0 },
384};
385
386static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
387 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
388 { 0 },
389};
390
391static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
392 { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
393 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
394 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
395 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
396 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
397 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
398 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
399 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
400 { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
401 { 0 },
402};
403
404static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
405 "apll_pcie_ck",
406 NULL,
407};
408
409static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
410 "optfclk_pciephy_div",
411 NULL,
412};
413
414static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
415 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
416 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
417 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
418 { 0 },
419};
420
421static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
422 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
423 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
424 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
425 { 0 },
426};
427
428static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
429 { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
430 { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
431 { 0 },
432};
433
434static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
435 "dpll_gmac_h11x2_ck",
436 "rmii_clk_ck",
437 NULL,
438};
439
440static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
441 "video1_clkin_ck",
442 "video2_clkin_ck",
443 "dpll_abe_m2_ck",
444 "hdmi_clkin_ck",
445 "l3_iclk_div",
446 NULL,
447};
448
449static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
450 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
451 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
452 { 0 },
453};
454
455static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
456 { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
457 { 0 },
458};
459
460static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
461 "timer_sys_clk_div",
462 "sys_32k_ck",
463 "sys_clkin2",
464 "ref_clkin0_ck",
465 "ref_clkin1_ck",
466 "ref_clkin2_ck",
467 "ref_clkin3_ck",
468 "abe_giclk_div",
469 "video1_div_clk",
470 "video2_div_clk",
471 "hdmi_div_clk",
472 NULL,
473};
474
475static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
476 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
477 { 0 },
478};
479
480static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
481 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
482 { 0 },
483};
484
485static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
486 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
487 { 0 },
488};
489
490static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
491 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
492 { 0 },
493};
494
495static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
496 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
497 { 0 },
498};
499
500static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
501 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
502 { 0 },
503};
504
505static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
506 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
507 { 0 },
508};
509
510static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
511 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
512 { 0 },
513};
514
515static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
516 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
517 { 0 },
518};
519
520static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
521 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
522 { 0 },
523};
524
525static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
526 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
527 { 0 },
528};
529
530static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
531 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
532 { 0 },
533};
534
535static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
536 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
537 { 0 },
538};
539
540static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
541 "l4per-clkctrl:00f8:24",
542 NULL,
543};
544
545static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
546 .max_div = 4,
547 .flags = CLK_DIVIDER_POWER_OF_TWO,
548};
549
550static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
551 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
552 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
553 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
554 { 0 },
555};
556
557static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
558 "l4per-clkctrl:0100:24",
559 NULL,
560};
561
562static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
563 .max_div = 4,
564 .flags = CLK_DIVIDER_POWER_OF_TWO,
565};
566
567static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
568 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
569 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
570 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
571 { 0 },
572};
573
574static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
575 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
576 { 0 },
577};
578
579static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
580 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
581 { 0 },
582};
583
584static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
585 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
586 { 0 },
587};
588
589static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
590 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
591 { 0 },
592};
593
594static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
595 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596 { 0 },
597};
598
599static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
600 { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
601 { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
602 { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
603 { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
604 { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
605 { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
606 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
607 { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
608 { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
609 { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
610 { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
611 { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
612 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
613 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
614 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
615 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
616 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
617 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
618 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
619 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
620 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
621 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
622 { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
623 { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
624 { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
625 { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
626 { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
627 { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
628 { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
629 { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
630 { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
631 { 0 },
632};
633
634static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
635 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
636 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
637 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
638 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
639 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
640 { DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
641 { 0 },
642};
643
644static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
645 "func_128m_clk",
646 "dpll_per_h13x2_ck",
647 NULL,
648};
649
650static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
651 "l4per2-clkctrl:012c:24",
652 NULL,
653};
654
655static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
656 .max_div = 4,
657 .flags = CLK_DIVIDER_POWER_OF_TWO,
658};
659
660static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
661 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
662 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
663 { 0 },
664};
665
666static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
667 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
668 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
669 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
670 { 0 },
671};
672
673static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
674 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
675 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
676 { 0 },
677};
678
679static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
680 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
681 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
682 { 0 },
683};
684
685static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
686 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
687 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
688 { 0 },
689};
690
691static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
692 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
693 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
694 { 0 },
695};
696
697static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
698 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
699 { 0 },
700};
701
702static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
703 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
704 { 0 },
705};
706
707static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
708 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
709 { 0 },
710};
711
712static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
713 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
714 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
715 { 0 },
716};
717
718static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
719 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
720 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
721 { 0 },
722};
723
724static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
725 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
726 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
727 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
728 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
729 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
730 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
731 { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
732 { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
733 { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
734 { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
735 { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
736 { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
737 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
738 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
739 { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
740 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
741 { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
742 { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
743 { 0 },
744};
745
746static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
747 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
748 { 0 },
749};
750
751static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
752 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
753 { 0 },
754};
755
756static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
757 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
758 { 0 },
759};
760
761static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
762 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
763 { 0 },
764};
765
766static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
767 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
768 { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
769 { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
770 { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
771 { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
772 { 0 },
773};
774
775static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
776 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
777 { 0 },
778};
779
780static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
781 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
782 { 0 },
783};
784
785static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
786 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
787 { 0 },
788};
789
790static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
791 "sys_clkin1",
792 "sys_clkin2",
793 NULL,
794};
795
796static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
797 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
798 { 0 },
799};
800
801static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
802 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
803 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
804 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
805 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
806 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
807 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
808 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
809 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
810 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
811 { 0 },
812};
813
814const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
815 { 0x4a005320, dra7_mpu_clkctrl_regs },
816 { 0x4a005420, dra7_dsp1_clkctrl_regs },
817 { 0x4a005520, dra7_ipu1_clkctrl_regs },
818 { 0x4a005550, dra7_ipu_clkctrl_regs },
819 { 0x4a005620, dra7_dsp2_clkctrl_regs },
820 { 0x4a005720, dra7_rtc_clkctrl_regs },
821 { 0x4a005760, dra7_vpe_clkctrl_regs },
822 { 0x4a008620, dra7_coreaon_clkctrl_regs },
823 { 0x4a008720, dra7_l3main1_clkctrl_regs },
824 { 0x4a008920, dra7_ipu2_clkctrl_regs },
825 { 0x4a008a20, dra7_dma_clkctrl_regs },
826 { 0x4a008b20, dra7_emif_clkctrl_regs },
827 { 0x4a008c00, dra7_atl_clkctrl_regs },
828 { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
829 { 0x4a008e20, dra7_l3instr_clkctrl_regs },
830 { 0x4a009020, dra7_cam_clkctrl_regs },
831 { 0x4a009120, dra7_dss_clkctrl_regs },
832 { 0x4a009220, dra7_gpu_clkctrl_regs },
833 { 0x4a009320, dra7_l3init_clkctrl_regs },
834 { 0x4a0093b0, dra7_pcie_clkctrl_regs },
835 { 0x4a0093d0, dra7_gmac_clkctrl_regs },
836 { 0x4a009728, dra7_l4per_clkctrl_regs },
837 { 0x4a0098a0, dra7_l4sec_clkctrl_regs },
838 { 0x4a00970c, dra7_l4per2_clkctrl_regs },
839 { 0x4a009714, dra7_l4per3_clkctrl_regs },
840 { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
841 { 0 },
842};
843
844static struct ti_dt_clk dra7xx_clks[] = {
845 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
846 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
847 DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
848 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
849 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
850 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
851 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
852 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
853 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
854 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
855 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
856 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
857 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
858 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
859 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
860 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
861 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
862 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
863 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
864 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
865 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
866 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
867 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
868 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
869 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
870 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
871 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
872 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
873 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
874 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
875 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
876 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
877 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
878 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
879 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
880 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
881 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
882 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
883 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
884 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
885 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
886 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
887 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
888 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
889 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
890 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
891 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
892 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
893 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
894 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
895 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
896 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
897 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
898 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
899 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
900 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
901 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
902 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
903 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
904 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
905 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
906 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
907 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
908 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
909 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
910 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
911 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
912 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
913 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
914 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
915 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
916 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
917 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
918 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
919 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
920 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
921 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
922 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
923 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
924 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
925 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
926 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
927 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
928 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
929 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
930 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
931 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
932 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
933 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
934 { .node_name = NULL },
935};
936
937int __init dra7xx_dt_clk_init(void)
938{
939 int rc;
940 struct clk *dpll_ck, *hdcp_ck;
941
942 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
943 ti_dt_clocks_register(dra7xx_compat_clks);
944 else
945 ti_dt_clocks_register(dra7xx_clks);
946
947 omap2_clk_disable_autoidle_all();
948
949 ti_clk_add_aliases();
950
951 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
952 rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
953 if (rc)
954 pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
955
956 dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
957 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
958 if (rc)
959 pr_err("%s: failed to configure USB DPLL!\n", __func__);
960
961 dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
962 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
963 if (rc)
964 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
965
966 hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
967 rc = clk_prepare_enable(hdcp_ck);
968 if (rc)
969 pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
970
971 return rc;
972}
973
