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9#ifndef __MTK_REGS_H__
10#define __MTK_REGS_H__
11
12
13#define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
14#define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
15#define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
16#define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
17#define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
18#define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12))
19#define CDR_RING_SIZE(x) (0x18 + ((x) << 12))
20#define CDR_DESC_SIZE(x) (0x1C + ((x) << 12))
21#define CDR_CFG(x) (0x20 + ((x) << 12))
22#define CDR_DMA_CFG(x) (0x24 + ((x) << 12))
23#define CDR_THRESH(x) (0x28 + ((x) << 12))
24#define CDR_PREP_COUNT(x) (0x2C + ((x) << 12))
25#define CDR_PROC_COUNT(x) (0x30 + ((x) << 12))
26#define CDR_PREP_PNTR(x) (0x34 + ((x) << 12))
27#define CDR_PROC_PNTR(x) (0x38 + ((x) << 12))
28#define CDR_STAT(x) (0x3C + ((x) << 12))
29
30
31#define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12))
32#define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12))
33#define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12))
34#define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12))
35#define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12))
36#define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12))
37#define RDR_RING_SIZE(x) (0x818 + ((x) << 12))
38#define RDR_DESC_SIZE(x) (0x81C + ((x) << 12))
39#define RDR_CFG(x) (0x820 + ((x) << 12))
40#define RDR_DMA_CFG(x) (0x824 + ((x) << 12))
41#define RDR_THRESH(x) (0x828 + ((x) << 12))
42#define RDR_PREP_COUNT(x) (0x82C + ((x) << 12))
43#define RDR_PROC_COUNT(x) (0x830 + ((x) << 12))
44#define RDR_PREP_PNTR(x) (0x834 + ((x) << 12))
45#define RDR_PROC_PNTR(x) (0x838 + ((x) << 12))
46#define RDR_STAT(x) (0x83C + ((x) << 12))
47
48
49#define AIC_POL_CTRL(x) (0xE000 - ((x) << 12))
50#define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12))
51#define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12))
52#define AIC_RAW_STAL(x) (0xE00C - ((x) << 12))
53#define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12))
54#define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12))
55#define AIC_ACK(x) (0xE010 - ((x) << 12))
56#define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12))
57#define AIC_OPTIONS(x) (0xE018 - ((x) << 12))
58#define AIC_VERSION(x) (0xE01C - ((x) << 12))
59
60
61#define AIC_G_POL_CTRL 0xF800
62#define AIC_G_TYPE_CTRL 0xF804
63#define AIC_G_ENABLE_CTRL 0xF808
64#define AIC_G_RAW_STAT 0xF80C
65#define AIC_G_ENABLE_SET 0xF80C
66#define AIC_G_ENABLED_STAT 0xF810
67#define AIC_G_ACK 0xF810
68#define AIC_G_ENABLE_CLR 0xF814
69#define AIC_G_OPTIONS 0xF818
70#define AIC_G_VERSION 0xF81C
71
72
73#define DFE_CFG 0xF000
74#define DFE_PRIO_0 0xF010
75#define DFE_PRIO_1 0xF014
76#define DFE_PRIO_2 0xF018
77#define DFE_PRIO_3 0xF01C
78
79
80#define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3))
81#define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3))
82
83
84#define DFE_THR_CTRL 0xF200
85#define DFE_THR_STAT 0xF204
86#define DFE_THR_DESC_CTRL 0xF208
87#define DFE_THR_DESC_DPTR_LO 0xF210
88#define DFE_THR_DESC_DPTR_HI 0xF214
89#define DFE_THR_DESC_ACDPTR_LO 0xF218
90#define DFE_THR_DESC_ACDPTR_HI 0xF21C
91
92
93#define DSE_CFG 0xF400
94#define DSE_PRIO_0 0xF410
95#define DSE_PRIO_1 0xF414
96#define DSE_PRIO_2 0xF418
97#define DSE_PRIO_3 0xF41C
98
99
100#define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3))
101#define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3))
102
103
104#define DSE_THR_CTRL 0xF600
105#define DSE_THR_STAT 0xF604
106#define DSE_THR_DESC_CTRL 0xF608
107#define DSE_THR_DESC_DPTR_LO 0xF610
108#define DSE_THR_DESC_DPTR_HI 0xF614
109#define DSE_THR_DESC_S_DPTR_LO 0xF618
110#define DSE_THR_DESC_S_DPTR_HI 0xF61C
111#define DSE_THR_ERROR_STAT 0xF620
112
113
114#define HIA_MST_CTRL 0xFFF4
115#define HIA_OPTIONS 0xFFF8
116#define HIA_VERSION 0xFFFC
117
118
119#define PE_IN_DBUF_THRESH 0x10000
120#define PE_IN_TBUF_THRESH 0x10100
121
122
123#define PE_TOKEN_CTRL_STAT 0x11000
124#define PE_FUNCTION_EN 0x11004
125#define PE_CONTEXT_CTRL 0x11008
126#define PE_INTERRUPT_CTRL_STAT 0x11010
127#define PE_CONTEXT_STAT 0x1100C
128#define PE_OUT_TRANS_CTRL_STAT 0x11018
129#define PE_OUT_BUF_CTRL 0x1101C
130
131
132#define PE_PRNG_STAT 0x11040
133#define PE_PRNG_CTRL 0x11044
134#define PE_PRNG_SEED_L 0x11048
135#define PE_PRNG_SEED_H 0x1104C
136#define PE_PRNG_KEY_0_L 0x11050
137#define PE_PRNG_KEY_0_H 0x11054
138#define PE_PRNG_KEY_1_L 0x11058
139#define PE_PRNG_KEY_1_H 0x1105C
140#define PE_PRNG_RES_0 0x11060
141#define PE_PRNG_RES_1 0x11064
142#define PE_PRNG_RES_2 0x11068
143#define PE_PRNG_RES_3 0x1106C
144#define PE_PRNG_LFSR_L 0x11070
145#define PE_PRNG_LFSR_H 0x11074
146
147
148#define PE_EIP96_AIC_POL_CTRL 0x113C0
149#define PE_EIP96_AIC_TYPE_CTRL 0x113C4
150#define PE_EIP96_AIC_ENABLE_CTRL 0x113C8
151#define PE_EIP96_AIC_RAW_STAT 0x113CC
152#define PE_EIP96_AIC_ENABLE_SET 0x113CC
153#define PE_EIP96_AIC_ENABLED_STAT 0x113D0
154#define PE_EIP96_AIC_ACK 0x113D0
155#define PE_EIP96_AIC_ENABLE_CLR 0x113D4
156#define PE_EIP96_AIC_OPTIONS 0x113D8
157#define PE_EIP96_AIC_VERSION 0x113DC
158
159
160#define PE_EIP96_OPTIONS 0x113F8
161#define PE_EIP96_VERSION 0x113FC
162
163
164#define PE_OUT_DBUF_THRESH 0x11C00
165#define PE_OUT_TBUF_THRESH 0x11D00
166
167
168#define PE_AIC_POL_CTRL 0x11F00
169#define PE_AIC_TYPE_CTRL 0x11F04
170#define PE_AIC_ENABLE_CTRL 0x11F08
171#define PE_AIC_RAW_STAT 0x11F0C
172#define PE_AIC_ENABLE_SET 0x11F0C
173#define PE_AIC_ENABLED_STAT 0x11F10
174#define PE_AIC_ENABLE_CLR 0x11F14
175#define PE_AIC_OPTIONS 0x11F18
176#define PE_AIC_VERSION 0x11F1C
177
178
179#define PE_IN_FLIGHT 0x11FF0
180#define PE_OPTIONS 0x11FF8
181#define PE_VERSION 0x11FFC
182
183
184#define EIP97_CLOCK_STATE 0x1FFE4
185#define EIP97_FORCE_CLOCK_ON 0x1FFE8
186#define EIP97_FORCE_CLOCK_OFF 0x1FFEC
187#define EIP97_MST_CTRL 0x1FFF4
188#define EIP97_OPTIONS 0x1FFF8
189#define EIP97_VERSION 0x1FFFC
190#endif
191
