LXR linux/drivers/edac/Kconfig

   1#
   2#       EDAC Kconfig
   3#       Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
   4#       Licensed and distributed under the GPL
   5
   6config EDAC_ATOMIC_SCRUB
   7        bool
   8
   9config EDAC_SUPPORT
  10        bool
  11
  12menuconfig EDAC
  13        tristate "EDAC (Error Detection And Correction) reporting"
  14        depends on HAS_IOMEM && EDAC_SUPPORT && RAS
  15        help
  16          EDAC is a subsystem along with hardware-specific drivers designed to
  17          report hardware errors. These are low-level errors that are reported
  18          in the CPU or supporting chipset or other subsystems:
  19          memory errors, cache errors, PCI errors, thermal throttling, etc..
  20          If unsure, select 'Y'.
  21
  22          The mailing list for the EDAC project is linux-edac@vger.kernel.org.
  23
  24if EDAC
  25
  26config EDAC_LEGACY_SYSFS
  27        bool "EDAC legacy sysfs"
  28        default y
  29        help
  30          Enable the compatibility sysfs nodes.
  31          Use 'Y' if your edac utilities aren't ported to work with the newer
  32          structures.
  33
  34config EDAC_DEBUG
  35        bool "Debugging"
  36        select DEBUG_FS
  37        help
  38          This turns on debugging information for the entire EDAC subsystem.
  39          You do so by inserting edac_module with "edac_debug_level=x." Valid
  40          levels are 0-4 (from low to high) and by default it is set to 2.
  41          Usually you should select 'N' here.
  42
  43config EDAC_DECODE_MCE
  44        tristate "Decode MCEs in human-readable form (only on AMD for now)"
  45        depends on CPU_SUP_AMD && X86_MCE_AMD
  46        default y
  47        help
  48          Enable this option if you want to decode Machine Check Exceptions
  49          occurring on your machine in human-readable form.
  50
  51          You should definitely say Y here in case you want to decode MCEs
  52          which occur really early upon boot, before the module infrastructure
  53          has been initialized.
  54
  55config EDAC_GHES
  56        bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
  57        depends on ACPI_APEI_GHES && (EDAC=y)
  58        help
  59          Not all machines support hardware-driven error report. Some of those
  60          provide a BIOS-driven error report mechanism via ACPI, using the
  61          APEI/GHES driver. By enabling this option, the error reports provided
  62          by GHES are sent to userspace via the EDAC API.
  63
  64          When this option is enabled, it will disable the hardware-driven
  65          mechanisms, if a GHES BIOS is detected, entering into the
  66          "Firmware First" mode.
  67
  68          It should be noticed that keeping both GHES and a hardware-driven
  69          error mechanism won't work well, as BIOS will race with OS, while
  70          reading the error registers. So, if you want to not use "Firmware
  71          first" GHES error mechanism, you should disable GHES either at
  72          compilation time or by passing "ghes.disable=1" Kernel parameter
  73          at boot time.
  74
  75          In doubt, say 'Y'.
  76
  77config EDAC_AMD64
  78        tristate "AMD64 (Opteron, Athlon64)"
  79        depends on AMD_NB && EDAC_DECODE_MCE
  80        help
  81          Support for error detection and correction of DRAM ECC errors on
  82          the AMD64 families (>= K8) of memory controllers.
  83
  84config EDAC_AMD64_ERROR_INJECTION
  85        bool "Sysfs HW Error injection facilities"
  86        depends on EDAC_AMD64
  87        help
  88          Recent Opterons (Family 10h and later) provide for Memory Error
  89          Injection into the ECC detection circuits. The amd64_edac module
  90          allows the operator/user to inject Uncorrectable and Correctable
  91          errors into DRAM.
  92
  93          When enabled, in each of the respective memory controller directories
  94          (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  95
  96          - inject_section (0..3, 16-byte section of 64-byte cacheline),
  97          - inject_word (0..8, 16-bit word of 16-byte section),
  98          - inject_ecc_vector (hex ecc vector: select bits of inject word)
  99
 100          In addition, there are two control files, inject_read and inject_write,
 101          which trigger the DRAM ECC Read and Write respectively.
 102
 103config EDAC_AL_MC
 104        tristate "Amazon's Annapurna Lab Memory Controller"
 105        depends on (ARCH_ALPINE || COMPILE_TEST)
 106        help
 107          Support for error detection and correction for Amazon's Annapurna
 108          Labs Alpine chips which allow 1 bit correction and 2 bits detection.
 109
 110config EDAC_AMD76X
 111        tristate "AMD 76x (760, 762, 768)"
 112        depends on PCI && X86_32
 113        help
 114          Support for error detection and correction on the AMD 76x
 115          series of chipsets used with the Athlon processor.
 116
 117config EDAC_E7XXX
 118        tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
 119        depends on PCI && X86_32
 120        help
 121          Support for error detection and correction on the Intel
 122          E7205, E7500, E7501 and E7505 server chipsets.
 123
 124config EDAC_E752X
 125        tristate "Intel e752x (e7520, e7525, e7320) and 3100"
 126        depends on PCI && X86
 127        help
 128          Support for error detection and correction on the Intel
 129          E7520, E7525, E7320 server chipsets.
 130
 131config EDAC_I82443BXGX
 132        tristate "Intel 82443BX/GX (440BX/GX)"
 133        depends on PCI && X86_32
 134        depends on BROKEN
 135        help
 136          Support for error detection and correction on the Intel
 137          82443BX/GX memory controllers (440BX/GX chipsets).
 138
 139config EDAC_I82875P
 140        tristate "Intel 82875p (D82875P, E7210)"
 141        depends on PCI && X86_32
 142        help
 143          Support for error detection and correction on the Intel
 144          DP82785P and E7210 server chipsets.
 145
 146config EDAC_I82975X
 147        tristate "Intel 82975x (D82975x)"
 148        depends on PCI && X86
 149        help
 150          Support for error detection and correction on the Intel
 151          DP82975x server chipsets.
 152
 153config EDAC_I3000
 154        tristate "Intel 3000/3010"
 155        depends on PCI && X86
 156        help
 157          Support for error detection and correction on the Intel
 158          3000 and 3010 server chipsets.
 159
 160config EDAC_I3200
 161        tristate "Intel 3200"
 162        depends on PCI && X86
 163        help
 164          Support for error detection and correction on the Intel
 165          3200 and 3210 server chipsets.
 166
 167config EDAC_IE31200
 168        tristate "Intel e312xx"
 169        depends on PCI && X86
 170        help
 171          Support for error detection and correction on the Intel
 172          E3-1200 based DRAM controllers.
 173
 174config EDAC_X38
 175        tristate "Intel X38"
 176        depends on PCI && X86
 177        help
 178          Support for error detection and correction on the Intel
 179          X38 server chipsets.
 180
 181config EDAC_I5400
 182        tristate "Intel 5400 (Seaburg) chipsets"
 183        depends on PCI && X86
 184        help
 185          Support for error detection and correction the Intel
 186          i5400 MCH chipset (Seaburg).
 187
 188config EDAC_I7CORE
 189        tristate "Intel i7 Core (Nehalem) processors"
 190        depends on PCI && X86 && X86_MCE_INTEL
 191        help
 192          Support for error detection and correction the Intel
 193          i7 Core (Nehalem) Integrated Memory Controller that exists on
 194          newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
 195          and Xeon 55xx processors.
 196
 197config EDAC_I82860
 198        tristate "Intel 82860"
 199        depends on PCI && X86_32
 200        help
 201          Support for error detection and correction on the Intel
 202          82860 chipset.
 203
 204config EDAC_R82600
 205        tristate "Radisys 82600 embedded chipset"
 206        depends on PCI && X86_32
 207        help
 208          Support for error detection and correction on the Radisys
 209          82600 embedded chipset.
 210
 211config EDAC_I5000
 212        tristate "Intel Greencreek/Blackford chipset"
 213        depends on X86 && PCI
 214        help
 215          Support for error detection and correction the Intel
 216          Greekcreek/Blackford chipsets.
 217
 218config EDAC_I5100
 219        tristate "Intel San Clemente MCH"
 220        depends on X86 && PCI
 221        help
 222          Support for error detection and correction the Intel
 223          San Clemente MCH.
 224
 225config EDAC_I7300
 226        tristate "Intel Clarksboro MCH"
 227        depends on X86 && PCI
 228        help
 229          Support for error detection and correction the Intel
 230          Clarksboro MCH (Intel 7300 chipset).
 231
 232config EDAC_SBRIDGE
 233        tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
 234        depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
 235        help
 236          Support for error detection and correction the Intel
 237          Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
 238
 239config EDAC_SKX
 240        tristate "Intel Skylake server Integrated MC"
 241        depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
 242        depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
 243        select DMI
 244        select ACPI_ADXL
 245        help
 246          Support for error detection and correction the Intel
 247          Skylake server Integrated Memory Controllers. If your
 248          system has non-volatile DIMMs you should also manually
 249          select CONFIG_ACPI_NFIT.
 250
 251config EDAC_I10NM
 252        tristate "Intel 10nm server Integrated MC"
 253        depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
 254        depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
 255        select DMI
 256        select ACPI_ADXL
 257        help
 258          Support for error detection and correction the Intel
 259          10nm server Integrated Memory Controllers. If your
 260          system has non-volatile DIMMs you should also manually
 261          select CONFIG_ACPI_NFIT.
 262
 263config EDAC_PND2
 264        tristate "Intel Pondicherry2"
 265        depends on PCI && X86_64 && X86_MCE_INTEL
 266        help
 267          Support for error detection and correction on the Intel
 268          Pondicherry2 Integrated Memory Controller. This SoC IP is
 269          first used on the Apollo Lake platform and Denverton
 270          micro-server but may appear on others in the future.
 271
 272config EDAC_MPC85XX
 273        bool "Freescale MPC83xx / MPC85xx"
 274        depends on FSL_SOC && EDAC=y
 275        help
 276          Support for error detection and correction on the Freescale
 277          MPC8349, MPC8560, MPC8540, MPC8548, T4240
 278
 279config EDAC_LAYERSCAPE
 280        tristate "Freescale Layerscape DDR"
 281        depends on ARCH_LAYERSCAPE || SOC_LS1021A
 282        help
 283          Support for error detection and correction on Freescale memory
 284          controllers on Layerscape SoCs.
 285
 286config EDAC_MV64X60
 287        tristate "Marvell MV64x60"
 288        depends on MV64X60
 289        help
 290          Support for error detection and correction on the Marvell
 291          MV64360 and MV64460 chipsets.
 292
 293config EDAC_PASEMI
 294        tristate "PA Semi PWRficient"
 295        depends on PPC_PASEMI && PCI
 296        help
 297          Support for error detection and correction on PA Semi
 298          PWRficient.
 299
 300config EDAC_CELL
 301        tristate "Cell Broadband Engine memory controller"
 302        depends on PPC_CELL_COMMON
 303        help
 304          Support for error detection and correction on the
 305          Cell Broadband Engine internal memory controller
 306          on platform without a hypervisor
 307
 308config EDAC_PPC4XX
 309        tristate "PPC4xx IBM DDR2 Memory Controller"
 310        depends on 4xx
 311        help
 312          This enables support for EDAC on the ECC memory used
 313          with the IBM DDR2 memory controller found in various
 314          PowerPC 4xx embedded processors such as the 405EX[r],
 315          440SP, 440SPe, 460EX, 460GT and 460SX.
 316
 317config EDAC_AMD8131
 318        tristate "AMD8131 HyperTransport PCI-X Tunnel"
 319        depends on PCI && PPC_MAPLE
 320        help
 321          Support for error detection and correction on the
 322          AMD8131 HyperTransport PCI-X Tunnel chip.
 323          Note, add more Kconfig dependency if it's adopted
 324          on some machine other than Maple.
 325
 326config EDAC_AMD8111
 327        tristate "AMD8111 HyperTransport I/O Hub"
 328        depends on PCI && PPC_MAPLE
 329        help
 330          Support for error detection and correction on the
 331          AMD8111 HyperTransport I/O Hub chip.
 332          Note, add more Kconfig dependency if it's adopted
 333          on some machine other than Maple.
 334
 335config EDAC_CPC925
 336        tristate "IBM CPC925 Memory Controller (PPC970FX)"
 337        depends on PPC64
 338        help
 339          Support for error detection and correction on the
 340          IBM CPC925 Bridge and Memory Controller, which is
 341          a companion chip to the PowerPC 970 family of
 342          processors.
 343
 344config EDAC_HIGHBANK_MC
 345        tristate "Highbank Memory Controller"
 346        depends on ARCH_HIGHBANK
 347        help
 348          Support for error detection and correction on the
 349          Calxeda Highbank memory controller.
 350
 351config EDAC_HIGHBANK_L2
 352        tristate "Highbank L2 Cache"
 353        depends on ARCH_HIGHBANK
 354        help
 355          Support for error detection and correction on the
 356          Calxeda Highbank memory controller.
 357
 358config EDAC_OCTEON_PC
 359        tristate "Cavium Octeon Primary Caches"
 360        depends on CPU_CAVIUM_OCTEON
 361        help
 362          Support for error detection and correction on the primary caches of
 363          the cnMIPS cores of Cavium Octeon family SOCs.
 364
 365config EDAC_OCTEON_L2C
 366        tristate "Cavium Octeon Secondary Caches (L2C)"
 367        depends on CAVIUM_OCTEON_SOC
 368        help
 369          Support for error detection and correction on the
 370          Cavium Octeon family of SOCs.
 371
 372config EDAC_OCTEON_LMC
 373        tristate "Cavium Octeon DRAM Memory Controller (LMC)"
 374        depends on CAVIUM_OCTEON_SOC
 375        help
 376          Support for error detection and correction on the
 377          Cavium Octeon family of SOCs.
 378
 379config EDAC_OCTEON_PCI
 380        tristate "Cavium Octeon PCI Controller"
 381        depends on PCI && CAVIUM_OCTEON_SOC
 382        help
 383          Support for error detection and correction on the
 384          Cavium Octeon family of SOCs.
 385
 386config EDAC_THUNDERX
 387        tristate "Cavium ThunderX EDAC"
 388        depends on ARM64
 389        depends on PCI
 390        help
 391          Support for error detection and correction on the
 392          Cavium ThunderX memory controllers (LMC), Cache
 393          Coherent Processor Interconnect (CCPI) and L2 cache
 394          blocks (TAD, CBC, MCI).
 395
 396config EDAC_ALTERA
 397        bool "Altera SOCFPGA ECC"
 398        depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
 399        help
 400          Support for error detection and correction on the
 401          Altera SOCs. This is the global enable for the
 402          various Altera peripherals.
 403
 404config EDAC_ALTERA_SDRAM
 405        bool "Altera SDRAM ECC"
 406        depends on EDAC_ALTERA=y
 407        help
 408          Support for error detection and correction on the
 409          Altera SDRAM Memory for Altera SoCs. Note that the
 410          preloader must initialize the SDRAM before loading
 411          the kernel.
 412
 413config EDAC_ALTERA_L2C
 414        bool "Altera L2 Cache ECC"
 415        depends on EDAC_ALTERA=y && CACHE_L2X0
 416        help
 417          Support for error detection and correction on the
 418          Altera L2 cache Memory for Altera SoCs. This option
 419          requires L2 cache.
 420
 421config EDAC_ALTERA_OCRAM
 422        bool "Altera On-Chip RAM ECC"
 423        depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
 424        help
 425          Support for error detection and correction on the
 426          Altera On-Chip RAM Memory for Altera SoCs.
 427
 428config EDAC_ALTERA_ETHERNET
 429        bool "Altera Ethernet FIFO ECC"
 430        depends on EDAC_ALTERA=y
 431        help
 432          Support for error detection and correction on the
 433          Altera Ethernet FIFO Memory for Altera SoCs.
 434
 435config EDAC_ALTERA_NAND
 436        bool "Altera NAND FIFO ECC"
 437        depends on EDAC_ALTERA=y && MTD_NAND_DENALI
 438        help
 439          Support for error detection and correction on the
 440          Altera NAND FIFO Memory for Altera SoCs.
 441
 442config EDAC_ALTERA_DMA
 443        bool "Altera DMA FIFO ECC"
 444        depends on EDAC_ALTERA=y && PL330_DMA=y
 445        help
 446          Support for error detection and correction on the
 447          Altera DMA FIFO Memory for Altera SoCs.
 448
 449config EDAC_ALTERA_USB
 450        bool "Altera USB FIFO ECC"
 451        depends on EDAC_ALTERA=y && USB_DWC2
 452        help
 453          Support for error detection and correction on the
 454          Altera USB FIFO Memory for Altera SoCs.
 455
 456config EDAC_ALTERA_QSPI
 457        bool "Altera QSPI FIFO ECC"
 458        depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
 459        help
 460          Support for error detection and correction on the
 461          Altera QSPI FIFO Memory for Altera SoCs.
 462
 463config EDAC_ALTERA_SDMMC
 464        bool "Altera SDMMC FIFO ECC"
 465        depends on EDAC_ALTERA=y && MMC_DW
 466        help
 467          Support for error detection and correction on the
 468          Altera SDMMC FIFO Memory for Altera SoCs.
 469
 470config EDAC_SIFIVE
 471        bool "Sifive platform EDAC driver"
 472        depends on EDAC=y && SIFIVE_L2
 473        help
 474          Support for error detection and correction on the SiFive SoCs.
 475
 476config EDAC_ARMADA_XP
 477        bool "Marvell Armada XP DDR and L2 Cache ECC"
 478        depends on MACH_MVEBU_V7
 479        help
 480          Support for error correction and detection on the Marvell Aramada XP
 481          DDR RAM and L2 cache controllers.
 482
 483config EDAC_SYNOPSYS
 484        tristate "Synopsys DDR Memory Controller"
 485        depends on ARCH_ZYNQ || ARCH_ZYNQMP
 486        help
 487          Support for error detection and correction on the Synopsys DDR
 488          memory controller.
 489
 490config EDAC_XGENE
 491        tristate "APM X-Gene SoC"
 492        depends on (ARM64 || COMPILE_TEST)
 493        help
 494          Support for error detection and correction on the
 495          APM X-Gene family of SOCs.
 496
 497config EDAC_TI
 498        tristate "Texas Instruments DDR3 ECC Controller"
 499        depends on ARCH_KEYSTONE || SOC_DRA7XX
 500        help
 501          Support for error detection and correction on the TI SoCs.
 502
 503config EDAC_QCOM
 504        tristate "QCOM EDAC Controller"
 505        depends on ARCH_QCOM && QCOM_LLCC
 506        help
 507          Support for error detection and correction on the
 508          Qualcomm Technologies, Inc. SoCs.
 509
 510          This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
 511          As of now, it supports error reporting for Last Level Cache Controller (LLCC)
 512          of Tag RAM and Data RAM.
 513
 514          For debugging issues having to do with stability and overall system
 515          health, you should probably say 'Y' here.
 516
 517config EDAC_ASPEED
 518        tristate "Aspeed AST 2500 SoC"
 519        depends on MACH_ASPEED_G5
 520        help
 521          Support for error detection and correction on the Aspeed AST 2500 SoC.
 522
 523          First, ECC must be configured in the bootloader. Then, this driver
 524          will expose error counters via the EDAC kernel framework.
 525
 526config EDAC_BLUEFIELD
 527        tristate "Mellanox BlueField Memory ECC"
 528        depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
 529        help
 530          Support for error detection and correction on the
 531          Mellanox BlueField SoCs.
 532
 533config EDAC_DMC520
 534        tristate "ARM DMC-520 ECC"
 535        depends on ARM64
 536        help
 537          Support for error detection and correction on the
 538          SoCs with ARM DMC-520 DRAM controller.
 539
 540endif # EDAC
 541