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24#ifndef __AMDGPU_SDMA_H__
25#define __AMDGPU_SDMA_H__
26
27
28#define AMDGPU_MAX_SDMA_INSTANCES 8
29
30enum amdgpu_sdma_irq {
31 AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
32 AMDGPU_SDMA_IRQ_INSTANCE1,
33 AMDGPU_SDMA_IRQ_INSTANCE2,
34 AMDGPU_SDMA_IRQ_INSTANCE3,
35 AMDGPU_SDMA_IRQ_INSTANCE4,
36 AMDGPU_SDMA_IRQ_INSTANCE5,
37 AMDGPU_SDMA_IRQ_INSTANCE6,
38 AMDGPU_SDMA_IRQ_INSTANCE7,
39 AMDGPU_SDMA_IRQ_LAST
40};
41
42struct amdgpu_sdma_instance {
43
44 const struct firmware *fw;
45 uint32_t fw_version;
46 uint32_t feature_version;
47
48 struct amdgpu_ring ring;
49 struct amdgpu_ring page;
50 bool burst_nop;
51};
52
53struct amdgpu_sdma_ras_funcs {
54 int (*ras_late_init)(struct amdgpu_device *adev,
55 void *ras_ih_info);
56 void (*ras_fini)(struct amdgpu_device *adev);
57 int (*query_ras_error_count)(struct amdgpu_device *adev,
58 uint32_t instance, void *ras_error_status);
59 void (*reset_ras_error_count)(struct amdgpu_device *adev);
60};
61
62struct amdgpu_sdma {
63 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
64 struct amdgpu_irq_src trap_irq;
65 struct amdgpu_irq_src illegal_inst_irq;
66 struct amdgpu_irq_src ecc_irq;
67 int num_instances;
68 uint32_t srbm_soft_reset;
69 bool has_page_queue;
70 struct ras_common_if *ras_if;
71 const struct amdgpu_sdma_ras_funcs *funcs;
72};
73
74
75
76
77
78struct amdgpu_buffer_funcs {
79
80 uint32_t copy_max_bytes;
81
82
83 unsigned copy_num_dw;
84
85
86 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
87
88 uint64_t src_offset,
89
90 uint64_t dst_offset,
91
92 uint32_t byte_count,
93 bool tmz);
94
95
96 uint32_t fill_max_bytes;
97
98
99 unsigned fill_num_dw;
100
101
102 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
103
104 uint32_t src_data,
105
106 uint64_t dst_offset,
107
108 uint32_t byte_count);
109};
110
111#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
112#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
113
114struct amdgpu_sdma_instance *
115amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
116int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
117uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
118int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
119 void *ras_ih_info);
120void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
121int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
122 void *err_data,
123 struct amdgpu_iv_entry *entry);
124int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
125 struct amdgpu_irq_src *source,
126 struct amdgpu_iv_entry *entry);
127#endif
128