LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2012 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __AMDGPU_UCODE_H__
  24#define __AMDGPU_UCODE_H__
  25
  26#include "amdgpu_socbb.h"
  27
  28struct common_firmware_header {
  29        uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  30        uint32_t header_size_bytes; /* size of just the header in bytes */
  31        uint16_t header_version_major; /* header version */
  32        uint16_t header_version_minor; /* header version */
  33        uint16_t ip_version_major; /* IP version */
  34        uint16_t ip_version_minor; /* IP version */
  35        uint32_t ucode_version;
  36        uint32_t ucode_size_bytes; /* size of ucode in bytes */
  37        uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  38        uint32_t crc32;  /* crc32 checksum of the payload */
  39};
  40
  41/* version_major=1, version_minor=0 */
  42struct mc_firmware_header_v1_0 {
  43        struct common_firmware_header header;
  44        uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  45        uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  46};
  47
  48/* version_major=1, version_minor=0 */
  49struct smc_firmware_header_v1_0 {
  50        struct common_firmware_header header;
  51        uint32_t ucode_start_addr;
  52};
  53
  54/* version_major=2, version_minor=0 */
  55struct smc_firmware_header_v2_0 {
  56        struct smc_firmware_header_v1_0 v1_0;
  57        uint32_t ppt_offset_bytes; /* soft pptable offset */
  58        uint32_t ppt_size_bytes; /* soft pptable size */
  59};
  60
  61struct smc_soft_pptable_entry {
  62        uint32_t id;
  63        uint32_t ppt_offset_bytes;
  64        uint32_t ppt_size_bytes;
  65};
  66
  67/* version_major=2, version_minor=1 */
  68struct smc_firmware_header_v2_1 {
  69        struct smc_firmware_header_v1_0 v1_0;
  70        uint32_t pptable_count;
  71        uint32_t pptable_entry_offset;
  72};
  73
  74/* version_major=1, version_minor=0 */
  75struct psp_firmware_header_v1_0 {
  76        struct common_firmware_header header;
  77        uint32_t ucode_feature_version;
  78        uint32_t sos_offset_bytes;
  79        uint32_t sos_size_bytes;
  80};
  81
  82/* version_major=1, version_minor=1 */
  83struct psp_firmware_header_v1_1 {
  84        struct psp_firmware_header_v1_0 v1_0;
  85        uint32_t toc_header_version;
  86        uint32_t toc_offset_bytes;
  87        uint32_t toc_size_bytes;
  88        uint32_t kdb_header_version;
  89        uint32_t kdb_offset_bytes;
  90        uint32_t kdb_size_bytes;
  91};
  92
  93/* version_major=1, version_minor=2 */
  94struct psp_firmware_header_v1_2 {
  95        struct psp_firmware_header_v1_0 v1_0;
  96        uint32_t reserve[3];
  97        uint32_t kdb_header_version;
  98        uint32_t kdb_offset_bytes;
  99        uint32_t kdb_size_bytes;
 100};
 101
 102/* version_major=1, version_minor=3 */
 103struct psp_firmware_header_v1_3 {
 104        struct psp_firmware_header_v1_1 v1_1;
 105        uint32_t spl_header_version;
 106        uint32_t spl_offset_bytes;
 107        uint32_t spl_size_bytes;
 108};
 109
 110/* version_major=1, version_minor=0 */
 111struct ta_firmware_header_v1_0 {
 112        struct common_firmware_header header;
 113        uint32_t ta_xgmi_ucode_version;
 114        uint32_t ta_xgmi_offset_bytes;
 115        uint32_t ta_xgmi_size_bytes;
 116        uint32_t ta_ras_ucode_version;
 117        uint32_t ta_ras_offset_bytes;
 118        uint32_t ta_ras_size_bytes;
 119        uint32_t ta_hdcp_ucode_version;
 120        uint32_t ta_hdcp_offset_bytes;
 121        uint32_t ta_hdcp_size_bytes;
 122        uint32_t ta_dtm_ucode_version;
 123        uint32_t ta_dtm_offset_bytes;
 124        uint32_t ta_dtm_size_bytes;
 125};
 126
 127enum ta_fw_type {
 128        TA_FW_TYPE_UNKOWN,
 129        TA_FW_TYPE_PSP_ASD,
 130        TA_FW_TYPE_PSP_XGMI,
 131        TA_FW_TYPE_PSP_RAS,
 132        TA_FW_TYPE_PSP_HDCP,
 133        TA_FW_TYPE_PSP_DTM,
 134        TA_FW_TYPE_PSP_RAP,
 135};
 136
 137struct ta_fw_bin_desc {
 138        uint32_t fw_type;
 139        uint32_t fw_version;
 140        uint32_t offset_bytes;
 141        uint32_t size_bytes;
 142};
 143
 144/* version_major=2, version_minor=0 */
 145struct ta_firmware_header_v2_0 {
 146        struct common_firmware_header header;
 147        uint32_t ta_fw_bin_count;
 148        struct ta_fw_bin_desc ta_fw_bin[];
 149};
 150
 151/* version_major=1, version_minor=0 */
 152struct gfx_firmware_header_v1_0 {
 153        struct common_firmware_header header;
 154        uint32_t ucode_feature_version;
 155        uint32_t jt_offset; /* jt location */
 156        uint32_t jt_size;  /* size of jt */
 157};
 158
 159/* version_major=1, version_minor=0 */
 160struct mes_firmware_header_v1_0 {
 161        struct common_firmware_header header;
 162        uint32_t mes_ucode_version;
 163        uint32_t mes_ucode_size_bytes;
 164        uint32_t mes_ucode_offset_bytes;
 165        uint32_t mes_ucode_data_version;
 166        uint32_t mes_ucode_data_size_bytes;
 167        uint32_t mes_ucode_data_offset_bytes;
 168        uint32_t mes_uc_start_addr_lo;
 169        uint32_t mes_uc_start_addr_hi;
 170        uint32_t mes_data_start_addr_lo;
 171        uint32_t mes_data_start_addr_hi;
 172};
 173
 174/* version_major=1, version_minor=0 */
 175struct rlc_firmware_header_v1_0 {
 176        struct common_firmware_header header;
 177        uint32_t ucode_feature_version;
 178        uint32_t save_and_restore_offset;
 179        uint32_t clear_state_descriptor_offset;
 180        uint32_t avail_scratch_ram_locations;
 181        uint32_t master_pkt_description_offset;
 182};
 183
 184/* version_major=2, version_minor=0 */
 185struct rlc_firmware_header_v2_0 {
 186        struct common_firmware_header header;
 187        uint32_t ucode_feature_version;
 188        uint32_t jt_offset; /* jt location */
 189        uint32_t jt_size;  /* size of jt */
 190        uint32_t save_and_restore_offset;
 191        uint32_t clear_state_descriptor_offset;
 192        uint32_t avail_scratch_ram_locations;
 193        uint32_t reg_restore_list_size;
 194        uint32_t reg_list_format_start;
 195        uint32_t reg_list_format_separate_start;
 196        uint32_t starting_offsets_start;
 197        uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
 198        uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
 199        uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
 200        uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
 201        uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
 202        uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
 203        uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
 204        uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
 205};
 206
 207/* version_major=2, version_minor=1 */
 208struct rlc_firmware_header_v2_1 {
 209        struct rlc_firmware_header_v2_0 v2_0;
 210        uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
 211        uint32_t save_restore_list_cntl_ucode_ver;
 212        uint32_t save_restore_list_cntl_feature_ver;
 213        uint32_t save_restore_list_cntl_size_bytes;
 214        uint32_t save_restore_list_cntl_offset_bytes;
 215        uint32_t save_restore_list_gpm_ucode_ver;
 216        uint32_t save_restore_list_gpm_feature_ver;
 217        uint32_t save_restore_list_gpm_size_bytes;
 218        uint32_t save_restore_list_gpm_offset_bytes;
 219        uint32_t save_restore_list_srm_ucode_ver;
 220        uint32_t save_restore_list_srm_feature_ver;
 221        uint32_t save_restore_list_srm_size_bytes;
 222        uint32_t save_restore_list_srm_offset_bytes;
 223};
 224
 225/* version_major=2, version_minor=1 */
 226struct rlc_firmware_header_v2_2 {
 227        struct rlc_firmware_header_v2_1 v2_1;
 228        uint32_t rlc_iram_ucode_size_bytes;
 229        uint32_t rlc_iram_ucode_offset_bytes;
 230        uint32_t rlc_dram_ucode_size_bytes;
 231        uint32_t rlc_dram_ucode_offset_bytes;
 232};
 233
 234/* version_major=1, version_minor=0 */
 235struct sdma_firmware_header_v1_0 {
 236        struct common_firmware_header header;
 237        uint32_t ucode_feature_version;
 238        uint32_t ucode_change_version;
 239        uint32_t jt_offset; /* jt location */
 240        uint32_t jt_size; /* size of jt */
 241};
 242
 243/* version_major=1, version_minor=1 */
 244struct sdma_firmware_header_v1_1 {
 245        struct sdma_firmware_header_v1_0 v1_0;
 246        uint32_t digest_size;
 247};
 248
 249/* gpu info payload */
 250struct gpu_info_firmware_v1_0 {
 251        uint32_t gc_num_se;
 252        uint32_t gc_num_cu_per_sh;
 253        uint32_t gc_num_sh_per_se;
 254        uint32_t gc_num_rb_per_se;
 255        uint32_t gc_num_tccs;
 256        uint32_t gc_num_gprs;
 257        uint32_t gc_num_max_gs_thds;
 258        uint32_t gc_gs_table_depth;
 259        uint32_t gc_gsprim_buff_depth;
 260        uint32_t gc_parameter_cache_depth;
 261        uint32_t gc_double_offchip_lds_buffer;
 262        uint32_t gc_wave_size;
 263        uint32_t gc_max_waves_per_simd;
 264        uint32_t gc_max_scratch_slots_per_cu;
 265        uint32_t gc_lds_size;
 266};
 267
 268struct gpu_info_firmware_v1_1 {
 269        struct gpu_info_firmware_v1_0 v1_0;
 270        uint32_t num_sc_per_sh;
 271        uint32_t num_packer_per_sc;
 272};
 273
 274/* gpu info payload
 275 * version_major=1, version_minor=1 */
 276struct gpu_info_firmware_v1_2 {
 277        struct gpu_info_firmware_v1_1 v1_1;
 278        struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
 279};
 280
 281/* version_major=1, version_minor=0 */
 282struct gpu_info_firmware_header_v1_0 {
 283        struct common_firmware_header header;
 284        uint16_t version_major; /* version */
 285        uint16_t version_minor; /* version */
 286};
 287
 288/* version_major=1, version_minor=0 */
 289struct dmcu_firmware_header_v1_0 {
 290        struct common_firmware_header header;
 291        uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
 292        uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
 293};
 294
 295/* version_major=1, version_minor=0 */
 296struct dmcub_firmware_header_v1_0 {
 297        struct common_firmware_header header;
 298        uint32_t inst_const_bytes; /* size of instruction region, in bytes */
 299        uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
 300};
 301
 302/* header is fixed size */
 303union amdgpu_firmware_header {
 304        struct common_firmware_header common;
 305        struct mc_firmware_header_v1_0 mc;
 306        struct smc_firmware_header_v1_0 smc;
 307        struct smc_firmware_header_v2_0 smc_v2_0;
 308        struct psp_firmware_header_v1_0 psp;
 309        struct psp_firmware_header_v1_1 psp_v1_1;
 310        struct psp_firmware_header_v1_3 psp_v1_3;
 311        struct ta_firmware_header_v1_0 ta;
 312        struct ta_firmware_header_v2_0 ta_v2_0;
 313        struct gfx_firmware_header_v1_0 gfx;
 314        struct rlc_firmware_header_v1_0 rlc;
 315        struct rlc_firmware_header_v2_0 rlc_v2_0;
 316        struct rlc_firmware_header_v2_1 rlc_v2_1;
 317        struct sdma_firmware_header_v1_0 sdma;
 318        struct sdma_firmware_header_v1_1 sdma_v1_1;
 319        struct gpu_info_firmware_header_v1_0 gpu_info;
 320        struct dmcu_firmware_header_v1_0 dmcu;
 321        struct dmcub_firmware_header_v1_0 dmcub;
 322        uint8_t raw[0x100];
 323};
 324
 325#define UCODE_MAX_TA_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct ta_fw_bin_desc))
 326
 327/*
 328 * fw loading support
 329 */
 330enum AMDGPU_UCODE_ID {
 331        AMDGPU_UCODE_ID_SDMA0 = 0,
 332        AMDGPU_UCODE_ID_SDMA1,
 333        AMDGPU_UCODE_ID_SDMA2,
 334        AMDGPU_UCODE_ID_SDMA3,
 335        AMDGPU_UCODE_ID_SDMA4,
 336        AMDGPU_UCODE_ID_SDMA5,
 337        AMDGPU_UCODE_ID_SDMA6,
 338        AMDGPU_UCODE_ID_SDMA7,
 339        AMDGPU_UCODE_ID_CP_CE,
 340        AMDGPU_UCODE_ID_CP_PFP,
 341        AMDGPU_UCODE_ID_CP_ME,
 342        AMDGPU_UCODE_ID_CP_MEC1,
 343        AMDGPU_UCODE_ID_CP_MEC1_JT,
 344        AMDGPU_UCODE_ID_CP_MEC2,
 345        AMDGPU_UCODE_ID_CP_MEC2_JT,
 346        AMDGPU_UCODE_ID_CP_MES,
 347        AMDGPU_UCODE_ID_CP_MES_DATA,
 348        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
 349        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
 350        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
 351        AMDGPU_UCODE_ID_RLC_IRAM,
 352        AMDGPU_UCODE_ID_RLC_DRAM,
 353        AMDGPU_UCODE_ID_RLC_G,
 354        AMDGPU_UCODE_ID_STORAGE,
 355        AMDGPU_UCODE_ID_SMC,
 356        AMDGPU_UCODE_ID_UVD,
 357        AMDGPU_UCODE_ID_UVD1,
 358        AMDGPU_UCODE_ID_VCE,
 359        AMDGPU_UCODE_ID_VCN,
 360        AMDGPU_UCODE_ID_VCN1,
 361        AMDGPU_UCODE_ID_DMCU_ERAM,
 362        AMDGPU_UCODE_ID_DMCU_INTV,
 363        AMDGPU_UCODE_ID_VCN0_RAM,
 364        AMDGPU_UCODE_ID_VCN1_RAM,
 365        AMDGPU_UCODE_ID_DMCUB,
 366        AMDGPU_UCODE_ID_MAXIMUM,
 367};
 368
 369/* engine firmware status */
 370enum AMDGPU_UCODE_STATUS {
 371        AMDGPU_UCODE_STATUS_INVALID,
 372        AMDGPU_UCODE_STATUS_NOT_LOADED,
 373        AMDGPU_UCODE_STATUS_LOADED,
 374};
 375
 376enum amdgpu_firmware_load_type {
 377        AMDGPU_FW_LOAD_DIRECT = 0,
 378        AMDGPU_FW_LOAD_SMU,
 379        AMDGPU_FW_LOAD_PSP,
 380        AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
 381};
 382
 383/* conform to smu_ucode_xfer_cz.h */
 384#define AMDGPU_SDMA0_UCODE_LOADED       0x00000001
 385#define AMDGPU_SDMA1_UCODE_LOADED       0x00000002
 386#define AMDGPU_CPCE_UCODE_LOADED        0x00000004
 387#define AMDGPU_CPPFP_UCODE_LOADED       0x00000008
 388#define AMDGPU_CPME_UCODE_LOADED        0x00000010
 389#define AMDGPU_CPMEC1_UCODE_LOADED      0x00000020
 390#define AMDGPU_CPMEC2_UCODE_LOADED      0x00000040
 391#define AMDGPU_CPRLC_UCODE_LOADED       0x00000100
 392
 393/* amdgpu firmware info */
 394struct amdgpu_firmware_info {
 395        /* ucode ID */
 396        enum AMDGPU_UCODE_ID ucode_id;
 397        /* request_firmware */
 398        const struct firmware *fw;
 399        /* starting mc address */
 400        uint64_t mc_addr;
 401        /* kernel linear address */
 402        void *kaddr;
 403        /* ucode_size_bytes */
 404        uint32_t ucode_size;
 405        /* starting tmr mc address */
 406        uint32_t tmr_mc_addr_lo;
 407        uint32_t tmr_mc_addr_hi;
 408};
 409
 410struct amdgpu_firmware {
 411        struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
 412        enum amdgpu_firmware_load_type load_type;
 413        struct amdgpu_bo *fw_buf;
 414        unsigned int fw_size;
 415        unsigned int max_ucodes;
 416        /* firmwares are loaded by psp instead of smu from vega10 */
 417        const struct amdgpu_psp_funcs *funcs;
 418        struct amdgpu_bo *rbuf;
 419        struct mutex mutex;
 420
 421        /* gpu info firmware data pointer */
 422        const struct firmware *gpu_info_fw;
 423
 424        void *fw_buf_ptr;
 425        uint64_t fw_buf_mc;
 426};
 427
 428void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 429void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 430void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 431void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 432void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 433void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
 434void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
 435int amdgpu_ucode_validate(const struct firmware *fw);
 436bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 437                                uint16_t hdr_major, uint16_t hdr_minor);
 438
 439int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 440int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
 441int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
 442void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
 443void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
 444
 445enum amdgpu_firmware_load_type
 446amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
 447
 448#endif
 449