1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#ifndef __AMDGPU_VM_H__
25#define __AMDGPU_VM_H__
26
27#include <linux/idr.h>
28#include <linux/kfifo.h>
29#include <linux/rbtree.h>
30#include <drm/gpu_scheduler.h>
31#include <drm/drm_file.h>
32#include <drm/ttm/ttm_bo_driver.h>
33#include <linux/sched/mm.h>
34
35#include "amdgpu_sync.h"
36#include "amdgpu_ring.h"
37#include "amdgpu_ids.h"
38
39struct amdgpu_bo_va;
40struct amdgpu_job;
41struct amdgpu_bo_list_entry;
42
43
44
45
46
47
48#define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
49
50
51#define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
52
53#define AMDGPU_PTE_VALID (1ULL << 0)
54#define AMDGPU_PTE_SYSTEM (1ULL << 1)
55#define AMDGPU_PTE_SNOOPED (1ULL << 2)
56
57
58#define AMDGPU_PTE_TMZ (1ULL << 3)
59
60
61#define AMDGPU_PTE_EXECUTABLE (1ULL << 4)
62
63#define AMDGPU_PTE_READABLE (1ULL << 5)
64#define AMDGPU_PTE_WRITEABLE (1ULL << 6)
65
66#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
67
68
69#define AMDGPU_PTE_PRT (1ULL << 51)
70
71
72#define AMDGPU_PDE_PTE (1ULL << 54)
73
74#define AMDGPU_PTE_LOG (1ULL << 55)
75
76
77#define AMDGPU_PTE_TF (1ULL << 56)
78
79
80#define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
81
82
83
84#define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57)
85#define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL)
86
87#define AMDGPU_MTYPE_NC 0
88#define AMDGPU_MTYPE_CC 2
89
90#define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \
91 | AMDGPU_PTE_SNOOPED \
92 | AMDGPU_PTE_EXECUTABLE \
93 | AMDGPU_PTE_READABLE \
94 | AMDGPU_PTE_WRITEABLE \
95 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
96
97
98#define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48)
99#define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL)
100
101
102#define AMDGPU_VM_FAULT_STOP_NEVER 0
103#define AMDGPU_VM_FAULT_STOP_FIRST 1
104#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
105
106
107#define AMDGPU_VM_RESERVED_VRAM (4ULL << 20)
108
109
110#define AMDGPU_MAX_VMHUBS 3
111#define AMDGPU_GFXHUB_0 0
112#define AMDGPU_MMHUB_0 1
113#define AMDGPU_MMHUB_1 2
114
115
116#define AMDGPU_VA_RESERVED_SIZE (2ULL << 20)
117
118
119#define AMDGPU_VM_MAX_RESERVED_VMID 1
120
121#define AMDGPU_VM_CONTEXT_GFX 0
122#define AMDGPU_VM_CONTEXT_COMPUTE 1
123
124
125#define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
126#define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
127
128
129
130
131enum amdgpu_vm_level {
132 AMDGPU_VM_PDB2,
133 AMDGPU_VM_PDB1,
134 AMDGPU_VM_PDB0,
135 AMDGPU_VM_PTB
136};
137
138
139struct amdgpu_vm_bo_base {
140
141 struct amdgpu_vm *vm;
142 struct amdgpu_bo *bo;
143
144
145 struct amdgpu_vm_bo_base *next;
146
147
148 struct list_head vm_status;
149
150
151 bool moved;
152};
153
154struct amdgpu_vm_pt {
155 struct amdgpu_vm_bo_base base;
156
157
158 struct amdgpu_vm_pt *entries;
159};
160
161
162struct amdgpu_vm_pte_funcs {
163
164 unsigned copy_pte_num_dw;
165
166
167 void (*copy_pte)(struct amdgpu_ib *ib,
168 uint64_t pe, uint64_t src,
169 unsigned count);
170
171
172 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
173 uint64_t value, unsigned count,
174 uint32_t incr);
175
176 void (*set_pte_pde)(struct amdgpu_ib *ib,
177 uint64_t pe,
178 uint64_t addr, unsigned count,
179 uint32_t incr, uint64_t flags);
180};
181
182struct amdgpu_task_info {
183 char process_name[TASK_COMM_LEN];
184 char task_name[TASK_COMM_LEN];
185 pid_t pid;
186 pid_t tgid;
187};
188
189
190
191
192
193
194
195
196struct amdgpu_vm_update_params {
197
198
199
200
201 struct amdgpu_device *adev;
202
203
204
205
206 struct amdgpu_vm *vm;
207
208
209
210
211 bool immediate;
212
213
214
215
216 bool unlocked;
217
218
219
220
221
222
223 dma_addr_t *pages_addr;
224
225
226
227
228 struct amdgpu_job *job;
229
230
231
232
233 unsigned int num_dw_left;
234};
235
236struct amdgpu_vm_update_funcs {
237 int (*map_table)(struct amdgpu_bo *bo);
238 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
239 enum amdgpu_sync_mode sync_mode);
240 int (*update)(struct amdgpu_vm_update_params *p,
241 struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
242 unsigned count, uint32_t incr, uint64_t flags);
243 int (*commit)(struct amdgpu_vm_update_params *p,
244 struct dma_fence **fence);
245};
246
247struct amdgpu_vm {
248
249 struct rb_root_cached va;
250
251
252
253
254 struct mutex eviction_lock;
255 bool evicting;
256 unsigned int saved_flags;
257
258
259 struct list_head evicted;
260
261
262 struct list_head relocated;
263
264
265 struct list_head moved;
266
267
268 struct list_head idle;
269
270
271 struct list_head invalidated;
272 spinlock_t invalidated_lock;
273
274
275 struct list_head freed;
276
277
278 struct amdgpu_vm_pt root;
279 struct dma_fence *last_update;
280
281
282 struct drm_sched_entity immediate;
283 struct drm_sched_entity delayed;
284
285
286 struct dma_fence *last_unlocked;
287
288 unsigned int pasid;
289
290 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
291
292
293 bool use_cpu_for_update;
294
295
296 const struct amdgpu_vm_update_funcs *update_funcs;
297
298
299 bool pte_support_ats;
300
301
302 DECLARE_KFIFO(faults, u64, 128);
303
304
305 struct amdkfd_process_info *process_info;
306
307
308 struct list_head vm_list_node;
309
310
311 uint64_t pd_phys_addr;
312
313
314 struct amdgpu_task_info task_info;
315
316
317 struct ttm_lru_bulk_move lru_bulk_move;
318
319 bool bulk_moveable;
320
321 bool is_compute_context;
322};
323
324struct amdgpu_vm_manager {
325
326 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS];
327 unsigned int first_kfd_vmid;
328
329
330 u64 fence_context;
331 unsigned seqno[AMDGPU_MAX_RINGS];
332
333 uint64_t max_pfn;
334 uint32_t num_level;
335 uint32_t block_size;
336 uint32_t fragment_size;
337 enum amdgpu_vm_level root_level;
338
339 u64 vram_base_offset;
340
341 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
342 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS];
343 unsigned vm_pte_num_scheds;
344 struct amdgpu_ring *page_fault;
345
346
347 spinlock_t prt_lock;
348 atomic_t num_prt_users;
349
350
351
352
353
354 int vm_update_mode;
355
356
357
358
359 struct idr pasid_idr;
360 spinlock_t pasid_lock;
361};
362
363#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
364#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
365#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
366
367extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
368extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
369
370void amdgpu_vm_manager_init(struct amdgpu_device *adev);
371void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
372
373long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
374int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
375 int vm_context, u32 pasid);
376int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid);
377void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
378void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
379void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
380 struct list_head *validated,
381 struct amdgpu_bo_list_entry *entry);
382bool amdgpu_vm_ready(struct amdgpu_vm *vm);
383int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
384 int (*callback)(void *p, struct amdgpu_bo *bo),
385 void *param);
386int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
387int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
388 struct amdgpu_vm *vm, bool immediate);
389int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
390 struct amdgpu_vm *vm,
391 struct dma_fence **fence);
392int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
393 struct amdgpu_vm *vm);
394int amdgpu_vm_bo_update(struct amdgpu_device *adev,
395 struct amdgpu_bo_va *bo_va,
396 bool clear);
397bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
398void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
399 struct amdgpu_bo *bo, bool evicted);
400uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
401struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
402 struct amdgpu_bo *bo);
403struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
404 struct amdgpu_vm *vm,
405 struct amdgpu_bo *bo);
406int amdgpu_vm_bo_map(struct amdgpu_device *adev,
407 struct amdgpu_bo_va *bo_va,
408 uint64_t addr, uint64_t offset,
409 uint64_t size, uint64_t flags);
410int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
411 struct amdgpu_bo_va *bo_va,
412 uint64_t addr, uint64_t offset,
413 uint64_t size, uint64_t flags);
414int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
415 struct amdgpu_bo_va *bo_va,
416 uint64_t addr);
417int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
418 struct amdgpu_vm *vm,
419 uint64_t saddr, uint64_t size);
420struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
421 uint64_t addr);
422void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
423void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
424 struct amdgpu_bo_va *bo_va);
425void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
426 uint32_t fragment_size_default, unsigned max_level,
427 unsigned max_bits);
428int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
429bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
430 struct amdgpu_job *job);
431void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
432
433void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
434 struct amdgpu_task_info *task_info);
435bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
436 uint64_t addr);
437
438void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
439
440void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
441 struct amdgpu_vm *vm);
442void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
443
444#endif
445