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23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include "amdgpu.h"
29#include "amdgpu_atombios.h"
30#include "amdgpu_ih.h"
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33#include "amdgpu_ucode.h"
34#include "amdgpu_psp.h"
35#include "atom.h"
36#include "amd_pcie.h"
37
38#include "uvd/uvd_7_0_offset.h"
39#include "gc/gc_9_0_offset.h"
40#include "gc/gc_9_0_sh_mask.h"
41#include "sdma0/sdma0_4_0_offset.h"
42#include "sdma1/sdma1_4_0_offset.h"
43#include "hdp/hdp_4_0_offset.h"
44#include "hdp/hdp_4_0_sh_mask.h"
45#include "smuio/smuio_9_0_offset.h"
46#include "smuio/smuio_9_0_sh_mask.h"
47#include "nbio/nbio_7_0_default.h"
48#include "nbio/nbio_7_0_offset.h"
49#include "nbio/nbio_7_0_sh_mask.h"
50#include "nbio/nbio_7_0_smn.h"
51#include "mp/mp_9_0_offset.h"
52
53#include "soc15.h"
54#include "soc15_common.h"
55#include "gfx_v9_0.h"
56#include "gmc_v9_0.h"
57#include "gfxhub_v1_0.h"
58#include "mmhub_v1_0.h"
59#include "df_v1_7.h"
60#include "df_v3_6.h"
61#include "nbio_v6_1.h"
62#include "nbio_v7_0.h"
63#include "nbio_v7_4.h"
64#include "vega10_ih.h"
65#include "sdma_v4_0.h"
66#include "uvd_v7_0.h"
67#include "vce_v4_0.h"
68#include "vcn_v1_0.h"
69#include "vcn_v2_0.h"
70#include "jpeg_v2_0.h"
71#include "vcn_v2_5.h"
72#include "jpeg_v2_5.h"
73#include "dce_virtual.h"
74#include "mxgpu_ai.h"
75#include "amdgpu_smu.h"
76#include "amdgpu_ras.h"
77#include "amdgpu_xgmi.h"
78#include <uapi/linux/kfd_ioctl.h>
79
80#define mmMP0_MISC_CGTT_CTRL0 0x01b9
81#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
84
85
86#define mmHDP_MEM_POWER_CTRL 0x00d4
87#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
92
93
94#define mmROM_INDEX_VG20 0x00e4
95#define mmROM_INDEX_VG20_BASE_IDX 0
96#define mmROM_DATA_VG20 0x00e5
97#define mmROM_DATA_VG20_BASE_IDX 0
98
99
100
101
102static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
103{
104 unsigned long address, data;
105 address = adev->nbio.funcs->get_pcie_index_offset(adev);
106 data = adev->nbio.funcs->get_pcie_data_offset(adev);
107
108 return amdgpu_device_indirect_rreg(adev, address, data, reg);
109}
110
111static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
112{
113 unsigned long address, data;
114
115 address = adev->nbio.funcs->get_pcie_index_offset(adev);
116 data = adev->nbio.funcs->get_pcie_data_offset(adev);
117
118 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
119}
120
121static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
122{
123 unsigned long address, data;
124 address = adev->nbio.funcs->get_pcie_index_offset(adev);
125 data = adev->nbio.funcs->get_pcie_data_offset(adev);
126
127 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
128}
129
130static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
131{
132 unsigned long address, data;
133
134 address = adev->nbio.funcs->get_pcie_index_offset(adev);
135 data = adev->nbio.funcs->get_pcie_data_offset(adev);
136
137 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
138}
139
140static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
141{
142 unsigned long flags, address, data;
143 u32 r;
144
145 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
146 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
147
148 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
149 WREG32(address, ((reg) & 0x1ff));
150 r = RREG32(data);
151 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
152 return r;
153}
154
155static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
156{
157 unsigned long flags, address, data;
158
159 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
160 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
161
162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
163 WREG32(address, ((reg) & 0x1ff));
164 WREG32(data, (v));
165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
166}
167
168static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
169{
170 unsigned long flags, address, data;
171 u32 r;
172
173 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
174 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
175
176 spin_lock_irqsave(&adev->didt_idx_lock, flags);
177 WREG32(address, (reg));
178 r = RREG32(data);
179 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
180 return r;
181}
182
183static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
184{
185 unsigned long flags, address, data;
186
187 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
188 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
189
190 spin_lock_irqsave(&adev->didt_idx_lock, flags);
191 WREG32(address, (reg));
192 WREG32(data, (v));
193 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
194}
195
196static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
197{
198 unsigned long flags;
199 u32 r;
200
201 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
202 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
203 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
204 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
205 return r;
206}
207
208static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
209{
210 unsigned long flags;
211
212 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
213 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
214 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
215 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
216}
217
218static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
219{
220 unsigned long flags;
221 u32 r;
222
223 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
224 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
225 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
226 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
227 return r;
228}
229
230static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
231{
232 unsigned long flags;
233
234 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
235 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
236 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
237 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
238}
239
240static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
241{
242 return adev->nbio.funcs->get_memsize(adev);
243}
244
245static u32 soc15_get_xclk(struct amdgpu_device *adev)
246{
247 u32 reference_clock = adev->clock.spll.reference_freq;
248
249 if (adev->asic_type == CHIP_RAVEN)
250 return reference_clock / 4;
251
252 return reference_clock;
253}
254
255
256void soc15_grbm_select(struct amdgpu_device *adev,
257 u32 me, u32 pipe, u32 queue, u32 vmid)
258{
259 u32 grbm_gfx_cntl = 0;
260 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
261 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
262 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
263 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
264
265 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
266}
267
268static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
269{
270
271}
272
273static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
274{
275
276 return false;
277}
278
279static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
280 u8 *bios, u32 length_bytes)
281{
282 u32 *dw_ptr;
283 u32 i, length_dw;
284 uint32_t rom_index_offset;
285 uint32_t rom_data_offset;
286
287 if (bios == NULL)
288 return false;
289 if (length_bytes == 0)
290 return false;
291
292 if (adev->flags & AMD_IS_APU)
293 return false;
294
295 dw_ptr = (u32 *)bios;
296 length_dw = ALIGN(length_bytes, 4) / 4;
297
298 switch (adev->asic_type) {
299 case CHIP_VEGA20:
300 case CHIP_ARCTURUS:
301 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
302 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
303 break;
304 default:
305 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
306 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
307 break;
308 }
309
310
311 WREG32(rom_index_offset, 0);
312
313 for (i = 0; i < length_dw; i++)
314 dw_ptr[i] = RREG32(rom_data_offset);
315
316 return true;
317}
318
319static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
320 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
321 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
322 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
323 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
324 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
325 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
326 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
327 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
328 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
329 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
330 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
331 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
332 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
333 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
334 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
335 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
336 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
337 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
338 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
339 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
340};
341
342static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
343 u32 sh_num, u32 reg_offset)
344{
345 uint32_t val;
346
347 mutex_lock(&adev->grbm_idx_mutex);
348 if (se_num != 0xffffffff || sh_num != 0xffffffff)
349 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
350
351 val = RREG32(reg_offset);
352
353 if (se_num != 0xffffffff || sh_num != 0xffffffff)
354 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
355 mutex_unlock(&adev->grbm_idx_mutex);
356 return val;
357}
358
359static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
360 bool indexed, u32 se_num,
361 u32 sh_num, u32 reg_offset)
362{
363 if (indexed) {
364 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
365 } else {
366 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
367 return adev->gfx.config.gb_addr_config;
368 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
369 return adev->gfx.config.db_debug2;
370 return RREG32(reg_offset);
371 }
372}
373
374static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
375 u32 sh_num, u32 reg_offset, u32 *value)
376{
377 uint32_t i;
378 struct soc15_allowed_register_entry *en;
379
380 *value = 0;
381 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
382 en = &soc15_allowed_read_registers[i];
383 if (adev->reg_offset[en->hwip][en->inst] &&
384 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
385 + en->reg_offset))
386 continue;
387
388 *value = soc15_get_register_value(adev,
389 soc15_allowed_read_registers[i].grbm_indexed,
390 se_num, sh_num, reg_offset);
391 return 0;
392 }
393 return -EINVAL;
394}
395
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399
400
401
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403
404
405
406
407
408void soc15_program_register_sequence(struct amdgpu_device *adev,
409 const struct soc15_reg_golden *regs,
410 const u32 array_size)
411{
412 const struct soc15_reg_golden *entry;
413 u32 tmp, reg;
414 int i;
415
416 for (i = 0; i < array_size; ++i) {
417 entry = ®s[i];
418 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
419
420 if (entry->and_mask == 0xffffffff) {
421 tmp = entry->or_mask;
422 } else {
423 tmp = RREG32(reg);
424 tmp &= ~(entry->and_mask);
425 tmp |= (entry->or_mask & entry->and_mask);
426 }
427
428 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
429 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
430 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
431 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
432 WREG32_RLC(reg, tmp);
433 else
434 WREG32(reg, tmp);
435
436 }
437
438}
439
440static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
441{
442 u32 i;
443 int ret = 0;
444
445 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
446
447 dev_info(adev->dev, "GPU mode1 reset\n");
448
449
450 pci_clear_master(adev->pdev);
451
452 amdgpu_device_cache_pci_state(adev->pdev);
453
454 ret = psp_gpu_reset(adev);
455 if (ret)
456 dev_err(adev->dev, "GPU mode1 reset failed\n");
457
458 amdgpu_device_load_pci_state(adev->pdev);
459
460
461 for (i = 0; i < adev->usec_timeout; i++) {
462 u32 memsize = adev->nbio.funcs->get_memsize(adev);
463
464 if (memsize != 0xffffffff)
465 break;
466 udelay(1);
467 }
468
469 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
470
471 return ret;
472}
473
474static int soc15_asic_baco_reset(struct amdgpu_device *adev)
475{
476 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
477 int ret = 0;
478
479
480 if (ras && ras->supported)
481 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
482
483 ret = amdgpu_dpm_baco_reset(adev);
484 if (ret)
485 return ret;
486
487
488 if (ras && ras->supported)
489 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
490
491 return 0;
492}
493
494static enum amd_reset_method
495soc15_asic_reset_method(struct amdgpu_device *adev)
496{
497 bool baco_reset = false;
498 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
499
500 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
501 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
502 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
503 return amdgpu_reset_method;
504
505 if (amdgpu_reset_method != -1)
506 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
507 amdgpu_reset_method);
508
509 switch (adev->asic_type) {
510 case CHIP_RAVEN:
511 case CHIP_RENOIR:
512 return AMD_RESET_METHOD_MODE2;
513 case CHIP_VEGA10:
514 case CHIP_VEGA12:
515 case CHIP_ARCTURUS:
516 baco_reset = amdgpu_dpm_is_baco_supported(adev);
517 break;
518 case CHIP_VEGA20:
519 if (adev->psp.sos_fw_version >= 0x80067)
520 baco_reset = amdgpu_dpm_is_baco_supported(adev);
521
522
523
524
525
526 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
527 baco_reset = false;
528 break;
529 default:
530 break;
531 }
532
533 if (baco_reset)
534 return AMD_RESET_METHOD_BACO;
535 else
536 return AMD_RESET_METHOD_MODE1;
537}
538
539static int soc15_asic_reset(struct amdgpu_device *adev)
540{
541
542 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
543 !(adev->apu_flags & AMD_APU_IS_RAVEN2))
544 return 0;
545
546 switch (soc15_asic_reset_method(adev)) {
547 case AMD_RESET_METHOD_BACO:
548 dev_info(adev->dev, "BACO reset\n");
549 return soc15_asic_baco_reset(adev);
550 case AMD_RESET_METHOD_MODE2:
551 dev_info(adev->dev, "MODE2 reset\n");
552 return amdgpu_dpm_mode2_reset(adev);
553 default:
554 dev_info(adev->dev, "MODE1 reset\n");
555 return soc15_asic_mode1_reset(adev);
556 }
557}
558
559static bool soc15_supports_baco(struct amdgpu_device *adev)
560{
561 switch (adev->asic_type) {
562 case CHIP_VEGA10:
563 case CHIP_VEGA12:
564 case CHIP_ARCTURUS:
565 return amdgpu_dpm_is_baco_supported(adev);
566 case CHIP_VEGA20:
567 if (adev->psp.sos_fw_version >= 0x80067)
568 return amdgpu_dpm_is_baco_supported(adev);
569 return false;
570 default:
571 return false;
572 }
573}
574
575
576
577
578
579
580
581static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
582{
583
584
585
586
587
588
589
590
591 return 0;
592}
593
594static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
595{
596
597
598 return 0;
599}
600
601static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
602{
603 if (pci_is_root_bus(adev->pdev->bus))
604 return;
605
606 if (amdgpu_pcie_gen2 == 0)
607 return;
608
609 if (adev->flags & AMD_IS_APU)
610 return;
611
612 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
613 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
614 return;
615
616
617}
618
619static void soc15_program_aspm(struct amdgpu_device *adev)
620{
621
622 if (amdgpu_aspm == 0)
623 return;
624
625
626}
627
628static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
629 bool enable)
630{
631 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
632 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
633}
634
635static const struct amdgpu_ip_block_version vega10_common_ip_block =
636{
637 .type = AMD_IP_BLOCK_TYPE_COMMON,
638 .major = 2,
639 .minor = 0,
640 .rev = 0,
641 .funcs = &soc15_common_ip_funcs,
642};
643
644static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
645{
646 return adev->nbio.funcs->get_rev_id(adev);
647}
648
649static void soc15_reg_base_init(struct amdgpu_device *adev)
650{
651 int r;
652
653
654 switch (adev->asic_type) {
655 case CHIP_VEGA10:
656 case CHIP_VEGA12:
657 case CHIP_RAVEN:
658 vega10_reg_base_init(adev);
659 break;
660 case CHIP_RENOIR:
661
662
663 if (amdgpu_discovery) {
664 r = amdgpu_discovery_reg_base_init(adev);
665 if (r == 0)
666 break;
667 DRM_WARN("failed to init reg base from ip discovery table, "
668 "fallback to legacy init method\n");
669 }
670 vega10_reg_base_init(adev);
671 break;
672 case CHIP_VEGA20:
673 vega20_reg_base_init(adev);
674 break;
675 case CHIP_ARCTURUS:
676 arct_reg_base_init(adev);
677 break;
678 default:
679 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
680 break;
681 }
682}
683
684void soc15_set_virt_ops(struct amdgpu_device *adev)
685{
686 adev->virt.ops = &xgpu_ai_virt_ops;
687
688
689
690
691 soc15_reg_base_init(adev);
692}
693
694int soc15_set_ip_blocks(struct amdgpu_device *adev)
695{
696
697 if (!amdgpu_sriov_vf(adev))
698 soc15_reg_base_init(adev);
699
700 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
701 adev->gmc.xgmi.supported = true;
702
703 if (adev->flags & AMD_IS_APU) {
704 adev->nbio.funcs = &nbio_v7_0_funcs;
705 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
706 } else if (adev->asic_type == CHIP_VEGA20 ||
707 adev->asic_type == CHIP_ARCTURUS) {
708 adev->nbio.funcs = &nbio_v7_4_funcs;
709 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
710 } else {
711 adev->nbio.funcs = &nbio_v6_1_funcs;
712 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
713 }
714
715 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
716 adev->df.funcs = &df_v3_6_funcs;
717 else
718 adev->df.funcs = &df_v1_7_funcs;
719
720 adev->rev_id = soc15_get_rev_id(adev);
721
722 switch (adev->asic_type) {
723 case CHIP_VEGA10:
724 case CHIP_VEGA12:
725 case CHIP_VEGA20:
726 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
727 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
728
729
730 if (amdgpu_sriov_vf(adev)) {
731 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
732 if (adev->asic_type == CHIP_VEGA20)
733 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
734 else
735 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
736 }
737 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
738 } else {
739 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
740 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
741 if (adev->asic_type == CHIP_VEGA20)
742 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
743 else
744 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
745 }
746 }
747 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
748 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
749 if (is_support_sw_smu(adev)) {
750 if (!amdgpu_sriov_vf(adev))
751 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
752 } else {
753 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
754 }
755 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
756 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
757#if defined(CONFIG_DRM_AMD_DC)
758 else if (amdgpu_device_has_dc_support(adev))
759 amdgpu_device_ip_block_add(adev, &dm_ip_block);
760#endif
761 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
762 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
763 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
764 }
765 break;
766 case CHIP_RAVEN:
767 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
768 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
769 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
770 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
771 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
772 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
773 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
774 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
775 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
776 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
777#if defined(CONFIG_DRM_AMD_DC)
778 else if (amdgpu_device_has_dc_support(adev))
779 amdgpu_device_ip_block_add(adev, &dm_ip_block);
780#endif
781 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
782 break;
783 case CHIP_ARCTURUS:
784 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
785 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
786
787 if (amdgpu_sriov_vf(adev)) {
788 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
789 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
790 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
791 } else {
792 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
793 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
794 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
795 }
796
797 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
798 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
799 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
800 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
801 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
802
803 if (amdgpu_sriov_vf(adev)) {
804 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
805 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
806 } else {
807 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
808 }
809 if (!amdgpu_sriov_vf(adev))
810 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
811 break;
812 case CHIP_RENOIR:
813 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
814 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
815 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
816 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
817 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
818 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
819 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
820 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
821 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
822 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
823#if defined(CONFIG_DRM_AMD_DC)
824 else if (amdgpu_device_has_dc_support(adev))
825 amdgpu_device_ip_block_add(adev, &dm_ip_block);
826#endif
827 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
828 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 return 0;
835}
836
837static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
838{
839 adev->nbio.funcs->hdp_flush(adev, ring);
840}
841
842static void soc15_invalidate_hdp(struct amdgpu_device *adev,
843 struct amdgpu_ring *ring)
844{
845 if (!ring || !ring->funcs->emit_wreg)
846 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
847 else
848 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
849 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
850}
851
852static bool soc15_need_full_reset(struct amdgpu_device *adev)
853{
854
855 return true;
856}
857
858static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
859{
860 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
861 return;
862
863 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
864}
865
866static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
867 uint64_t *count1)
868{
869 uint32_t perfctr = 0;
870 uint64_t cnt0_of, cnt1_of;
871 int tmp;
872
873
874
875
876 if (adev->flags & AMD_IS_APU)
877 return;
878
879
880
881
882 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
883 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
884
885
886 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
887
888
889
890
891
892 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
893
894 msleep(1000);
895
896
897
898
899
900
901 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
902
903
904 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
905 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
906 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
907
908
909 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
910 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
911}
912
913static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
914 uint64_t *count1)
915{
916 uint32_t perfctr = 0;
917 uint64_t cnt0_of, cnt1_of;
918 int tmp;
919
920
921
922
923 if (adev->flags & AMD_IS_APU)
924 return;
925
926
927
928
929 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
930 EVENT0_SEL, 40);
931 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
932 EVENT1_SEL, 108);
933
934
935 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
936
937
938
939
940
941 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
942
943 msleep(1000);
944
945
946
947
948
949
950 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
951
952
953 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
954 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
955 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
956
957
958 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
959 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
960}
961
962static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
963{
964 u32 sol_reg;
965
966
967
968
969 if (!amdgpu_passthrough(adev))
970 return false;
971
972 if (adev->flags & AMD_IS_APU)
973 return false;
974
975
976
977
978 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
979 if (sol_reg)
980 return true;
981
982 return false;
983}
984
985static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
986{
987 uint64_t nak_r, nak_g;
988
989
990 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
991 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
992
993
994 return (nak_r + nak_g);
995}
996
997static void soc15_pre_asic_init(struct amdgpu_device *adev)
998{
999 gmc_v9_0_restore_registers(adev);
1000}
1001
1002static const struct amdgpu_asic_funcs soc15_asic_funcs =
1003{
1004 .read_disabled_bios = &soc15_read_disabled_bios,
1005 .read_bios_from_rom = &soc15_read_bios_from_rom,
1006 .read_register = &soc15_read_register,
1007 .reset = &soc15_asic_reset,
1008 .reset_method = &soc15_asic_reset_method,
1009 .set_vga_state = &soc15_vga_set_state,
1010 .get_xclk = &soc15_get_xclk,
1011 .set_uvd_clocks = &soc15_set_uvd_clocks,
1012 .set_vce_clocks = &soc15_set_vce_clocks,
1013 .get_config_memsize = &soc15_get_config_memsize,
1014 .flush_hdp = &soc15_flush_hdp,
1015 .invalidate_hdp = &soc15_invalidate_hdp,
1016 .need_full_reset = &soc15_need_full_reset,
1017 .init_doorbell_index = &vega10_doorbell_index_init,
1018 .get_pcie_usage = &soc15_get_pcie_usage,
1019 .need_reset_on_init = &soc15_need_reset_on_init,
1020 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1021 .supports_baco = &soc15_supports_baco,
1022 .pre_asic_init = &soc15_pre_asic_init,
1023};
1024
1025static const struct amdgpu_asic_funcs vega20_asic_funcs =
1026{
1027 .read_disabled_bios = &soc15_read_disabled_bios,
1028 .read_bios_from_rom = &soc15_read_bios_from_rom,
1029 .read_register = &soc15_read_register,
1030 .reset = &soc15_asic_reset,
1031 .reset_method = &soc15_asic_reset_method,
1032 .set_vga_state = &soc15_vga_set_state,
1033 .get_xclk = &soc15_get_xclk,
1034 .set_uvd_clocks = &soc15_set_uvd_clocks,
1035 .set_vce_clocks = &soc15_set_vce_clocks,
1036 .get_config_memsize = &soc15_get_config_memsize,
1037 .flush_hdp = &soc15_flush_hdp,
1038 .invalidate_hdp = &soc15_invalidate_hdp,
1039 .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
1040 .need_full_reset = &soc15_need_full_reset,
1041 .init_doorbell_index = &vega20_doorbell_index_init,
1042 .get_pcie_usage = &vega20_get_pcie_usage,
1043 .need_reset_on_init = &soc15_need_reset_on_init,
1044 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1045 .supports_baco = &soc15_supports_baco,
1046 .pre_asic_init = &soc15_pre_asic_init,
1047};
1048
1049static int soc15_common_early_init(void *handle)
1050{
1051#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053
1054 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1055 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1056 adev->smc_rreg = NULL;
1057 adev->smc_wreg = NULL;
1058 adev->pcie_rreg = &soc15_pcie_rreg;
1059 adev->pcie_wreg = &soc15_pcie_wreg;
1060 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1061 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1062 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1063 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1064 adev->didt_rreg = &soc15_didt_rreg;
1065 adev->didt_wreg = &soc15_didt_wreg;
1066 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1067 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1068 adev->se_cac_rreg = &soc15_se_cac_rreg;
1069 adev->se_cac_wreg = &soc15_se_cac_wreg;
1070
1071
1072 adev->external_rev_id = 0xFF;
1073 switch (adev->asic_type) {
1074 case CHIP_VEGA10:
1075 adev->asic_funcs = &soc15_asic_funcs;
1076 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1077 AMD_CG_SUPPORT_GFX_MGLS |
1078 AMD_CG_SUPPORT_GFX_RLC_LS |
1079 AMD_CG_SUPPORT_GFX_CP_LS |
1080 AMD_CG_SUPPORT_GFX_3D_CGCG |
1081 AMD_CG_SUPPORT_GFX_3D_CGLS |
1082 AMD_CG_SUPPORT_GFX_CGCG |
1083 AMD_CG_SUPPORT_GFX_CGLS |
1084 AMD_CG_SUPPORT_BIF_MGCG |
1085 AMD_CG_SUPPORT_BIF_LS |
1086 AMD_CG_SUPPORT_HDP_LS |
1087 AMD_CG_SUPPORT_DRM_MGCG |
1088 AMD_CG_SUPPORT_DRM_LS |
1089 AMD_CG_SUPPORT_ROM_MGCG |
1090 AMD_CG_SUPPORT_DF_MGCG |
1091 AMD_CG_SUPPORT_SDMA_MGCG |
1092 AMD_CG_SUPPORT_SDMA_LS |
1093 AMD_CG_SUPPORT_MC_MGCG |
1094 AMD_CG_SUPPORT_MC_LS;
1095 adev->pg_flags = 0;
1096 adev->external_rev_id = 0x1;
1097 break;
1098 case CHIP_VEGA12:
1099 adev->asic_funcs = &soc15_asic_funcs;
1100 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1101 AMD_CG_SUPPORT_GFX_MGLS |
1102 AMD_CG_SUPPORT_GFX_CGCG |
1103 AMD_CG_SUPPORT_GFX_CGLS |
1104 AMD_CG_SUPPORT_GFX_3D_CGCG |
1105 AMD_CG_SUPPORT_GFX_3D_CGLS |
1106 AMD_CG_SUPPORT_GFX_CP_LS |
1107 AMD_CG_SUPPORT_MC_LS |
1108 AMD_CG_SUPPORT_MC_MGCG |
1109 AMD_CG_SUPPORT_SDMA_MGCG |
1110 AMD_CG_SUPPORT_SDMA_LS |
1111 AMD_CG_SUPPORT_BIF_MGCG |
1112 AMD_CG_SUPPORT_BIF_LS |
1113 AMD_CG_SUPPORT_HDP_MGCG |
1114 AMD_CG_SUPPORT_HDP_LS |
1115 AMD_CG_SUPPORT_ROM_MGCG |
1116 AMD_CG_SUPPORT_VCE_MGCG |
1117 AMD_CG_SUPPORT_UVD_MGCG;
1118 adev->pg_flags = 0;
1119 adev->external_rev_id = adev->rev_id + 0x14;
1120 break;
1121 case CHIP_VEGA20:
1122 adev->asic_funcs = &vega20_asic_funcs;
1123 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1124 AMD_CG_SUPPORT_GFX_MGLS |
1125 AMD_CG_SUPPORT_GFX_CGCG |
1126 AMD_CG_SUPPORT_GFX_CGLS |
1127 AMD_CG_SUPPORT_GFX_3D_CGCG |
1128 AMD_CG_SUPPORT_GFX_3D_CGLS |
1129 AMD_CG_SUPPORT_GFX_CP_LS |
1130 AMD_CG_SUPPORT_MC_LS |
1131 AMD_CG_SUPPORT_MC_MGCG |
1132 AMD_CG_SUPPORT_SDMA_MGCG |
1133 AMD_CG_SUPPORT_SDMA_LS |
1134 AMD_CG_SUPPORT_BIF_MGCG |
1135 AMD_CG_SUPPORT_BIF_LS |
1136 AMD_CG_SUPPORT_HDP_MGCG |
1137 AMD_CG_SUPPORT_HDP_LS |
1138 AMD_CG_SUPPORT_ROM_MGCG |
1139 AMD_CG_SUPPORT_VCE_MGCG |
1140 AMD_CG_SUPPORT_UVD_MGCG;
1141 adev->pg_flags = 0;
1142 adev->external_rev_id = adev->rev_id + 0x28;
1143 break;
1144 case CHIP_RAVEN:
1145 adev->asic_funcs = &soc15_asic_funcs;
1146 if (adev->pdev->device == 0x15dd)
1147 adev->apu_flags |= AMD_APU_IS_RAVEN;
1148 if (adev->pdev->device == 0x15d8)
1149 adev->apu_flags |= AMD_APU_IS_PICASSO;
1150 if (adev->rev_id >= 0x8)
1151 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1152
1153 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1154 adev->external_rev_id = adev->rev_id + 0x79;
1155 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1156 adev->external_rev_id = adev->rev_id + 0x41;
1157 else if (adev->rev_id == 1)
1158 adev->external_rev_id = adev->rev_id + 0x20;
1159 else
1160 adev->external_rev_id = adev->rev_id + 0x01;
1161
1162 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1163 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1164 AMD_CG_SUPPORT_GFX_MGLS |
1165 AMD_CG_SUPPORT_GFX_CP_LS |
1166 AMD_CG_SUPPORT_GFX_3D_CGCG |
1167 AMD_CG_SUPPORT_GFX_3D_CGLS |
1168 AMD_CG_SUPPORT_GFX_CGCG |
1169 AMD_CG_SUPPORT_GFX_CGLS |
1170 AMD_CG_SUPPORT_BIF_LS |
1171 AMD_CG_SUPPORT_HDP_LS |
1172 AMD_CG_SUPPORT_ROM_MGCG |
1173 AMD_CG_SUPPORT_MC_MGCG |
1174 AMD_CG_SUPPORT_MC_LS |
1175 AMD_CG_SUPPORT_SDMA_MGCG |
1176 AMD_CG_SUPPORT_SDMA_LS |
1177 AMD_CG_SUPPORT_VCN_MGCG;
1178
1179 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1180 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1181 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1182 AMD_CG_SUPPORT_GFX_MGLS |
1183 AMD_CG_SUPPORT_GFX_CP_LS |
1184 AMD_CG_SUPPORT_GFX_3D_CGCG |
1185 AMD_CG_SUPPORT_GFX_3D_CGLS |
1186 AMD_CG_SUPPORT_GFX_CGCG |
1187 AMD_CG_SUPPORT_GFX_CGLS |
1188 AMD_CG_SUPPORT_BIF_LS |
1189 AMD_CG_SUPPORT_HDP_LS |
1190 AMD_CG_SUPPORT_ROM_MGCG |
1191 AMD_CG_SUPPORT_MC_MGCG |
1192 AMD_CG_SUPPORT_MC_LS |
1193 AMD_CG_SUPPORT_SDMA_MGCG |
1194 AMD_CG_SUPPORT_SDMA_LS;
1195
1196 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1197 AMD_PG_SUPPORT_MMHUB |
1198 AMD_PG_SUPPORT_VCN;
1199 } else {
1200 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1201 AMD_CG_SUPPORT_GFX_MGLS |
1202 AMD_CG_SUPPORT_GFX_RLC_LS |
1203 AMD_CG_SUPPORT_GFX_CP_LS |
1204 AMD_CG_SUPPORT_GFX_3D_CGCG |
1205 AMD_CG_SUPPORT_GFX_3D_CGLS |
1206 AMD_CG_SUPPORT_GFX_CGCG |
1207 AMD_CG_SUPPORT_GFX_CGLS |
1208 AMD_CG_SUPPORT_BIF_MGCG |
1209 AMD_CG_SUPPORT_BIF_LS |
1210 AMD_CG_SUPPORT_HDP_MGCG |
1211 AMD_CG_SUPPORT_HDP_LS |
1212 AMD_CG_SUPPORT_DRM_MGCG |
1213 AMD_CG_SUPPORT_DRM_LS |
1214 AMD_CG_SUPPORT_ROM_MGCG |
1215 AMD_CG_SUPPORT_MC_MGCG |
1216 AMD_CG_SUPPORT_MC_LS |
1217 AMD_CG_SUPPORT_SDMA_MGCG |
1218 AMD_CG_SUPPORT_SDMA_LS |
1219 AMD_CG_SUPPORT_VCN_MGCG;
1220
1221 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1222 }
1223 break;
1224 case CHIP_ARCTURUS:
1225 adev->asic_funcs = &vega20_asic_funcs;
1226 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1227 AMD_CG_SUPPORT_GFX_MGLS |
1228 AMD_CG_SUPPORT_GFX_CGCG |
1229 AMD_CG_SUPPORT_GFX_CGLS |
1230 AMD_CG_SUPPORT_GFX_CP_LS |
1231 AMD_CG_SUPPORT_HDP_MGCG |
1232 AMD_CG_SUPPORT_HDP_LS |
1233 AMD_CG_SUPPORT_SDMA_MGCG |
1234 AMD_CG_SUPPORT_SDMA_LS |
1235 AMD_CG_SUPPORT_MC_MGCG |
1236 AMD_CG_SUPPORT_MC_LS |
1237 AMD_CG_SUPPORT_IH_CG |
1238 AMD_CG_SUPPORT_VCN_MGCG |
1239 AMD_CG_SUPPORT_JPEG_MGCG;
1240 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1241 adev->external_rev_id = adev->rev_id + 0x32;
1242 break;
1243 case CHIP_RENOIR:
1244 adev->asic_funcs = &soc15_asic_funcs;
1245 if (adev->pdev->device == 0x1636)
1246 adev->apu_flags |= AMD_APU_IS_RENOIR;
1247 else
1248 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1249
1250 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1251 adev->external_rev_id = adev->rev_id + 0x91;
1252 else
1253 adev->external_rev_id = adev->rev_id + 0xa1;
1254 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1255 AMD_CG_SUPPORT_GFX_MGLS |
1256 AMD_CG_SUPPORT_GFX_3D_CGCG |
1257 AMD_CG_SUPPORT_GFX_3D_CGLS |
1258 AMD_CG_SUPPORT_GFX_CGCG |
1259 AMD_CG_SUPPORT_GFX_CGLS |
1260 AMD_CG_SUPPORT_GFX_CP_LS |
1261 AMD_CG_SUPPORT_MC_MGCG |
1262 AMD_CG_SUPPORT_MC_LS |
1263 AMD_CG_SUPPORT_SDMA_MGCG |
1264 AMD_CG_SUPPORT_SDMA_LS |
1265 AMD_CG_SUPPORT_BIF_LS |
1266 AMD_CG_SUPPORT_HDP_LS |
1267 AMD_CG_SUPPORT_ROM_MGCG |
1268 AMD_CG_SUPPORT_VCN_MGCG |
1269 AMD_CG_SUPPORT_JPEG_MGCG |
1270 AMD_CG_SUPPORT_IH_CG |
1271 AMD_CG_SUPPORT_ATHUB_LS |
1272 AMD_CG_SUPPORT_ATHUB_MGCG |
1273 AMD_CG_SUPPORT_DF_MGCG;
1274 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1275 AMD_PG_SUPPORT_VCN |
1276 AMD_PG_SUPPORT_JPEG |
1277 AMD_PG_SUPPORT_VCN_DPG;
1278 break;
1279 default:
1280
1281 return -EINVAL;
1282 }
1283
1284 if (amdgpu_sriov_vf(adev)) {
1285 amdgpu_virt_init_setting(adev);
1286 xgpu_ai_mailbox_set_irq_funcs(adev);
1287 }
1288
1289 return 0;
1290}
1291
1292static int soc15_common_late_init(void *handle)
1293{
1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295 int r = 0;
1296
1297 if (amdgpu_sriov_vf(adev))
1298 xgpu_ai_mailbox_get_irq(adev);
1299
1300 if (adev->asic_funcs &&
1301 adev->asic_funcs->reset_hdp_ras_error_count)
1302 adev->asic_funcs->reset_hdp_ras_error_count(adev);
1303
1304 if (adev->nbio.funcs->ras_late_init)
1305 r = adev->nbio.funcs->ras_late_init(adev);
1306
1307 return r;
1308}
1309
1310static int soc15_common_sw_init(void *handle)
1311{
1312 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313
1314 if (amdgpu_sriov_vf(adev))
1315 xgpu_ai_mailbox_add_irq_id(adev);
1316
1317 adev->df.funcs->sw_init(adev);
1318
1319 return 0;
1320}
1321
1322static int soc15_common_sw_fini(void *handle)
1323{
1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1325
1326 amdgpu_nbio_ras_fini(adev);
1327 adev->df.funcs->sw_fini(adev);
1328 return 0;
1329}
1330
1331static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1332{
1333 int i;
1334 struct amdgpu_ring *ring;
1335
1336
1337 if (!amdgpu_sriov_vf(adev)) {
1338 for (i = 0; i < adev->sdma.num_instances; i++) {
1339 ring = &adev->sdma.instance[i].ring;
1340 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1341 ring->use_doorbell, ring->doorbell_index,
1342 adev->doorbell_index.sdma_doorbell_range);
1343 }
1344
1345 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1346 adev->irq.ih.doorbell_index);
1347 }
1348}
1349
1350static int soc15_common_hw_init(void *handle)
1351{
1352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1353
1354
1355 soc15_pcie_gen3_enable(adev);
1356
1357 soc15_program_aspm(adev);
1358
1359 adev->nbio.funcs->init_registers(adev);
1360
1361
1362
1363
1364 if (adev->nbio.funcs->remap_hdp_registers)
1365 adev->nbio.funcs->remap_hdp_registers(adev);
1366
1367
1368 soc15_enable_doorbell_aperture(adev, true);
1369
1370
1371
1372
1373
1374 soc15_doorbell_range_init(adev);
1375
1376 return 0;
1377}
1378
1379static int soc15_common_hw_fini(void *handle)
1380{
1381 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1382
1383
1384 soc15_enable_doorbell_aperture(adev, false);
1385 if (amdgpu_sriov_vf(adev))
1386 xgpu_ai_mailbox_put_irq(adev);
1387
1388 if (adev->nbio.ras_if &&
1389 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1390 if (adev->nbio.funcs->init_ras_controller_interrupt)
1391 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1392 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1393 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1394 }
1395
1396 return 0;
1397}
1398
1399static int soc15_common_suspend(void *handle)
1400{
1401 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1402
1403 return soc15_common_hw_fini(adev);
1404}
1405
1406static int soc15_common_resume(void *handle)
1407{
1408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1409
1410 return soc15_common_hw_init(adev);
1411}
1412
1413static bool soc15_common_is_idle(void *handle)
1414{
1415 return true;
1416}
1417
1418static int soc15_common_wait_for_idle(void *handle)
1419{
1420 return 0;
1421}
1422
1423static int soc15_common_soft_reset(void *handle)
1424{
1425 return 0;
1426}
1427
1428static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1429{
1430 uint32_t def, data;
1431
1432 if (adev->asic_type == CHIP_VEGA20 ||
1433 adev->asic_type == CHIP_ARCTURUS ||
1434 adev->asic_type == CHIP_RENOIR) {
1435 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1436
1437 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1438 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1439 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1440 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1441 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1442 else
1443 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1444 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1445 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1446 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1447
1448 if (def != data)
1449 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1450 } else {
1451 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1452
1453 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1454 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1455 else
1456 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1457
1458 if (def != data)
1459 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1460 }
1461}
1462
1463static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1464{
1465 uint32_t def, data;
1466
1467 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1468
1469 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1470 data &= ~(0x01000000 |
1471 0x02000000 |
1472 0x04000000 |
1473 0x08000000 |
1474 0x10000000 |
1475 0x20000000 |
1476 0x40000000 |
1477 0x80000000);
1478 else
1479 data |= (0x01000000 |
1480 0x02000000 |
1481 0x04000000 |
1482 0x08000000 |
1483 0x10000000 |
1484 0x20000000 |
1485 0x40000000 |
1486 0x80000000);
1487
1488 if (def != data)
1489 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1490}
1491
1492static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1493{
1494 uint32_t def, data;
1495
1496 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1497
1498 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1499 data |= 1;
1500 else
1501 data &= ~1;
1502
1503 if (def != data)
1504 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1505}
1506
1507static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1508 bool enable)
1509{
1510 uint32_t def, data;
1511
1512 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1513
1514 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1515 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1516 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1517 else
1518 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1519 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1520
1521 if (def != data)
1522 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1523}
1524
1525static int soc15_common_set_clockgating_state(void *handle,
1526 enum amd_clockgating_state state)
1527{
1528 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1529
1530 if (amdgpu_sriov_vf(adev))
1531 return 0;
1532
1533 switch (adev->asic_type) {
1534 case CHIP_VEGA10:
1535 case CHIP_VEGA12:
1536 case CHIP_VEGA20:
1537 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1538 state == AMD_CG_STATE_GATE);
1539 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1540 state == AMD_CG_STATE_GATE);
1541 soc15_update_hdp_light_sleep(adev,
1542 state == AMD_CG_STATE_GATE);
1543 soc15_update_drm_clock_gating(adev,
1544 state == AMD_CG_STATE_GATE);
1545 soc15_update_drm_light_sleep(adev,
1546 state == AMD_CG_STATE_GATE);
1547 soc15_update_rom_medium_grain_clock_gating(adev,
1548 state == AMD_CG_STATE_GATE);
1549 adev->df.funcs->update_medium_grain_clock_gating(adev,
1550 state == AMD_CG_STATE_GATE);
1551 break;
1552 case CHIP_RAVEN:
1553 case CHIP_RENOIR:
1554 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1555 state == AMD_CG_STATE_GATE);
1556 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1557 state == AMD_CG_STATE_GATE);
1558 soc15_update_hdp_light_sleep(adev,
1559 state == AMD_CG_STATE_GATE);
1560 soc15_update_drm_clock_gating(adev,
1561 state == AMD_CG_STATE_GATE);
1562 soc15_update_drm_light_sleep(adev,
1563 state == AMD_CG_STATE_GATE);
1564 soc15_update_rom_medium_grain_clock_gating(adev,
1565 state == AMD_CG_STATE_GATE);
1566 break;
1567 case CHIP_ARCTURUS:
1568 soc15_update_hdp_light_sleep(adev,
1569 state == AMD_CG_STATE_GATE);
1570 break;
1571 default:
1572 break;
1573 }
1574 return 0;
1575}
1576
1577static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1578{
1579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1580 int data;
1581
1582 if (amdgpu_sriov_vf(adev))
1583 *flags = 0;
1584
1585 adev->nbio.funcs->get_clockgating_state(adev, flags);
1586
1587
1588 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1589 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1590 *flags |= AMD_CG_SUPPORT_HDP_LS;
1591
1592
1593 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1594 if (!(data & 0x01000000))
1595 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1596
1597
1598 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1599 if (data & 0x1)
1600 *flags |= AMD_CG_SUPPORT_DRM_LS;
1601
1602
1603 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1604 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1605 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1606
1607 adev->df.funcs->get_clockgating_state(adev, flags);
1608}
1609
1610static int soc15_common_set_powergating_state(void *handle,
1611 enum amd_powergating_state state)
1612{
1613
1614 return 0;
1615}
1616
1617const struct amd_ip_funcs soc15_common_ip_funcs = {
1618 .name = "soc15_common",
1619 .early_init = soc15_common_early_init,
1620 .late_init = soc15_common_late_init,
1621 .sw_init = soc15_common_sw_init,
1622 .sw_fini = soc15_common_sw_fini,
1623 .hw_init = soc15_common_hw_init,
1624 .hw_fini = soc15_common_hw_fini,
1625 .suspend = soc15_common_suspend,
1626 .resume = soc15_common_resume,
1627 .is_idle = soc15_common_is_idle,
1628 .wait_for_idle = soc15_common_wait_for_idle,
1629 .soft_reset = soc15_common_soft_reset,
1630 .set_clockgating_state = soc15_common_set_clockgating_state,
1631 .set_powergating_state = soc15_common_set_powergating_state,
1632 .get_clockgating_state= soc15_common_get_clockgating_state,
1633};
1634
