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24#define SWSMU_CODE_LAYER_L2
25
26#include "amdgpu.h"
27#include "amdgpu_smu.h"
28#include "smu_v12_0_ppsmc.h"
29#include "smu12_driver_if.h"
30#include "smu_v12_0.h"
31#include "renoir_ppt.h"
32#include "smu_cmn.h"
33
34
35
36
37
38
39#undef pr_err
40#undef pr_warn
41#undef pr_info
42#undef pr_debug
43
44static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1),
49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1),
56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1),
57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1),
58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
59 MSG_MAP(Spare1, PPSMC_MSG_spare1, 1),
60 MSG_MAP(Spare2, PPSMC_MSG_spare2, 1),
61 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
62 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
63 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
64 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
65 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
66 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
67 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1),
68 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
69 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
70 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
71 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
72 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
73 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1),
74 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1),
75 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
76 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1),
77 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
78 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1),
79 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1),
80 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1),
81 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1),
82 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
83 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
84 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
85 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
86 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1),
87 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1),
88 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1),
89 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1),
90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
95 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1),
96 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1),
97 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
98 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
99 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1),
100 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
101 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
102 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
103 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1),
104 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1),
105 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
106};
107
108static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
109 CLK_MAP(GFXCLK, CLOCK_GFXCLK),
110 CLK_MAP(SCLK, CLOCK_GFXCLK),
111 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
112 CLK_MAP(UCLK, CLOCK_FCLK),
113 CLK_MAP(MCLK, CLOCK_FCLK),
114};
115
116static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
117 TAB_MAP_VALID(WATERMARKS),
118 TAB_MAP_INVALID(CUSTOM_DPM),
119 TAB_MAP_VALID(DPMCLOCKS),
120 TAB_MAP_VALID(SMU_METRICS),
121};
122
123static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
127 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
128 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
129};
130
131static int renoir_init_smc_tables(struct smu_context *smu)
132{
133 struct smu_table_context *smu_table = &smu->smu_table;
134 struct smu_table *tables = smu_table->tables;
135
136 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
137 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
138 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
139 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
140 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
141 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
142
143 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
144 if (!smu_table->clocks_table)
145 goto err0_out;
146
147 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
148 if (!smu_table->metrics_table)
149 goto err1_out;
150 smu_table->metrics_time = 0;
151
152 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
153 if (!smu_table->watermarks_table)
154 goto err2_out;
155
156 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0);
157 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
158 if (!smu_table->gpu_metrics_table)
159 goto err3_out;
160
161 return 0;
162
163err3_out:
164 kfree(smu_table->watermarks_table);
165err2_out:
166 kfree(smu_table->metrics_table);
167err1_out:
168 kfree(smu_table->clocks_table);
169err0_out:
170 return -ENOMEM;
171}
172
173
174
175
176
177static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
178 uint32_t dpm_level, uint32_t *freq)
179{
180 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
181
182 if (!clk_table || clk_type >= SMU_CLK_COUNT)
183 return -EINVAL;
184
185 switch (clk_type) {
186 case SMU_SOCCLK:
187 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
188 return -EINVAL;
189 *freq = clk_table->SocClocks[dpm_level].Freq;
190 break;
191 case SMU_MCLK:
192 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
193 return -EINVAL;
194 *freq = clk_table->FClocks[dpm_level].Freq;
195 break;
196 case SMU_DCEFCLK:
197 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
198 return -EINVAL;
199 *freq = clk_table->DcfClocks[dpm_level].Freq;
200 break;
201 case SMU_FCLK:
202 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
203 return -EINVAL;
204 *freq = clk_table->FClocks[dpm_level].Freq;
205 break;
206 default:
207 return -EINVAL;
208 }
209
210 return 0;
211}
212
213static int renoir_get_profiling_clk_mask(struct smu_context *smu,
214 enum amd_dpm_forced_level level,
215 uint32_t *sclk_mask,
216 uint32_t *mclk_mask,
217 uint32_t *soc_mask)
218{
219
220 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
221 if (sclk_mask)
222 *sclk_mask = 0;
223 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
224 if (mclk_mask)
225
226 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
227 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
228 if(sclk_mask)
229
230 *sclk_mask = 3 - 1;
231
232 if(mclk_mask)
233
234 *mclk_mask = 0;
235
236 if(soc_mask)
237 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
238 }
239
240 return 0;
241}
242
243static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
244 enum smu_clk_type clk_type,
245 uint32_t *min,
246 uint32_t *max)
247{
248 int ret = 0;
249 uint32_t mclk_mask, soc_mask;
250 uint32_t clock_limit;
251
252 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
253 switch (clk_type) {
254 case SMU_MCLK:
255 case SMU_UCLK:
256 clock_limit = smu->smu_table.boot_values.uclk;
257 break;
258 case SMU_GFXCLK:
259 case SMU_SCLK:
260 clock_limit = smu->smu_table.boot_values.gfxclk;
261 break;
262 case SMU_SOCCLK:
263 clock_limit = smu->smu_table.boot_values.socclk;
264 break;
265 default:
266 clock_limit = 0;
267 break;
268 }
269
270
271 if (min)
272 *min = clock_limit / 100;
273 if (max)
274 *max = clock_limit / 100;
275
276 return 0;
277 }
278
279 if (max) {
280 ret = renoir_get_profiling_clk_mask(smu,
281 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
282 NULL,
283 &mclk_mask,
284 &soc_mask);
285 if (ret)
286 goto failed;
287
288 switch (clk_type) {
289 case SMU_GFXCLK:
290 case SMU_SCLK:
291 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
292 if (ret) {
293 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
294 goto failed;
295 }
296 break;
297 case SMU_UCLK:
298 case SMU_FCLK:
299 case SMU_MCLK:
300 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
301 if (ret)
302 goto failed;
303 break;
304 case SMU_SOCCLK:
305 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
306 if (ret)
307 goto failed;
308 break;
309 default:
310 ret = -EINVAL;
311 goto failed;
312 }
313 }
314
315 if (min) {
316 switch (clk_type) {
317 case SMU_GFXCLK:
318 case SMU_SCLK:
319 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
320 if (ret) {
321 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
322 goto failed;
323 }
324 break;
325 case SMU_UCLK:
326 case SMU_FCLK:
327 case SMU_MCLK:
328 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
329 if (ret)
330 goto failed;
331 break;
332 case SMU_SOCCLK:
333 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
334 if (ret)
335 goto failed;
336 break;
337 default:
338 ret = -EINVAL;
339 goto failed;
340 }
341 }
342failed:
343 return ret;
344}
345
346static int renoir_print_clk_levels(struct smu_context *smu,
347 enum smu_clk_type clk_type, char *buf)
348{
349 int i, size = 0, ret = 0;
350 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
351 SmuMetrics_t metrics;
352 bool cur_value_match_level = false;
353
354 memset(&metrics, 0, sizeof(metrics));
355
356 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
357 if (ret)
358 return ret;
359
360 switch (clk_type) {
361 case SMU_GFXCLK:
362 case SMU_SCLK:
363
364 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
365 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
366 if (!ret) {
367
368 if (cur_value == max)
369 i = 2;
370 else if (cur_value == min)
371 i = 0;
372 else
373 i = 1;
374
375 size += sprintf(buf + size, "0: %uMhz %s\n", min,
376 i == 0 ? "*" : "");
377 size += sprintf(buf + size, "1: %uMhz %s\n",
378 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
379 i == 1 ? "*" : "");
380 size += sprintf(buf + size, "2: %uMhz %s\n", max,
381 i == 2 ? "*" : "");
382 }
383 return size;
384 case SMU_SOCCLK:
385 count = NUM_SOCCLK_DPM_LEVELS;
386 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
387 break;
388 case SMU_MCLK:
389 count = NUM_MEMCLK_DPM_LEVELS;
390 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
391 break;
392 case SMU_DCEFCLK:
393 count = NUM_DCFCLK_DPM_LEVELS;
394 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
395 break;
396 case SMU_FCLK:
397 count = NUM_FCLK_DPM_LEVELS;
398 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
399 break;
400 default:
401 return -EINVAL;
402 }
403
404 for (i = 0; i < count; i++) {
405 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
406 if (ret)
407 return ret;
408 if (!value)
409 continue;
410 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
411 cur_value == value ? "*" : "");
412 if (cur_value == value)
413 cur_value_match_level = true;
414 }
415
416 if (!cur_value_match_level)
417 size += sprintf(buf + size, " %uMhz *\n", cur_value);
418
419 return size;
420}
421
422static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
423{
424 enum amd_pm_state_type pm_type;
425 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
426
427 if (!smu_dpm_ctx->dpm_context ||
428 !smu_dpm_ctx->dpm_current_power_state)
429 return -EINVAL;
430
431 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
432 case SMU_STATE_UI_LABEL_BATTERY:
433 pm_type = POWER_STATE_TYPE_BATTERY;
434 break;
435 case SMU_STATE_UI_LABEL_BALLANCED:
436 pm_type = POWER_STATE_TYPE_BALANCED;
437 break;
438 case SMU_STATE_UI_LABEL_PERFORMANCE:
439 pm_type = POWER_STATE_TYPE_PERFORMANCE;
440 break;
441 default:
442 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
443 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
444 else
445 pm_type = POWER_STATE_TYPE_DEFAULT;
446 break;
447 }
448
449 return pm_type;
450}
451
452static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
453{
454 int ret = 0;
455
456 if (enable) {
457
458 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
459 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
460 if (ret)
461 return ret;
462 }
463 } else {
464 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
465 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
466 if (ret)
467 return ret;
468 }
469 }
470
471 return ret;
472}
473
474static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
475{
476 int ret = 0;
477
478 if (enable) {
479 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
480 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
481 if (ret)
482 return ret;
483 }
484 } else {
485 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
486 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
487 if (ret)
488 return ret;
489 }
490 }
491
492 return ret;
493}
494
495static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
496 enum smu_clk_type clk_type,
497 uint32_t *value)
498{
499 int ret = 0, clk_id = 0;
500 SmuMetrics_t metrics;
501
502 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
503 if (ret)
504 return ret;
505
506 clk_id = smu_cmn_to_asic_specific_index(smu,
507 CMN2ASIC_MAPPING_CLK,
508 clk_type);
509 if (clk_id < 0)
510 return clk_id;
511
512 *value = metrics.ClockFrequency[clk_id];
513
514 return ret;
515}
516
517static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
518{
519 int ret = 0, i = 0;
520 uint32_t min_freq, max_freq, force_freq;
521 enum smu_clk_type clk_type;
522
523 enum smu_clk_type clks[] = {
524 SMU_GFXCLK,
525 SMU_MCLK,
526 SMU_SOCCLK,
527 };
528
529 for (i = 0; i < ARRAY_SIZE(clks); i++) {
530 clk_type = clks[i];
531 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
532 if (ret)
533 return ret;
534
535 force_freq = highest ? max_freq : min_freq;
536 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
537 if (ret)
538 return ret;
539 }
540
541 return ret;
542}
543
544static int renoir_unforce_dpm_levels(struct smu_context *smu) {
545
546 int ret = 0, i = 0;
547 uint32_t min_freq, max_freq;
548 enum smu_clk_type clk_type;
549
550 struct clk_feature_map {
551 enum smu_clk_type clk_type;
552 uint32_t feature;
553 } clk_feature_map[] = {
554 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
555 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
556 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
557 };
558
559 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
560 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
561 continue;
562
563 clk_type = clk_feature_map[i].clk_type;
564
565 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
566 if (ret)
567 return ret;
568
569 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
570 if (ret)
571 return ret;
572 }
573
574 return ret;
575}
576
577static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
578{
579 int ret = 0;
580 SmuMetrics_t metrics;
581
582 if (!value)
583 return -EINVAL;
584
585 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
586 if (ret)
587 return ret;
588
589 *value = (metrics.GfxTemperature / 100) *
590 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
591
592 return 0;
593}
594
595static int renoir_get_current_activity_percent(struct smu_context *smu,
596 enum amd_pp_sensors sensor,
597 uint32_t *value)
598{
599 int ret = 0;
600 SmuMetrics_t metrics;
601
602 if (!value)
603 return -EINVAL;
604
605 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
606 if (ret)
607 return ret;
608
609 switch (sensor) {
610 case AMDGPU_PP_SENSOR_GPU_LOAD:
611 *value = metrics.AverageGfxActivity / 100;
612 break;
613 default:
614 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
615 return -EINVAL;
616 }
617
618 return 0;
619}
620
621static int renoir_get_vddc(struct smu_context *smu, uint32_t *value,
622 unsigned int index)
623{
624 int ret = 0;
625 SmuMetrics_t metrics;
626
627 if (index >= 2)
628 return -EINVAL;
629
630 if (!value)
631 return -EINVAL;
632
633 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
634 if (ret)
635 return ret;
636
637 *value = metrics.Voltage[index];
638
639 return 0;
640}
641
642static int renoir_get_power(struct smu_context *smu, uint32_t *value)
643{
644 int ret = 0;
645 SmuMetrics_t metrics;
646
647 if (!value)
648 return -EINVAL;
649
650 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
651 if (ret)
652 return ret;
653
654 *value = metrics.CurrentSocketPower << 8;
655
656 return 0;
657}
658
659
660
661
662static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
663{
664 DpmClocks_t *table = smu->smu_table.clocks_table;
665 int i;
666
667 if (!clock_table || !table)
668 return -EINVAL;
669
670 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
671 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
672 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
673 }
674
675 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
676 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
677 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
678 }
679
680 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
681 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
682 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
683 }
684
685 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
686 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
687 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
688 }
689
690 return 0;
691}
692
693static int renoir_force_clk_levels(struct smu_context *smu,
694 enum smu_clk_type clk_type, uint32_t mask)
695{
696
697 int ret = 0 ;
698 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
699
700 soft_min_level = mask ? (ffs(mask) - 1) : 0;
701 soft_max_level = mask ? (fls(mask) - 1) : 0;
702
703 switch (clk_type) {
704 case SMU_GFXCLK:
705 case SMU_SCLK:
706 if (soft_min_level > 2 || soft_max_level > 2) {
707 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
708 return -EINVAL;
709 }
710
711 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
712 if (ret)
713 return ret;
714 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
715 soft_max_level == 0 ? min_freq :
716 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
717 NULL);
718 if (ret)
719 return ret;
720 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
721 soft_min_level == 2 ? max_freq :
722 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
723 NULL);
724 if (ret)
725 return ret;
726 break;
727 case SMU_SOCCLK:
728 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
729 if (ret)
730 return ret;
731 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
732 if (ret)
733 return ret;
734 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
735 if (ret)
736 return ret;
737 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
738 if (ret)
739 return ret;
740 break;
741 case SMU_MCLK:
742 case SMU_FCLK:
743 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
744 if (ret)
745 return ret;
746 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
747 if (ret)
748 return ret;
749 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
750 if (ret)
751 return ret;
752 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
753 if (ret)
754 return ret;
755 break;
756 default:
757 break;
758 }
759
760 return ret;
761}
762
763static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
764{
765 int workload_type, ret;
766 uint32_t profile_mode = input[size];
767
768 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
769 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
770 return -EINVAL;
771 }
772
773
774 workload_type = smu_cmn_to_asic_specific_index(smu,
775 CMN2ASIC_MAPPING_WORKLOAD,
776 profile_mode);
777 if (workload_type < 0) {
778
779
780
781
782 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
783 return -EINVAL;
784 }
785
786 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
787 1 << workload_type,
788 NULL);
789 if (ret) {
790 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
791 return ret;
792 }
793
794 smu->power_profile_mode = profile_mode;
795
796 return 0;
797}
798
799static int renoir_set_peak_clock_by_device(struct smu_context *smu)
800{
801 int ret = 0;
802 uint32_t sclk_freq = 0, uclk_freq = 0;
803
804 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
805 if (ret)
806 return ret;
807
808 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
809 if (ret)
810 return ret;
811
812 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
813 if (ret)
814 return ret;
815
816 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
817 if (ret)
818 return ret;
819
820 return ret;
821}
822
823static int renoir_set_performance_level(struct smu_context *smu,
824 enum amd_dpm_forced_level level)
825{
826 int ret = 0;
827 uint32_t sclk_mask, mclk_mask, soc_mask;
828
829 switch (level) {
830 case AMD_DPM_FORCED_LEVEL_HIGH:
831 ret = renoir_force_dpm_limit_value(smu, true);
832 break;
833 case AMD_DPM_FORCED_LEVEL_LOW:
834 ret = renoir_force_dpm_limit_value(smu, false);
835 break;
836 case AMD_DPM_FORCED_LEVEL_AUTO:
837 ret = renoir_unforce_dpm_levels(smu);
838 break;
839 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
840 ret = smu_cmn_send_smc_msg_with_param(smu,
841 SMU_MSG_SetHardMinGfxClk,
842 RENOIR_UMD_PSTATE_GFXCLK,
843 NULL);
844 if (ret)
845 return ret;
846 ret = smu_cmn_send_smc_msg_with_param(smu,
847 SMU_MSG_SetHardMinFclkByFreq,
848 RENOIR_UMD_PSTATE_FCLK,
849 NULL);
850 if (ret)
851 return ret;
852 ret = smu_cmn_send_smc_msg_with_param(smu,
853 SMU_MSG_SetHardMinSocclkByFreq,
854 RENOIR_UMD_PSTATE_SOCCLK,
855 NULL);
856 if (ret)
857 return ret;
858 ret = smu_cmn_send_smc_msg_with_param(smu,
859 SMU_MSG_SetHardMinVcn,
860 RENOIR_UMD_PSTATE_VCNCLK,
861 NULL);
862 if (ret)
863 return ret;
864
865 ret = smu_cmn_send_smc_msg_with_param(smu,
866 SMU_MSG_SetSoftMaxGfxClk,
867 RENOIR_UMD_PSTATE_GFXCLK,
868 NULL);
869 if (ret)
870 return ret;
871 ret = smu_cmn_send_smc_msg_with_param(smu,
872 SMU_MSG_SetSoftMaxFclkByFreq,
873 RENOIR_UMD_PSTATE_FCLK,
874 NULL);
875 if (ret)
876 return ret;
877 ret = smu_cmn_send_smc_msg_with_param(smu,
878 SMU_MSG_SetSoftMaxSocclkByFreq,
879 RENOIR_UMD_PSTATE_SOCCLK,
880 NULL);
881 if (ret)
882 return ret;
883 ret = smu_cmn_send_smc_msg_with_param(smu,
884 SMU_MSG_SetSoftMaxVcn,
885 RENOIR_UMD_PSTATE_VCNCLK,
886 NULL);
887 if (ret)
888 return ret;
889 break;
890 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
891 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
892 ret = renoir_get_profiling_clk_mask(smu, level,
893 &sclk_mask,
894 &mclk_mask,
895 &soc_mask);
896 if (ret)
897 return ret;
898 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
899 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
900 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
901 break;
902 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
903 ret = renoir_set_peak_clock_by_device(smu);
904 break;
905 case AMD_DPM_FORCED_LEVEL_MANUAL:
906 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
907 default:
908 break;
909 }
910 return ret;
911}
912
913
914
915
916static int renoir_set_watermarks_table(
917 struct smu_context *smu,
918 struct pp_smu_wm_range_sets *clock_ranges)
919{
920 Watermarks_t *table = smu->smu_table.watermarks_table;
921 int ret = 0;
922 int i;
923
924 if (clock_ranges) {
925 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
926 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
927 return -EINVAL;
928
929
930 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
931 table->WatermarkRow[WM_DCFCLK][i].MinClock =
932 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
933 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
934 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
935 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
936 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
937 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
938 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
939
940 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
941 clock_ranges->reader_wm_sets[i].wm_inst;
942 table->WatermarkRow[WM_DCFCLK][i].WmType =
943 clock_ranges->reader_wm_sets[i].wm_type;
944 }
945
946 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
947 table->WatermarkRow[WM_SOCCLK][i].MinClock =
948 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
949 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
950 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
951 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
952 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
953 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
954 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
955
956 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
957 clock_ranges->writer_wm_sets[i].wm_inst;
958 table->WatermarkRow[WM_SOCCLK][i].WmType =
959 clock_ranges->writer_wm_sets[i].wm_type;
960 }
961
962 smu->watermarks_bitmap |= WATERMARKS_EXIST;
963 }
964
965
966 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
967 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
968 ret = smu_cmn_write_watermarks_table(smu);
969 if (ret) {
970 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
971 return ret;
972 }
973 smu->watermarks_bitmap |= WATERMARKS_LOADED;
974 }
975
976 return 0;
977}
978
979static int renoir_get_power_profile_mode(struct smu_context *smu,
980 char *buf)
981{
982 static const char *profile_name[] = {
983 "BOOTUP_DEFAULT",
984 "3D_FULL_SCREEN",
985 "POWER_SAVING",
986 "VIDEO",
987 "VR",
988 "COMPUTE",
989 "CUSTOM"};
990 uint32_t i, size = 0;
991 int16_t workload_type = 0;
992
993 if (!buf)
994 return -EINVAL;
995
996 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
997
998
999
1000
1001 workload_type = smu_cmn_to_asic_specific_index(smu,
1002 CMN2ASIC_MAPPING_WORKLOAD,
1003 i);
1004 if (workload_type < 0)
1005 continue;
1006
1007 size += sprintf(buf + size, "%2d %14s%s\n",
1008 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1009 }
1010
1011 return size;
1012}
1013
1014static int renoir_read_sensor(struct smu_context *smu,
1015 enum amd_pp_sensors sensor,
1016 void *data, uint32_t *size)
1017{
1018 int ret = 0;
1019
1020 if (!data || !size)
1021 return -EINVAL;
1022
1023 mutex_lock(&smu->sensor_lock);
1024 switch (sensor) {
1025 case AMDGPU_PP_SENSOR_GPU_LOAD:
1026 ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1027 *size = 4;
1028 break;
1029 case AMDGPU_PP_SENSOR_GPU_TEMP:
1030 ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
1031 *size = 4;
1032 break;
1033 case AMDGPU_PP_SENSOR_GFX_MCLK:
1034 ret = renoir_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1035 *(uint32_t *)data *= 100;
1036 *size = 4;
1037 break;
1038 case AMDGPU_PP_SENSOR_GFX_SCLK:
1039 ret = renoir_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1040 *(uint32_t *)data *= 100;
1041 *size = 4;
1042 break;
1043 case AMDGPU_PP_SENSOR_VDDGFX:
1044 ret = renoir_get_vddc(smu, (uint32_t *)data, 0);
1045 *size = 4;
1046 break;
1047 case AMDGPU_PP_SENSOR_VDDNB:
1048 ret = renoir_get_vddc(smu, (uint32_t *)data, 1);
1049 *size = 4;
1050 break;
1051 case AMDGPU_PP_SENSOR_GPU_POWER:
1052 ret = renoir_get_power(smu, (uint32_t *)data);
1053 *size = 4;
1054 break;
1055 default:
1056 ret = -EOPNOTSUPP;
1057 break;
1058 }
1059 mutex_unlock(&smu->sensor_lock);
1060
1061 return ret;
1062}
1063
1064static bool renoir_is_dpm_running(struct smu_context *smu)
1065{
1066 struct amdgpu_device *adev = smu->adev;
1067
1068
1069
1070
1071
1072
1073 if (adev->in_suspend)
1074 return false;
1075 else
1076 return true;
1077
1078}
1079
1080static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1081 void **table)
1082{
1083 struct smu_table_context *smu_table = &smu->smu_table;
1084 struct gpu_metrics_v2_0 *gpu_metrics =
1085 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table;
1086 SmuMetrics_t metrics;
1087 int ret = 0;
1088
1089 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1090 if (ret)
1091 return ret;
1092
1093 smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics);
1094
1095 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1096 gpu_metrics->temperature_soc = metrics.SocTemperature;
1097 memcpy(&gpu_metrics->temperature_core[0],
1098 &metrics.CoreTemperature[0],
1099 sizeof(uint16_t) * 8);
1100 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1101 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1102
1103 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1104 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1105
1106 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1107 gpu_metrics->average_cpu_power = metrics.Power[0];
1108 gpu_metrics->average_soc_power = metrics.Power[1];
1109 memcpy(&gpu_metrics->average_core_power[0],
1110 &metrics.CorePower[0],
1111 sizeof(uint16_t) * 8);
1112
1113 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1114 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1115 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1116 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1117
1118 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1119 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1120 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1121 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1122 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1123 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1124 memcpy(&gpu_metrics->current_coreclk[0],
1125 &metrics.CoreFrequency[0],
1126 sizeof(uint16_t) * 8);
1127 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1128 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1129
1130 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1131
1132 gpu_metrics->fan_pwm = metrics.FanPwm;
1133
1134 *table = (void *)gpu_metrics;
1135
1136 return sizeof(struct gpu_metrics_v2_0);
1137}
1138
1139static const struct pptable_funcs renoir_ppt_funcs = {
1140 .set_power_state = NULL,
1141 .print_clk_levels = renoir_print_clk_levels,
1142 .get_current_power_state = renoir_get_current_power_state,
1143 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1144 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1145 .force_clk_levels = renoir_force_clk_levels,
1146 .set_power_profile_mode = renoir_set_power_profile_mode,
1147 .set_performance_level = renoir_set_performance_level,
1148 .get_dpm_clock_table = renoir_get_dpm_clock_table,
1149 .set_watermarks_table = renoir_set_watermarks_table,
1150 .get_power_profile_mode = renoir_get_power_profile_mode,
1151 .read_sensor = renoir_read_sensor,
1152 .check_fw_status = smu_v12_0_check_fw_status,
1153 .check_fw_version = smu_v12_0_check_fw_version,
1154 .powergate_sdma = smu_v12_0_powergate_sdma,
1155 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1156 .send_smc_msg = smu_cmn_send_smc_msg,
1157 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1158 .gfx_off_control = smu_v12_0_gfx_off_control,
1159 .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1160 .init_smc_tables = renoir_init_smc_tables,
1161 .fini_smc_tables = smu_v12_0_fini_smc_tables,
1162 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1163 .get_enabled_mask = smu_cmn_get_enabled_mask,
1164 .feature_is_enabled = smu_cmn_feature_is_enabled,
1165 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1166 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1167 .mode2_reset = smu_v12_0_mode2_reset,
1168 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1169 .set_driver_table_location = smu_v12_0_set_driver_table_location,
1170 .is_dpm_running = renoir_is_dpm_running,
1171 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1172 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1173 .get_gpu_metrics = renoir_get_gpu_metrics,
1174};
1175
1176void renoir_set_ppt_funcs(struct smu_context *smu)
1177{
1178 smu->ppt_funcs = &renoir_ppt_funcs;
1179 smu->message_map = renoir_message_map;
1180 smu->clock_map = renoir_clk_map;
1181 smu->table_map = renoir_table_map;
1182 smu->workload_map = renoir_workload_map;
1183 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1184 smu->is_apu = true;
1185}
1186
