linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3 */
   4
   5#ifndef _DPU_HW_CATALOG_H
   6#define _DPU_HW_CATALOG_H
   7
   8#include <linux/kernel.h>
   9#include <linux/bug.h>
  10#include <linux/bitmap.h>
  11#include <linux/err.h>
  12
  13/**
  14 * Max hardware block count: For ex: max 12 SSPP pipes or
  15 * 5 ctl paths. In all cases, it can have max 12 hardware blocks
  16 * based on current design
  17 */
  18#define MAX_BLOCKS    12
  19
  20#define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28)    |\
  21                ((MINOR & 0xFFF) << 16)  |\
  22                (STEP & 0xFFFF))
  23
  24#define DPU_HW_MAJOR(rev)               ((rev) >> 28)
  25#define DPU_HW_MINOR(rev)               (((rev) >> 16) & 0xFFF)
  26#define DPU_HW_STEP(rev)                ((rev) & 0xFFFF)
  27#define DPU_HW_MAJOR_MINOR(rev)         ((rev) >> 16)
  28
  29#define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2)   \
  30        (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2)))
  31
  32#define DPU_HW_VER_170  DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */
  33#define DPU_HW_VER_171  DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */
  34#define DPU_HW_VER_172  DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */
  35#define DPU_HW_VER_300  DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */
  36#define DPU_HW_VER_301  DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */
  37#define DPU_HW_VER_400  DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
  38#define DPU_HW_VER_401  DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
  39#define DPU_HW_VER_410  DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
  40#define DPU_HW_VER_500  DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */
  41#define DPU_HW_VER_501  DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */
  42#define DPU_HW_VER_600  DPU_HW_VER(6, 0, 0) /* sm8250 */
  43#define DPU_HW_VER_620  DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
  44
  45
  46#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
  47#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
  48#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
  49#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
  50#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
  51#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620)
  52
  53
  54#define DPU_HW_BLK_NAME_LEN     16
  55
  56#define MAX_IMG_WIDTH 0x3fff
  57#define MAX_IMG_HEIGHT 0x3fff
  58
  59#define CRTC_DUAL_MIXERS        2
  60
  61#define MAX_XIN_COUNT 16
  62
  63/**
  64 * Supported UBWC feature versions
  65 */
  66enum {
  67        DPU_HW_UBWC_VER_10 = 0x100,
  68        DPU_HW_UBWC_VER_20 = 0x200,
  69        DPU_HW_UBWC_VER_30 = 0x300,
  70        DPU_HW_UBWC_VER_40 = 0x400,
  71};
  72
  73/**
  74 * MDP TOP BLOCK features
  75 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
  76 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
  77 * @DPU_MDP_BWC,           MDSS HW supports Bandwidth compression.
  78 * @DPU_MDP_UBWC_1_0,      This chipsets supports Universal Bandwidth
  79 *                         compression initial revision
  80 * @DPU_MDP_UBWC_1_5,      Universal Bandwidth compression version 1.5
  81 * @DPU_MDP_MAX            Maximum value
  82
  83 */
  84enum {
  85        DPU_MDP_PANIC_PER_PIPE = 0x1,
  86        DPU_MDP_10BIT_SUPPORT,
  87        DPU_MDP_BWC,
  88        DPU_MDP_UBWC_1_0,
  89        DPU_MDP_UBWC_1_5,
  90        DPU_MDP_MAX
  91};
  92
  93/**
  94 * SSPP sub-blocks/features
  95 * @DPU_SSPP_SRC             Src and fetch part of the pipes,
  96 * @DPU_SSPP_SCALER_QSEED2,  QSEED2 algorithm support
  97 * @DPU_SSPP_SCALER_QSEED3,  QSEED3 alogorithm support
  98 * @DPU_SSPP_SCALER_QSEED4,  QSEED4 algorithm support
  99 * @DPU_SSPP_SCALER_RGB,     RGB Scaler, supported by RGB pipes
 100 * @DPU_SSPP_CSC,            Support of Color space converion
 101 * @DPU_SSPP_CSC_10BIT,      Support of 10-bit Color space conversion
 102 * @DPU_SSPP_CURSOR,         SSPP can be used as a cursor layer
 103 * @DPU_SSPP_QOS,            SSPP support QoS control, danger/safe/creq
 104 * @DPU_SSPP_QOS_8LVL,       SSPP support 8-level QoS control
 105 * @DPU_SSPP_EXCL_RECT,      SSPP supports exclusion rect
 106 * @DPU_SSPP_SMART_DMA_V1,   SmartDMA 1.0 support
 107 * @DPU_SSPP_SMART_DMA_V2,   SmartDMA 2.0 support
 108 * @DPU_SSPP_TS_PREFILL      Supports prefill with traffic shaper
 109 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
 110 * @DPU_SSPP_CDP             Supports client driven prefetch
 111 * @DPU_SSPP_MAX             maximum value
 112 */
 113enum {
 114        DPU_SSPP_SRC = 0x1,
 115        DPU_SSPP_SCALER_QSEED2,
 116        DPU_SSPP_SCALER_QSEED3,
 117        DPU_SSPP_SCALER_QSEED4,
 118        DPU_SSPP_SCALER_RGB,
 119        DPU_SSPP_CSC,
 120        DPU_SSPP_CSC_10BIT,
 121        DPU_SSPP_CURSOR,
 122        DPU_SSPP_QOS,
 123        DPU_SSPP_QOS_8LVL,
 124        DPU_SSPP_EXCL_RECT,
 125        DPU_SSPP_SMART_DMA_V1,
 126        DPU_SSPP_SMART_DMA_V2,
 127        DPU_SSPP_TS_PREFILL,
 128        DPU_SSPP_TS_PREFILL_REC1,
 129        DPU_SSPP_CDP,
 130        DPU_SSPP_MAX
 131};
 132
 133/*
 134 * MIXER sub-blocks/features
 135 * @DPU_MIXER_LAYER           Layer mixer layer blend configuration,
 136 * @DPU_MIXER_SOURCESPLIT     Layer mixer supports source-split configuration
 137 * @DPU_MIXER_GC              Gamma correction block
 138 * @DPU_DIM_LAYER             Layer mixer supports dim layer
 139 * @DPU_MIXER_MAX             maximum value
 140 */
 141enum {
 142        DPU_MIXER_LAYER = 0x1,
 143        DPU_MIXER_SOURCESPLIT,
 144        DPU_MIXER_GC,
 145        DPU_DIM_LAYER,
 146        DPU_MIXER_MAX
 147};
 148
 149/**
 150 * DSPP sub-blocks
 151 * @DPU_DSPP_PCC             Panel color correction block
 152 * @DPU_DSPP_GC              Gamma correction block
 153 */
 154enum {
 155        DPU_DSPP_PCC = 0x1,
 156        DPU_DSPP_GC,
 157        DPU_DSPP_MAX
 158};
 159
 160/**
 161 * PINGPONG sub-blocks
 162 * @DPU_PINGPONG_TE         Tear check block
 163 * @DPU_PINGPONG_TE2        Additional tear check block for split pipes
 164 * @DPU_PINGPONG_SPLIT      PP block supports split fifo
 165 * @DPU_PINGPONG_SLAVE      PP block is a suitable slave for split fifo
 166 * @DPU_PINGPONG_DITHER,    Dither blocks
 167 * @DPU_PINGPONG_MAX
 168 */
 169enum {
 170        DPU_PINGPONG_TE = 0x1,
 171        DPU_PINGPONG_TE2,
 172        DPU_PINGPONG_SPLIT,
 173        DPU_PINGPONG_SLAVE,
 174        DPU_PINGPONG_DITHER,
 175        DPU_PINGPONG_MAX
 176};
 177
 178/**
 179 * CTL sub-blocks
 180 * @DPU_CTL_SPLIT_DISPLAY       CTL supports video mode split display
 181 * @DPU_CTL_MAX
 182 */
 183enum {
 184        DPU_CTL_SPLIT_DISPLAY = 0x1,
 185        DPU_CTL_ACTIVE_CFG,
 186        DPU_CTL_MAX
 187};
 188
 189/**
 190 * INTF sub-blocks
 191 * @DPU_INTF_INPUT_CTRL         Supports the setting of pp block from which
 192 *                              pixel data arrives to this INTF
 193 * @DPU_INTF_TE                 INTF block has TE configuration support
 194 * @DPU_INTF_MAX
 195 */
 196enum {
 197        DPU_INTF_INPUT_CTRL = 0x1,
 198        DPU_INTF_TE,
 199        DPU_INTF_MAX
 200};
 201
 202/**
 203 * VBIF sub-blocks and features
 204 * @DPU_VBIF_QOS_OTLIM        VBIF supports OT Limit
 205 * @DPU_VBIF_QOS_REMAP        VBIF supports QoS priority remap
 206 * @DPU_VBIF_MAX              maximum value
 207 */
 208enum {
 209        DPU_VBIF_QOS_OTLIM = 0x1,
 210        DPU_VBIF_QOS_REMAP,
 211        DPU_VBIF_MAX
 212};
 213
 214/**
 215 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
 216 * @name:              string name for debug purposes
 217 * @id:                enum identifying this block
 218 * @base:              register base offset to mdss
 219 * @len:               length of hardware block
 220 * @features           bit mask identifying sub-blocks/features
 221 */
 222#define DPU_HW_BLK_INFO \
 223        char name[DPU_HW_BLK_NAME_LEN]; \
 224        u32 id; \
 225        u32 base; \
 226        u32 len; \
 227        unsigned long features
 228
 229/**
 230 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU
 231 * @name:              string name for debug purposes
 232 * @id:                enum identifying this sub-block
 233 * @base:              offset of this sub-block relative to the block
 234 *                     offset
 235 * @len                register block length of this sub-block
 236 */
 237#define DPU_HW_SUBBLK_INFO \
 238        char name[DPU_HW_BLK_NAME_LEN]; \
 239        u32 id; \
 240        u32 base; \
 241        u32 len
 242
 243/**
 244 * struct dpu_src_blk: SSPP part of the source pipes
 245 * @info:   HW register and features supported by this sub-blk
 246 */
 247struct dpu_src_blk {
 248        DPU_HW_SUBBLK_INFO;
 249};
 250
 251/**
 252 * struct dpu_scaler_blk: Scaler information
 253 * @info:   HW register and features supported by this sub-blk
 254 * @version: qseed block revision
 255 */
 256struct dpu_scaler_blk {
 257        DPU_HW_SUBBLK_INFO;
 258        u32 version;
 259};
 260
 261struct dpu_csc_blk {
 262        DPU_HW_SUBBLK_INFO;
 263};
 264
 265/**
 266 * struct dpu_pp_blk : Pixel processing sub-blk information
 267 * @info:   HW register and features supported by this sub-blk
 268 * @version: HW Algorithm version
 269 */
 270struct dpu_pp_blk {
 271        DPU_HW_SUBBLK_INFO;
 272        u32 version;
 273};
 274
 275/**
 276 * enum dpu_qos_lut_usage - define QoS LUT use cases
 277 */
 278enum dpu_qos_lut_usage {
 279        DPU_QOS_LUT_USAGE_LINEAR,
 280        DPU_QOS_LUT_USAGE_MACROTILE,
 281        DPU_QOS_LUT_USAGE_NRT,
 282        DPU_QOS_LUT_USAGE_MAX,
 283};
 284
 285/**
 286 * struct dpu_qos_lut_entry - define QoS LUT table entry
 287 * @fl: fill level, or zero on last entry to indicate default lut
 288 * @lut: lut to use if equal to or less than fill level
 289 */
 290struct dpu_qos_lut_entry {
 291        u32 fl;
 292        u64 lut;
 293};
 294
 295/**
 296 * struct dpu_qos_lut_tbl - define QoS LUT table
 297 * @nentry: number of entry in this table
 298 * @entries: Pointer to table entries
 299 */
 300struct dpu_qos_lut_tbl {
 301        u32 nentry;
 302        const struct dpu_qos_lut_entry *entries;
 303};
 304
 305/**
 306 * struct dpu_caps - define DPU capabilities
 307 * @max_mixer_width    max layer mixer line width support.
 308 * @max_mixer_blendstages max layer mixer blend stages or
 309 *                       supported z order
 310 * @qseed_type         qseed2 or qseed3 support.
 311 * @smart_dma_rev      Supported version of SmartDMA feature.
 312 * @ubwc_version       UBWC feature version (0x0 for not supported)
 313 * @has_src_split      source split feature status
 314 * @has_dim_layer      dim layer feature status
 315 * @has_idle_pc        indicate if idle power collapse feature is supported
 316 * @has_3d_merge       indicate if 3D merge is supported
 317 * @max_linewidth      max linewidth for sspp
 318 * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
 319 * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
 320 * @max_vdeci_exp      max vertical decimation supported (max is 2^value)
 321 */
 322struct dpu_caps {
 323        u32 max_mixer_width;
 324        u32 max_mixer_blendstages;
 325        u32 qseed_type;
 326        u32 smart_dma_rev;
 327        u32 ubwc_version;
 328        bool has_src_split;
 329        bool has_dim_layer;
 330        bool has_idle_pc;
 331        bool has_3d_merge;
 332        /* SSPP limits */
 333        u32 max_linewidth;
 334        u32 pixel_ram_size;
 335        u32 max_hdeci_exp;
 336        u32 max_vdeci_exp;
 337};
 338
 339/**
 340 * struct dpu_sspp_sub_blks : SSPP sub-blocks
 341 * common: Pointer to common configurations shared by sub blocks
 342 * @creq_vblank: creq priority during vertical blanking
 343 * @danger_vblank: danger priority during vertical blanking
 344 * @maxdwnscale: max downscale ratio supported(without DECIMATION)
 345 * @maxupscale:  maxupscale ratio supported
 346 * @smart_dma_priority: hw priority of rect1 of multirect pipe
 347 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
 348 * @qseed_ver: qseed version
 349 * @src_blk:
 350 * @scaler_blk:
 351 * @csc_blk:
 352 * @hsic:
 353 * @memcolor:
 354 * @pcc_blk:
 355 * @igc_blk:
 356 * @format_list: Pointer to list of supported formats
 357 * @num_formats: Number of supported formats
 358 * @virt_format_list: Pointer to list of supported formats for virtual planes
 359 * @virt_num_formats: Number of supported formats for virtual planes
 360 */
 361struct dpu_sspp_sub_blks {
 362        u32 creq_vblank;
 363        u32 danger_vblank;
 364        u32 maxdwnscale;
 365        u32 maxupscale;
 366        u32 smart_dma_priority;
 367        u32 max_per_pipe_bw;
 368        u32 qseed_ver;
 369        struct dpu_src_blk src_blk;
 370        struct dpu_scaler_blk scaler_blk;
 371        struct dpu_pp_blk csc_blk;
 372        struct dpu_pp_blk hsic_blk;
 373        struct dpu_pp_blk memcolor_blk;
 374        struct dpu_pp_blk pcc_blk;
 375        struct dpu_pp_blk igc_blk;
 376
 377        const u32 *format_list;
 378        u32 num_formats;
 379        const u32 *virt_format_list;
 380        u32 virt_num_formats;
 381};
 382
 383/**
 384 * struct dpu_lm_sub_blks:      information of mixer block
 385 * @maxwidth:               Max pixel width supported by this mixer
 386 * @maxblendstages:         Max number of blend-stages supported
 387 * @blendstage_base:        Blend-stage register base offset
 388 * @gc: gamma correction block
 389 */
 390struct dpu_lm_sub_blks {
 391        u32 maxwidth;
 392        u32 maxblendstages;
 393        u32 blendstage_base[MAX_BLOCKS];
 394        struct dpu_pp_blk gc;
 395};
 396
 397/**
 398 * struct dpu_dspp_sub_blks: Information of DSPP block
 399 * @gc : gamma correction block
 400 * @pcc: pixel color correction block
 401 */
 402struct dpu_dspp_sub_blks {
 403        struct dpu_pp_blk gc;
 404        struct dpu_pp_blk pcc;
 405};
 406
 407struct dpu_pingpong_sub_blks {
 408        struct dpu_pp_blk te;
 409        struct dpu_pp_blk te2;
 410        struct dpu_pp_blk dither;
 411};
 412
 413/**
 414 * dpu_clk_ctrl_type - Defines top level clock control signals
 415 */
 416enum dpu_clk_ctrl_type {
 417        DPU_CLK_CTRL_NONE,
 418        DPU_CLK_CTRL_VIG0,
 419        DPU_CLK_CTRL_VIG1,
 420        DPU_CLK_CTRL_VIG2,
 421        DPU_CLK_CTRL_VIG3,
 422        DPU_CLK_CTRL_VIG4,
 423        DPU_CLK_CTRL_RGB0,
 424        DPU_CLK_CTRL_RGB1,
 425        DPU_CLK_CTRL_RGB2,
 426        DPU_CLK_CTRL_RGB3,
 427        DPU_CLK_CTRL_DMA0,
 428        DPU_CLK_CTRL_DMA1,
 429        DPU_CLK_CTRL_CURSOR0,
 430        DPU_CLK_CTRL_CURSOR1,
 431        DPU_CLK_CTRL_INLINE_ROT0_SSPP,
 432        DPU_CLK_CTRL_REG_DMA,
 433        DPU_CLK_CTRL_MAX,
 434};
 435
 436/* struct dpu_clk_ctrl_reg : Clock control register
 437 * @reg_off:           register offset
 438 * @bit_off:           bit offset
 439 */
 440struct dpu_clk_ctrl_reg {
 441        u32 reg_off;
 442        u32 bit_off;
 443};
 444
 445/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
 446 * @id:                index identifying this block
 447 * @base:              register base offset to mdss
 448 * @features           bit mask identifying sub-blocks/features
 449 * @highest_bank_bit:  UBWC parameter
 450 * @ubwc_static:       ubwc static configuration
 451 * @ubwc_swizzle:      ubwc default swizzle setting
 452 * @clk_ctrls          clock control register definition
 453 */
 454struct dpu_mdp_cfg {
 455        DPU_HW_BLK_INFO;
 456        u32 highest_bank_bit;
 457        u32 ubwc_swizzle;
 458        struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
 459};
 460
 461/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
 462 * @id:                index identifying this block
 463 * @base:              register base offset to mdss
 464 * @features           bit mask identifying sub-blocks/features
 465 */
 466struct dpu_ctl_cfg {
 467        DPU_HW_BLK_INFO;
 468};
 469
 470/**
 471 * struct dpu_sspp_cfg - information of source pipes
 472 * @id:                index identifying this block
 473 * @base               register offset of this block
 474 * @features           bit mask identifying sub-blocks/features
 475 * @sblk:              SSPP sub-blocks information
 476 * @xin_id:            bus client identifier
 477 * @clk_ctrl           clock control identifier
 478 * @type               sspp type identifier
 479 */
 480struct dpu_sspp_cfg {
 481        DPU_HW_BLK_INFO;
 482        const struct dpu_sspp_sub_blks *sblk;
 483        u32 xin_id;
 484        enum dpu_clk_ctrl_type clk_ctrl;
 485        u32 type;
 486};
 487
 488/**
 489 * struct dpu_lm_cfg - information of layer mixer blocks
 490 * @id:                index identifying this block
 491 * @base               register offset of this block
 492 * @features           bit mask identifying sub-blocks/features
 493 * @sblk:              LM Sub-blocks information
 494 * @pingpong:          ID of connected PingPong, PINGPONG_MAX if unsupported
 495 * @lm_pair_mask:      Bitmask of LMs that can be controlled by same CTL
 496 */
 497struct dpu_lm_cfg {
 498        DPU_HW_BLK_INFO;
 499        const struct dpu_lm_sub_blks *sblk;
 500        u32 pingpong;
 501        u32 dspp;
 502        unsigned long lm_pair_mask;
 503};
 504
 505/**
 506 * struct dpu_dspp_cfg - information of DSPP blocks
 507 * @id                 enum identifying this block
 508 * @base               register offset of this block
 509 * @features           bit mask identifying sub-blocks/features
 510 *                     supported by this block
 511 * @sblk               sub-blocks information
 512 */
 513struct dpu_dspp_cfg  {
 514        DPU_HW_BLK_INFO;
 515        const struct dpu_dspp_sub_blks *sblk;
 516};
 517
 518/**
 519 * struct dpu_pingpong_cfg - information of PING-PONG blocks
 520 * @id                 enum identifying this block
 521 * @base               register offset of this block
 522 * @features           bit mask identifying sub-blocks/features
 523 * @sblk               sub-blocks information
 524 */
 525struct dpu_pingpong_cfg  {
 526        DPU_HW_BLK_INFO;
 527        const struct dpu_pingpong_sub_blks *sblk;
 528};
 529
 530/**
 531 * struct dpu_intf_cfg - information of timing engine blocks
 532 * @id                 enum identifying this block
 533 * @base               register offset of this block
 534 * @features           bit mask identifying sub-blocks/features
 535 * @type:              Interface type(DSI, DP, HDMI)
 536 * @controller_id:     Controller Instance ID in case of multiple of intf type
 537 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
 538 */
 539struct dpu_intf_cfg  {
 540        DPU_HW_BLK_INFO;
 541        u32 type;   /* interface type*/
 542        u32 controller_id;
 543        u32 prog_fetch_lines_worst_case;
 544};
 545
 546/**
 547 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
 548 * @pps                pixel per seconds
 549 * @ot_limit           OT limit to use up to specified pixel per second
 550 */
 551struct dpu_vbif_dynamic_ot_cfg {
 552        u64 pps;
 553        u32 ot_limit;
 554};
 555
 556/**
 557 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table
 558 * @count              length of cfg
 559 * @cfg                pointer to array of configuration settings with
 560 *                     ascending requirements
 561 */
 562struct dpu_vbif_dynamic_ot_tbl {
 563        u32 count;
 564        const struct dpu_vbif_dynamic_ot_cfg *cfg;
 565};
 566
 567/**
 568 * struct dpu_vbif_qos_tbl - QoS priority table
 569 * @npriority_lvl      num of priority level
 570 * @priority_lvl       pointer to array of priority level in ascending order
 571 */
 572struct dpu_vbif_qos_tbl {
 573        u32 npriority_lvl;
 574        const u32 *priority_lvl;
 575};
 576
 577/**
 578 * struct dpu_vbif_cfg - information of VBIF blocks
 579 * @id                 enum identifying this block
 580 * @base               register offset of this block
 581 * @features           bit mask identifying sub-blocks/features
 582 * @ot_rd_limit        default OT read limit
 583 * @ot_wr_limit        default OT write limit
 584 * @xin_halt_timeout   maximum time (in usec) for xin to halt
 585 * @dynamic_ot_rd_tbl  dynamic OT read configuration table
 586 * @dynamic_ot_wr_tbl  dynamic OT write configuration table
 587 * @qos_rt_tbl         real-time QoS priority table
 588 * @qos_nrt_tbl        non-real-time QoS priority table
 589 * @memtype_count      number of defined memtypes
 590 * @memtype            array of xin memtype definitions
 591 */
 592struct dpu_vbif_cfg {
 593        DPU_HW_BLK_INFO;
 594        u32 default_ot_rd_limit;
 595        u32 default_ot_wr_limit;
 596        u32 xin_halt_timeout;
 597        struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
 598        struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
 599        struct dpu_vbif_qos_tbl qos_rt_tbl;
 600        struct dpu_vbif_qos_tbl qos_nrt_tbl;
 601        u32 memtype_count;
 602        u32 memtype[MAX_XIN_COUNT];
 603};
 604/**
 605 * struct dpu_reg_dma_cfg - information of lut dma blocks
 606 * @id                 enum identifying this block
 607 * @base               register offset of this block
 608 * @features           bit mask identifying sub-blocks/features
 609 * @version            version of lutdma hw block
 610 * @trigger_sel_off    offset to trigger select registers of lutdma
 611 */
 612struct dpu_reg_dma_cfg {
 613        DPU_HW_BLK_INFO;
 614        u32 version;
 615        u32 trigger_sel_off;
 616        u32 xin_id;
 617        enum dpu_clk_ctrl_type clk_ctrl;
 618};
 619
 620/**
 621 * Define CDP use cases
 622 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases
 623 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
 624 */
 625enum {
 626        DPU_PERF_CDP_USAGE_RT,
 627        DPU_PERF_CDP_USAGE_NRT,
 628        DPU_PERF_CDP_USAGE_MAX
 629};
 630
 631/**
 632 * struct dpu_perf_cdp_cfg - define CDP use case configuration
 633 * @rd_enable: true if read pipe CDP is enabled
 634 * @wr_enable: true if write pipe CDP is enabled
 635 */
 636struct dpu_perf_cdp_cfg {
 637        bool rd_enable;
 638        bool wr_enable;
 639};
 640
 641/**
 642 * struct dpu_perf_cfg - performance control settings
 643 * @max_bw_low         low threshold of maximum bandwidth (kbps)
 644 * @max_bw_high        high threshold of maximum bandwidth (kbps)
 645 * @min_core_ib        minimum bandwidth for core (kbps)
 646 * @min_core_ib        minimum mnoc ib vote in kbps
 647 * @min_llcc_ib        minimum llcc ib vote in kbps
 648 * @min_dram_ib        minimum dram ib vote in kbps
 649 * @core_ib_ff         core instantaneous bandwidth fudge factor
 650 * @core_clk_ff        core clock fudge factor
 651 * @comp_ratio_rt      string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
 652 * @comp_ratio_nrt     string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
 653 * @undersized_prefill_lines   undersized prefill in lines
 654 * @xtra_prefill_lines         extra prefill latency in lines
 655 * @dest_scale_prefill_lines   destination scaler latency in lines
 656 * @macrotile_perfill_lines    macrotile latency in lines
 657 * @yuv_nv12_prefill_lines     yuv_nv12 latency in lines
 658 * @linear_prefill_lines       linear latency in lines
 659 * @downscaling_prefill_lines  downscaling latency in lines
 660 * @amortizable_theshold minimum y position for traffic shaping prefill
 661 * @min_prefill_lines  minimum pipeline latency in lines
 662 * @clk_inefficiency_factor DPU src clock inefficiency factor
 663 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor
 664 * @safe_lut_tbl: LUT tables for safe signals
 665 * @danger_lut_tbl: LUT tables for danger signals
 666 * @qos_lut_tbl: LUT tables for QoS signals
 667 * @cdp_cfg            cdp use case configurations
 668 */
 669struct dpu_perf_cfg {
 670        u32 max_bw_low;
 671        u32 max_bw_high;
 672        u32 min_core_ib;
 673        u32 min_llcc_ib;
 674        u32 min_dram_ib;
 675        const char *core_ib_ff;
 676        const char *core_clk_ff;
 677        const char *comp_ratio_rt;
 678        const char *comp_ratio_nrt;
 679        u32 undersized_prefill_lines;
 680        u32 xtra_prefill_lines;
 681        u32 dest_scale_prefill_lines;
 682        u32 macrotile_prefill_lines;
 683        u32 yuv_nv12_prefill_lines;
 684        u32 linear_prefill_lines;
 685        u32 downscaling_prefill_lines;
 686        u32 amortizable_threshold;
 687        u32 min_prefill_lines;
 688        u32 clk_inefficiency_factor;
 689        u32 bw_inefficiency_factor;
 690        u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
 691        u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
 692        struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
 693        struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
 694};
 695
 696/**
 697 * struct dpu_mdss_cfg - information of MDSS HW
 698 * This is the main catalog data structure representing
 699 * this HW version. Contains number of instances,
 700 * register offsets, capabilities of the all MDSS HW sub-blocks.
 701 *
 702 * @dma_formats        Supported formats for dma pipe
 703 * @cursor_formats     Supported formats for cursor pipe
 704 * @vig_formats        Supported formats for vig pipe
 705 * @mdss_irqs:         Bitmap with the irqs supported by the target
 706 */
 707struct dpu_mdss_cfg {
 708        u32 hwversion;
 709
 710        const struct dpu_caps *caps;
 711
 712        u32 mdp_count;
 713        const struct dpu_mdp_cfg *mdp;
 714
 715        u32 ctl_count;
 716        const struct dpu_ctl_cfg *ctl;
 717
 718        u32 sspp_count;
 719        const struct dpu_sspp_cfg *sspp;
 720
 721        u32 mixer_count;
 722        const struct dpu_lm_cfg *mixer;
 723
 724        u32 pingpong_count;
 725        const struct dpu_pingpong_cfg *pingpong;
 726
 727        u32 intf_count;
 728        const struct dpu_intf_cfg *intf;
 729
 730        u32 vbif_count;
 731        const struct dpu_vbif_cfg *vbif;
 732
 733        u32 reg_dma_count;
 734        struct dpu_reg_dma_cfg dma_cfg;
 735
 736        u32 ad_count;
 737
 738        u32 dspp_count;
 739        const struct dpu_dspp_cfg *dspp;
 740
 741        /* Add additional block data structures here */
 742
 743        struct dpu_perf_cfg perf;
 744        const struct dpu_format_extended *dma_formats;
 745        const struct dpu_format_extended *cursor_formats;
 746        const struct dpu_format_extended *vig_formats;
 747
 748        unsigned long mdss_irqs;
 749};
 750
 751struct dpu_mdss_hw_cfg_handler {
 752        u32 hw_rev;
 753        void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg);
 754};
 755
 756/*
 757 * Access Macros
 758 */
 759#define BLK_MDP(s) ((s)->mdp)
 760#define BLK_CTL(s) ((s)->ctl)
 761#define BLK_VIG(s) ((s)->vig)
 762#define BLK_RGB(s) ((s)->rgb)
 763#define BLK_DMA(s) ((s)->dma)
 764#define BLK_CURSOR(s) ((s)->cursor)
 765#define BLK_MIXER(s) ((s)->mixer)
 766#define BLK_PINGPONG(s) ((s)->pingpong)
 767#define BLK_INTF(s) ((s)->intf)
 768#define BLK_AD(s) ((s)->ad)
 769#define BLK_DSPP(s) ((s)->dspp)
 770
 771/**
 772 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
 773 * hardcoded target specific catalog information in config structure
 774 * @hw_rev:       caller needs provide the hardware revision.
 775 *
 776 * Return: dpu config structure
 777 */
 778struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
 779
 780/**
 781 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup
 782 * @dpu_cfg:      pointer returned from init function
 783 */
 784void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
 785
 786#endif /* _DPU_HW_CATALOG_H */
 787