LXR linux/drivers/gpu/drm/msm/disp/mdp

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2013 Red Hat
   4 * Author: Rob Clark <robdclark@gmail.com>
   5 */
   6
   7#ifndef __MDP_KMS_H__
   8#define __MDP_KMS_H__
   9
  10#include <linux/clk.h>
  11#include <linux/platform_device.h>
  12#include <linux/regulator/consumer.h>
  13
  14#include "msm_drv.h"
  15#include "msm_kms.h"
  16#include "mdp_common.xml.h"
  17
  18struct mdp_kms;
  19
  20struct mdp_kms_funcs {
  21        struct msm_kms_funcs base;
  22        void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask,
  23                uint32_t old_irqmask);
  24};
  25
  26struct mdp_kms {
  27        struct msm_kms base;
  28
  29        const struct mdp_kms_funcs *funcs;
  30
  31        /* irq handling: */
  32        bool in_irq;
  33        struct list_head irq_list;    /* list of mdp4_irq */
  34        uint32_t vblank_mask;         /* irq bits set for userspace vblank */
  35        uint32_t cur_irq_mask;        /* current irq mask */
  36};
  37#define to_mdp_kms(x) container_of(x, struct mdp_kms, base)
  38
  39static inline void mdp_kms_init(struct mdp_kms *mdp_kms,
  40                const struct mdp_kms_funcs *funcs)
  41{
  42        mdp_kms->funcs = funcs;
  43        INIT_LIST_HEAD(&mdp_kms->irq_list);
  44        msm_kms_init(&mdp_kms->base, &funcs->base);
  45}
  46
  47/*
  48 * irq helpers:
  49 */
  50
  51/* For transiently registering for different MDP irqs that various parts
  52 * of the KMS code need during setup/configuration.  These are not
  53 * necessarily the same as what drm_vblank_get/put() are requesting, and
  54 * the hysteresis in drm_vblank_put() is not necessarily desirable for
  55 * internal housekeeping related irq usage.
  56 */
  57struct mdp_irq {
  58        struct list_head node;
  59        uint32_t irqmask;
  60        bool registered;
  61        void (*irq)(struct mdp_irq *irq, uint32_t irqstatus);
  62};
  63
  64void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status);
  65void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable);
  66void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
  67void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
  68void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
  69void mdp_irq_update(struct mdp_kms *mdp_kms);
  70
  71/*
  72 * pixel format helpers:
  73 */
  74
  75struct mdp_format {
  76        struct msm_format base;
  77        enum mdp_bpc bpc_r, bpc_g, bpc_b;
  78        enum mdp_bpc_alpha bpc_a;
  79        uint8_t unpack[4];
  80        bool alpha_enable, unpack_tight;
  81        uint8_t cpp, unpack_count;
  82        enum mdp_fetch_type fetch_type;
  83        enum mdp_chroma_samp_type chroma_sample;
  84        bool is_yuv;
  85};
  86#define to_mdp_format(x) container_of(x, struct mdp_format, base)
  87#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
  88
  89uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
  90const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
  91
  92/* MDP capabilities */
  93#define MDP_CAP_SMP             BIT(0)  /* Shared Memory Pool                 */
  94#define MDP_CAP_DSC             BIT(1)  /* VESA Display Stream Compression    */
  95#define MDP_CAP_CDM             BIT(2)  /* Chroma Down Module (HDMI 2.0 YUV)  */
  96#define MDP_CAP_SRC_SPLIT       BIT(3)  /* Source Split of SSPPs */
  97
  98/* MDP pipe capabilities */
  99#define MDP_PIPE_CAP_HFLIP                      BIT(0)
 100#define MDP_PIPE_CAP_VFLIP                      BIT(1)
 101#define MDP_PIPE_CAP_SCALE                      BIT(2)
 102#define MDP_PIPE_CAP_CSC                        BIT(3)
 103#define MDP_PIPE_CAP_DECIMATION                 BIT(4)
 104#define MDP_PIPE_CAP_SW_PIX_EXT                 BIT(5)
 105#define MDP_PIPE_CAP_CURSOR                     BIT(6)
 106
 107/* MDP layer mixer caps */
 108#define MDP_LM_CAP_DISPLAY                      BIT(0)
 109#define MDP_LM_CAP_WB                           BIT(1)
 110#define MDP_LM_CAP_PAIR                         BIT(2)
 111
 112static inline bool pipe_supports_yuv(uint32_t pipe_caps)
 113{
 114        return (pipe_caps & MDP_PIPE_CAP_SCALE) &&
 115                (pipe_caps & MDP_PIPE_CAP_CSC);
 116}
 117
 118enum csc_type {
 119        CSC_RGB2RGB = 0,
 120        CSC_YUV2RGB,
 121        CSC_RGB2YUV,
 122        CSC_YUV2YUV,
 123        CSC_MAX
 124};
 125
 126struct csc_cfg {
 127        enum csc_type type;
 128        uint32_t matrix[9];
 129        uint32_t pre_bias[3];
 130        uint32_t post_bias[3];
 131        uint32_t pre_clamp[6];
 132        uint32_t post_clamp[6];
 133};
 134
 135struct csc_cfg *mdp_get_default_csc_cfg(enum csc_type);
 136
 137#endif /* __MDP_KMS_H__ */
 138