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7
8#include <linux/bitmap.h>
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/input.h>
14#include <linux/interrupt.h>
15#include <linux/jiffies.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22#include <linux/slab.h>
23#include <linux/wait.h>
24
25#include <linux/platform_data/at91_adc.h>
26
27#include <linux/iio/iio.h>
28#include <linux/iio/buffer.h>
29#include <linux/iio/trigger.h>
30#include <linux/iio/trigger_consumer.h>
31#include <linux/iio/triggered_buffer.h>
32#include <linux/pinctrl/consumer.h>
33
34
35#define AT91_ADC_CR 0x00
36#define AT91_ADC_SWRST (1 << 0)
37#define AT91_ADC_START (1 << 1)
38
39#define AT91_ADC_MR 0x04
40#define AT91_ADC_TSAMOD (3 << 0)
41#define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0)
42#define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0)
43#define AT91_ADC_TRGEN (1 << 0)
44#define AT91_ADC_TRGSEL (7 << 1)
45#define AT91_ADC_TRGSEL_TC0 (0 << 1)
46#define AT91_ADC_TRGSEL_TC1 (1 << 1)
47#define AT91_ADC_TRGSEL_TC2 (2 << 1)
48#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
49#define AT91_ADC_LOWRES (1 << 4)
50#define AT91_ADC_SLEEP (1 << 5)
51#define AT91_ADC_PENDET (1 << 6)
52#define AT91_ADC_PRESCAL_9260 (0x3f << 8)
53#define AT91_ADC_PRESCAL_9G45 (0xff << 8)
54#define AT91_ADC_PRESCAL_(x) ((x) << 8)
55#define AT91_ADC_STARTUP_9260 (0x1f << 16)
56#define AT91_ADC_STARTUP_9G45 (0x7f << 16)
57#define AT91_ADC_STARTUP_9X5 (0xf << 16)
58#define AT91_ADC_STARTUP_(x) ((x) << 16)
59#define AT91_ADC_SHTIM (0xf << 24)
60#define AT91_ADC_SHTIM_(x) ((x) << 24)
61#define AT91_ADC_PENDBC (0x0f << 28)
62#define AT91_ADC_PENDBC_(x) ((x) << 28)
63
64#define AT91_ADC_TSR 0x0C
65#define AT91_ADC_TSR_SHTIM (0xf << 24)
66#define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
67
68#define AT91_ADC_CHER 0x10
69#define AT91_ADC_CHDR 0x14
70#define AT91_ADC_CHSR 0x18
71#define AT91_ADC_CH(n) (1 << (n))
72
73#define AT91_ADC_SR 0x1C
74#define AT91_ADC_EOC(n) (1 << (n))
75#define AT91_ADC_OVRE(n) (1 << ((n) + 8))
76#define AT91_ADC_DRDY (1 << 16)
77#define AT91_ADC_GOVRE (1 << 17)
78#define AT91_ADC_ENDRX (1 << 18)
79#define AT91_ADC_RXFUFF (1 << 19)
80
81#define AT91_ADC_SR_9X5 0x30
82#define AT91_ADC_SR_DRDY_9X5 (1 << 24)
83
84#define AT91_ADC_LCDR 0x20
85#define AT91_ADC_LDATA (0x3ff)
86
87#define AT91_ADC_IER 0x24
88#define AT91_ADC_IDR 0x28
89#define AT91_ADC_IMR 0x2C
90#define AT91RL_ADC_IER_PEN (1 << 20)
91#define AT91RL_ADC_IER_NOPEN (1 << 21)
92#define AT91_ADC_IER_PEN (1 << 29)
93#define AT91_ADC_IER_NOPEN (1 << 30)
94#define AT91_ADC_IER_XRDY (1 << 20)
95#define AT91_ADC_IER_YRDY (1 << 21)
96#define AT91_ADC_IER_PRDY (1 << 22)
97#define AT91_ADC_ISR_PENS (1 << 31)
98
99#define AT91_ADC_CHR(n) (0x30 + ((n) * 4))
100#define AT91_ADC_DATA (0x3ff)
101
102#define AT91_ADC_CDR0_9X5 (0x50)
103
104#define AT91_ADC_ACR 0x94
105#define AT91_ADC_ACR_PENDETSENS (0x3 << 0)
106
107#define AT91_ADC_TSMR 0xB0
108#define AT91_ADC_TSMR_TSMODE (3 << 0)
109#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
110#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
111#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
112#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
113#define AT91_ADC_TSMR_TSAV (3 << 4)
114#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
115#define AT91_ADC_TSMR_SCTIM (0x0f << 16)
116#define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
117#define AT91_ADC_TSMR_PENDBC (0x0f << 28)
118#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
119#define AT91_ADC_TSMR_NOTSDMA (1 << 22)
120#define AT91_ADC_TSMR_PENDET_DIS (0 << 24)
121#define AT91_ADC_TSMR_PENDET_ENA (1 << 24)
122
123#define AT91_ADC_TSXPOSR 0xB4
124#define AT91_ADC_TSYPOSR 0xB8
125#define AT91_ADC_TSPRESSR 0xBC
126
127#define AT91_ADC_TRGR_9260 AT91_ADC_MR
128#define AT91_ADC_TRGR_9G45 0x08
129#define AT91_ADC_TRGR_9X5 0xC0
130
131
132#define AT91_ADC_TRGR_TRGPER (0xffff << 16)
133#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
134#define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
135#define AT91_ADC_TRGR_NONE (0 << 0)
136#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
137
138#define AT91_ADC_CHAN(st, ch) \
139 (st->registers->channel_base + (ch * 4))
140#define at91_adc_readl(st, reg) \
141 (readl_relaxed(st->reg_base + reg))
142#define at91_adc_writel(st, reg, val) \
143 (writel_relaxed(val, st->reg_base + reg))
144
145#define DRIVER_NAME "at91_adc"
146#define MAX_POS_BITS 12
147
148#define TOUCH_SAMPLE_PERIOD_US 2000
149#define TOUCH_PEN_DETECT_DEBOUNCE_US 200
150
151#define MAX_RLPOS_BITS 10
152#define TOUCH_SAMPLE_PERIOD_US_RL 10000
153#define TOUCH_SHTIM 0xa
154#define TOUCH_SCTIM_US 10
155
156
157
158
159
160
161
162
163
164
165
166struct at91_adc_reg_desc {
167 u8 channel_base;
168 u32 drdy_mask;
169 u8 status_register;
170 u8 trigger_register;
171 u32 mr_prescal_mask;
172 u32 mr_startup_mask;
173};
174
175struct at91_adc_caps {
176 bool has_ts;
177 bool has_tsmr;
178
179
180
181
182 u8 ts_filter_average;
183
184 u8 ts_pen_detect_sensitivity;
185
186
187 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
188
189 u8 num_channels;
190 struct at91_adc_reg_desc registers;
191};
192
193struct at91_adc_state {
194 struct clk *adc_clk;
195 u16 *buffer;
196 unsigned long channels_mask;
197 struct clk *clk;
198 bool done;
199 int irq;
200 u16 last_value;
201 int chnb;
202 struct mutex lock;
203 u8 num_channels;
204 void __iomem *reg_base;
205 struct at91_adc_reg_desc *registers;
206 u32 startup_time;
207 u8 sample_hold_time;
208 bool sleep_mode;
209 struct iio_trigger **trig;
210 struct at91_adc_trigger *trigger_list;
211 u32 trigger_number;
212 bool use_external;
213 u32 vref_mv;
214 u32 res;
215 bool low_res;
216 wait_queue_head_t wq_data_avail;
217 struct at91_adc_caps *caps;
218
219
220
221
222
223
224
225
226
227
228
229
230
231#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
232#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
233 enum atmel_adc_ts_type touchscreen_type;
234 struct input_dev *ts_input;
235
236 u16 ts_sample_period_val;
237 u32 ts_pressure_threshold;
238 u16 ts_pendbc;
239
240 bool ts_bufferedmeasure;
241 u32 ts_prev_absx;
242 u32 ts_prev_absy;
243};
244
245static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
246{
247 struct iio_poll_func *pf = p;
248 struct iio_dev *idev = pf->indio_dev;
249 struct at91_adc_state *st = iio_priv(idev);
250 struct iio_chan_spec const *chan;
251 int i, j = 0;
252
253 for (i = 0; i < idev->masklength; i++) {
254 if (!test_bit(i, idev->active_scan_mask))
255 continue;
256 chan = idev->channels + i;
257 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
258 j++;
259 }
260
261 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
262
263 iio_trigger_notify_done(idev->trig);
264
265
266 at91_adc_readl(st, AT91_ADC_LCDR);
267
268 enable_irq(st->irq);
269
270 return IRQ_HANDLED;
271}
272
273
274static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
275{
276 struct at91_adc_state *st = iio_priv(idev);
277
278 if (iio_buffer_enabled(idev)) {
279 disable_irq_nosync(irq);
280 iio_trigger_poll(idev->trig);
281 } else {
282 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
283
284 at91_adc_readl(st, AT91_ADC_LCDR);
285 st->done = true;
286 wake_up_interruptible(&st->wq_data_avail);
287 }
288}
289
290static int at91_ts_sample(struct iio_dev *idev)
291{
292 struct at91_adc_state *st = iio_priv(idev);
293 unsigned int xscale, yscale, reg, z1, z2;
294 unsigned int x, y, pres, xpos, ypos;
295 unsigned int rxp = 1;
296 unsigned int factor = 1000;
297
298 unsigned int xyz_mask_bits = st->res;
299 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
300
301
302
303 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
304 xpos = reg & xyz_mask;
305 x = (xpos << MAX_POS_BITS) - xpos;
306 xscale = (reg >> 16) & xyz_mask;
307 if (xscale == 0) {
308 dev_err(&idev->dev, "Error: xscale == 0!\n");
309 return -1;
310 }
311 x /= xscale;
312
313
314 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
315 ypos = reg & xyz_mask;
316 y = (ypos << MAX_POS_BITS) - ypos;
317 yscale = (reg >> 16) & xyz_mask;
318 if (yscale == 0) {
319 dev_err(&idev->dev, "Error: yscale == 0!\n");
320 return -1;
321 }
322 y /= yscale;
323
324
325 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
326 z1 = reg & xyz_mask;
327 z2 = (reg >> 16) & xyz_mask;
328
329 if (z1 != 0)
330 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
331 / factor;
332 else
333 pres = st->ts_pressure_threshold;
334
335 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
336 xpos, xscale, ypos, yscale, z1, z2, pres);
337
338 if (pres < st->ts_pressure_threshold) {
339 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
340 x, y, pres / factor);
341 input_report_abs(st->ts_input, ABS_X, x);
342 input_report_abs(st->ts_input, ABS_Y, y);
343 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
344 input_report_key(st->ts_input, BTN_TOUCH, 1);
345 input_sync(st->ts_input);
346 } else {
347 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
348 }
349
350 return 0;
351}
352
353static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
354{
355 struct iio_dev *idev = private;
356 struct at91_adc_state *st = iio_priv(idev);
357 u32 status = at91_adc_readl(st, st->registers->status_register);
358 unsigned int reg;
359
360 status &= at91_adc_readl(st, AT91_ADC_IMR);
361 if (status & GENMASK(st->num_channels - 1, 0))
362 handle_adc_eoc_trigger(irq, idev);
363
364 if (status & AT91RL_ADC_IER_PEN) {
365
366 reg = at91_adc_readl(st, AT91_ADC_MR);
367 reg &= ~AT91_ADC_PENDBC;
368 at91_adc_writel(st, AT91_ADC_MR, reg);
369
370 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
371 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
372 | AT91_ADC_EOC(3));
373
374 at91_adc_writel(st, st->registers->trigger_register,
375 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
376 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
377 } else if (status & AT91RL_ADC_IER_NOPEN) {
378 reg = at91_adc_readl(st, AT91_ADC_MR);
379 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
380 at91_adc_writel(st, AT91_ADC_MR, reg);
381 at91_adc_writel(st, st->registers->trigger_register,
382 AT91_ADC_TRGR_NONE);
383
384 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
385 | AT91_ADC_EOC(3));
386 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
387 st->ts_bufferedmeasure = false;
388 input_report_key(st->ts_input, BTN_TOUCH, 0);
389 input_sync(st->ts_input);
390 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
391
392 if (st->ts_bufferedmeasure) {
393
394
395
396
397
398 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
399 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
400 input_report_key(st->ts_input, BTN_TOUCH, 1);
401 input_sync(st->ts_input);
402 } else
403 st->ts_bufferedmeasure = true;
404
405
406 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
407 << MAX_RLPOS_BITS;
408 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
409
410 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
411 << MAX_RLPOS_BITS;
412 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
413 }
414
415 return IRQ_HANDLED;
416}
417
418static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
419{
420 struct iio_dev *idev = private;
421 struct at91_adc_state *st = iio_priv(idev);
422 u32 status = at91_adc_readl(st, st->registers->status_register);
423 const uint32_t ts_data_irq_mask =
424 AT91_ADC_IER_XRDY |
425 AT91_ADC_IER_YRDY |
426 AT91_ADC_IER_PRDY;
427
428 if (status & GENMASK(st->num_channels - 1, 0))
429 handle_adc_eoc_trigger(irq, idev);
430
431 if (status & AT91_ADC_IER_PEN) {
432 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
433 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
434 ts_data_irq_mask);
435
436 at91_adc_writel(st, st->registers->trigger_register,
437 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
438 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
439 } else if (status & AT91_ADC_IER_NOPEN) {
440 at91_adc_writel(st, st->registers->trigger_register, 0);
441 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
442 ts_data_irq_mask);
443 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
444
445 input_report_key(st->ts_input, BTN_TOUCH, 0);
446 input_sync(st->ts_input);
447 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
448
449
450 if (status & AT91_ADC_ISR_PENS) {
451
452 at91_ts_sample(idev);
453 } else {
454
455
456
457 at91_adc_readl(st, AT91_ADC_TSXPOSR);
458 at91_adc_readl(st, AT91_ADC_TSYPOSR);
459 at91_adc_readl(st, AT91_ADC_TSPRESSR);
460 }
461 }
462
463 return IRQ_HANDLED;
464}
465
466static int at91_adc_channel_init(struct iio_dev *idev)
467{
468 struct at91_adc_state *st = iio_priv(idev);
469 struct iio_chan_spec *chan_array, *timestamp;
470 int bit, idx = 0;
471 unsigned long rsvd_mask = 0;
472
473
474 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
475 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
476 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
477 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
478
479
480 st->channels_mask &= ~rsvd_mask;
481
482 idev->num_channels = bitmap_weight(&st->channels_mask,
483 st->num_channels) + 1;
484
485 chan_array = devm_kzalloc(&idev->dev,
486 ((idev->num_channels + 1) *
487 sizeof(struct iio_chan_spec)),
488 GFP_KERNEL);
489
490 if (!chan_array)
491 return -ENOMEM;
492
493 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
494 struct iio_chan_spec *chan = chan_array + idx;
495
496 chan->type = IIO_VOLTAGE;
497 chan->indexed = 1;
498 chan->channel = bit;
499 chan->scan_index = idx;
500 chan->scan_type.sign = 'u';
501 chan->scan_type.realbits = st->res;
502 chan->scan_type.storagebits = 16;
503 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
504 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
505 idx++;
506 }
507 timestamp = chan_array + idx;
508
509 timestamp->type = IIO_TIMESTAMP;
510 timestamp->channel = -1;
511 timestamp->scan_index = idx;
512 timestamp->scan_type.sign = 's';
513 timestamp->scan_type.realbits = 64;
514 timestamp->scan_type.storagebits = 64;
515
516 idev->channels = chan_array;
517 return idev->num_channels;
518}
519
520static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
521 struct at91_adc_trigger *triggers,
522 const char *trigger_name)
523{
524 struct at91_adc_state *st = iio_priv(idev);
525 int i;
526
527 for (i = 0; i < st->trigger_number; i++) {
528 char *name = kasprintf(GFP_KERNEL,
529 "%s-dev%d-%s",
530 idev->name,
531 idev->id,
532 triggers[i].name);
533 if (!name)
534 return -ENOMEM;
535
536 if (strcmp(trigger_name, name) == 0) {
537 kfree(name);
538 if (triggers[i].value == 0)
539 return -EINVAL;
540 return triggers[i].value;
541 }
542
543 kfree(name);
544 }
545
546 return -EINVAL;
547}
548
549static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
550{
551 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
552 struct at91_adc_state *st = iio_priv(idev);
553 struct at91_adc_reg_desc *reg = st->registers;
554 u32 status = at91_adc_readl(st, reg->trigger_register);
555 int value;
556 u8 bit;
557
558 value = at91_adc_get_trigger_value_by_name(idev,
559 st->trigger_list,
560 idev->trig->name);
561 if (value < 0)
562 return value;
563
564 if (state) {
565 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
566 if (st->buffer == NULL)
567 return -ENOMEM;
568
569 at91_adc_writel(st, reg->trigger_register,
570 status | value);
571
572 for_each_set_bit(bit, idev->active_scan_mask,
573 st->num_channels) {
574 struct iio_chan_spec const *chan = idev->channels + bit;
575 at91_adc_writel(st, AT91_ADC_CHER,
576 AT91_ADC_CH(chan->channel));
577 }
578
579 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
580
581 } else {
582 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
583
584 at91_adc_writel(st, reg->trigger_register,
585 status & ~value);
586
587 for_each_set_bit(bit, idev->active_scan_mask,
588 st->num_channels) {
589 struct iio_chan_spec const *chan = idev->channels + bit;
590 at91_adc_writel(st, AT91_ADC_CHDR,
591 AT91_ADC_CH(chan->channel));
592 }
593 kfree(st->buffer);
594 }
595
596 return 0;
597}
598
599static const struct iio_trigger_ops at91_adc_trigger_ops = {
600 .set_trigger_state = &at91_adc_configure_trigger,
601};
602
603static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
604 struct at91_adc_trigger *trigger)
605{
606 struct iio_trigger *trig;
607 int ret;
608
609 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
610 idev->id, trigger->name);
611 if (trig == NULL)
612 return NULL;
613
614 trig->dev.parent = idev->dev.parent;
615 iio_trigger_set_drvdata(trig, idev);
616 trig->ops = &at91_adc_trigger_ops;
617
618 ret = iio_trigger_register(trig);
619 if (ret)
620 return NULL;
621
622 return trig;
623}
624
625static int at91_adc_trigger_init(struct iio_dev *idev)
626{
627 struct at91_adc_state *st = iio_priv(idev);
628 int i, ret;
629
630 st->trig = devm_kcalloc(&idev->dev,
631 st->trigger_number, sizeof(*st->trig),
632 GFP_KERNEL);
633
634 if (st->trig == NULL) {
635 ret = -ENOMEM;
636 goto error_ret;
637 }
638
639 for (i = 0; i < st->trigger_number; i++) {
640 if (st->trigger_list[i].is_external && !(st->use_external))
641 continue;
642
643 st->trig[i] = at91_adc_allocate_trigger(idev,
644 st->trigger_list + i);
645 if (st->trig[i] == NULL) {
646 dev_err(&idev->dev,
647 "Could not allocate trigger %d\n", i);
648 ret = -ENOMEM;
649 goto error_trigger;
650 }
651 }
652
653 return 0;
654
655error_trigger:
656 for (i--; i >= 0; i--) {
657 iio_trigger_unregister(st->trig[i]);
658 iio_trigger_free(st->trig[i]);
659 }
660error_ret:
661 return ret;
662}
663
664static void at91_adc_trigger_remove(struct iio_dev *idev)
665{
666 struct at91_adc_state *st = iio_priv(idev);
667 int i;
668
669 for (i = 0; i < st->trigger_number; i++) {
670 iio_trigger_unregister(st->trig[i]);
671 iio_trigger_free(st->trig[i]);
672 }
673}
674
675static int at91_adc_buffer_init(struct iio_dev *idev)
676{
677 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
678 &at91_adc_trigger_handler, NULL);
679}
680
681static void at91_adc_buffer_remove(struct iio_dev *idev)
682{
683 iio_triggered_buffer_cleanup(idev);
684}
685
686static int at91_adc_read_raw(struct iio_dev *idev,
687 struct iio_chan_spec const *chan,
688 int *val, int *val2, long mask)
689{
690 struct at91_adc_state *st = iio_priv(idev);
691 int ret;
692
693 switch (mask) {
694 case IIO_CHAN_INFO_RAW:
695 mutex_lock(&st->lock);
696
697 st->chnb = chan->channel;
698 at91_adc_writel(st, AT91_ADC_CHER,
699 AT91_ADC_CH(chan->channel));
700 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
701 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
702
703 ret = wait_event_interruptible_timeout(st->wq_data_avail,
704 st->done,
705 msecs_to_jiffies(1000));
706
707
708
709
710 at91_adc_writel(st, AT91_ADC_CHDR,
711 AT91_ADC_CH(chan->channel));
712 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
713
714 if (ret > 0) {
715
716 *val = st->last_value;
717 st->last_value = 0;
718 st->done = false;
719 ret = IIO_VAL_INT;
720 } else if (ret == 0) {
721
722 dev_err(&idev->dev, "ADC Channel %d timeout.\n",
723 chan->channel);
724 ret = -ETIMEDOUT;
725 }
726
727 mutex_unlock(&st->lock);
728 return ret;
729
730 case IIO_CHAN_INFO_SCALE:
731 *val = st->vref_mv;
732 *val2 = chan->scan_type.realbits;
733 return IIO_VAL_FRACTIONAL_LOG2;
734 default:
735 break;
736 }
737 return -EINVAL;
738}
739
740static int at91_adc_of_get_resolution(struct iio_dev *idev,
741 struct platform_device *pdev)
742{
743 struct at91_adc_state *st = iio_priv(idev);
744 struct device_node *np = pdev->dev.of_node;
745 int count, i, ret = 0;
746 char *res_name, *s;
747 u32 *resolutions;
748
749 count = of_property_count_strings(np, "atmel,adc-res-names");
750 if (count < 2) {
751 dev_err(&idev->dev, "You must specified at least two resolution names for "
752 "adc-res-names property in the DT\n");
753 return count;
754 }
755
756 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
757 if (!resolutions)
758 return -ENOMEM;
759
760 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
761 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
762 ret = -ENODEV;
763 goto ret;
764 }
765
766 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
767 res_name = "highres";
768
769 for (i = 0; i < count; i++) {
770 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
771 continue;
772
773 if (strcmp(res_name, s))
774 continue;
775
776 st->res = resolutions[i];
777 if (!strcmp(res_name, "lowres"))
778 st->low_res = true;
779 else
780 st->low_res = false;
781
782 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
783 goto ret;
784 }
785
786 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
787
788ret:
789 kfree(resolutions);
790 return ret;
791}
792
793static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
794{
795
796
797
798
799
800
801 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
802}
803
804static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
805{
806
807
808
809
810 static const int startup_lookup[] = {
811 0, 8, 16, 24,
812 64, 80, 96, 112,
813 512, 576, 640, 704,
814 768, 832, 896, 960
815 };
816 int i, size = ARRAY_SIZE(startup_lookup);
817 unsigned int ticks;
818
819 ticks = startup_time * adc_clk_khz / 1000;
820 for (i = 0; i < size; i++)
821 if (ticks < startup_lookup[i])
822 break;
823
824 ticks = i;
825 if (ticks == size)
826
827 ticks = size - 1;
828
829 return ticks;
830}
831
832static const struct of_device_id at91_adc_dt_ids[];
833
834static int at91_adc_probe_dt_ts(struct device_node *node,
835 struct at91_adc_state *st, struct device *dev)
836{
837 int ret;
838 u32 prop;
839
840 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
841 if (ret) {
842 dev_info(dev, "ADC Touch screen is disabled.\n");
843 return 0;
844 }
845
846 switch (prop) {
847 case 4:
848 case 5:
849 st->touchscreen_type = prop;
850 break;
851 default:
852 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
853 return -EINVAL;
854 }
855
856 if (!st->caps->has_tsmr)
857 return 0;
858 prop = 0;
859 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
860 st->ts_pressure_threshold = prop;
861 if (st->ts_pressure_threshold) {
862 return 0;
863 } else {
864 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
865 return -EINVAL;
866 }
867}
868
869static int at91_adc_probe_dt(struct iio_dev *idev,
870 struct platform_device *pdev)
871{
872 struct at91_adc_state *st = iio_priv(idev);
873 struct device_node *node = pdev->dev.of_node;
874 struct device_node *trig_node;
875 int i = 0, ret;
876 u32 prop;
877
878 if (!node)
879 return -EINVAL;
880
881 st->caps = (struct at91_adc_caps *)
882 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
883
884 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
885
886 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
887 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
888 ret = -EINVAL;
889 goto error_ret;
890 }
891 st->channels_mask = prop;
892
893 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
894
895 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
896 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
897 ret = -EINVAL;
898 goto error_ret;
899 }
900 st->startup_time = prop;
901
902 prop = 0;
903 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
904 st->sample_hold_time = prop;
905
906 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
907 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
908 ret = -EINVAL;
909 goto error_ret;
910 }
911 st->vref_mv = prop;
912
913 ret = at91_adc_of_get_resolution(idev, pdev);
914 if (ret)
915 goto error_ret;
916
917 st->registers = &st->caps->registers;
918 st->num_channels = st->caps->num_channels;
919 st->trigger_number = of_get_child_count(node);
920 st->trigger_list = devm_kcalloc(&idev->dev,
921 st->trigger_number,
922 sizeof(struct at91_adc_trigger),
923 GFP_KERNEL);
924 if (!st->trigger_list) {
925 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
926 ret = -ENOMEM;
927 goto error_ret;
928 }
929
930 for_each_child_of_node(node, trig_node) {
931 struct at91_adc_trigger *trig = st->trigger_list + i;
932 const char *name;
933
934 if (of_property_read_string(trig_node, "trigger-name", &name)) {
935 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
936 ret = -EINVAL;
937 goto error_ret;
938 }
939 trig->name = name;
940
941 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
942 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
943 ret = -EINVAL;
944 goto error_ret;
945 }
946 trig->value = prop;
947 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
948 i++;
949 }
950
951
952 if (st->caps->has_ts)
953 return at91_adc_probe_dt_ts(node, st, &idev->dev);
954 else
955 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
956
957 return 0;
958
959error_ret:
960 return ret;
961}
962
963static int at91_adc_probe_pdata(struct at91_adc_state *st,
964 struct platform_device *pdev)
965{
966 struct at91_adc_data *pdata = pdev->dev.platform_data;
967
968 if (!pdata)
969 return -EINVAL;
970
971 st->caps = (struct at91_adc_caps *)
972 platform_get_device_id(pdev)->driver_data;
973
974 st->use_external = pdata->use_external_triggers;
975 st->vref_mv = pdata->vref;
976 st->channels_mask = pdata->channels_used;
977 st->num_channels = st->caps->num_channels;
978 st->startup_time = pdata->startup_time;
979 st->trigger_number = pdata->trigger_number;
980 st->trigger_list = pdata->trigger_list;
981 st->registers = &st->caps->registers;
982 st->touchscreen_type = pdata->touchscreen_type;
983
984 return 0;
985}
986
987static const struct iio_info at91_adc_info = {
988 .read_raw = &at91_adc_read_raw,
989};
990
991
992static int atmel_ts_open(struct input_dev *dev)
993{
994 struct at91_adc_state *st = input_get_drvdata(dev);
995
996 if (st->caps->has_tsmr)
997 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
998 else
999 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
1000 return 0;
1001}
1002
1003static void atmel_ts_close(struct input_dev *dev)
1004{
1005 struct at91_adc_state *st = input_get_drvdata(dev);
1006
1007 if (st->caps->has_tsmr)
1008 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1009 else
1010 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1011}
1012
1013static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz)
1014{
1015 struct at91_adc_state *st = iio_priv(idev);
1016 u32 reg = 0;
1017 u32 tssctim = 0;
1018 int i = 0;
1019
1020
1021
1022
1023
1024 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1025 1000, 1);
1026
1027 while (st->ts_pendbc >> ++i)
1028 ;
1029 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1030 st->ts_pendbc = i;
1031 else
1032 st->ts_pendbc = i - 1;
1033
1034 if (!st->caps->has_tsmr) {
1035 reg = at91_adc_readl(st, AT91_ADC_MR);
1036 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1037
1038 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1039 at91_adc_writel(st, AT91_ADC_MR, reg);
1040
1041 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1042 at91_adc_writel(st, AT91_ADC_TSR, reg);
1043
1044 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1045 adc_clk_khz / 1000) - 1, 1);
1046
1047 return 0;
1048 }
1049
1050
1051
1052
1053
1054 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1055 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1056 adc_clk_khz, tssctim);
1057
1058 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1059 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1060 else
1061 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1062
1063 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1064 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1065 & AT91_ADC_TSMR_TSAV;
1066 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1067 reg |= AT91_ADC_TSMR_NOTSDMA;
1068 reg |= AT91_ADC_TSMR_PENDET_ENA;
1069 reg |= 0x03 << 8;
1070
1071 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1072
1073
1074
1075
1076
1077
1078 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1079 & AT91_ADC_ACR_PENDETSENS);
1080
1081
1082 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1083 adc_clk_khz / 1000) - 1, 1);
1084
1085 return 0;
1086}
1087
1088static int at91_ts_register(struct iio_dev *idev,
1089 struct platform_device *pdev)
1090{
1091 struct at91_adc_state *st = iio_priv(idev);
1092 struct input_dev *input;
1093 int ret;
1094
1095 input = input_allocate_device();
1096 if (!input) {
1097 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1098 return -ENOMEM;
1099 }
1100
1101 input->name = DRIVER_NAME;
1102 input->id.bustype = BUS_HOST;
1103 input->dev.parent = &pdev->dev;
1104 input->open = atmel_ts_open;
1105 input->close = atmel_ts_close;
1106
1107 __set_bit(EV_ABS, input->evbit);
1108 __set_bit(EV_KEY, input->evbit);
1109 __set_bit(BTN_TOUCH, input->keybit);
1110 if (st->caps->has_tsmr) {
1111 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1112 0, 0);
1113 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1114 0, 0);
1115 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1116 } else {
1117 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1118 dev_err(&pdev->dev,
1119 "This touchscreen controller only support 4 wires\n");
1120 ret = -EINVAL;
1121 goto err;
1122 }
1123
1124 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1125 0, 0);
1126 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1127 0, 0);
1128 }
1129
1130 st->ts_input = input;
1131 input_set_drvdata(input, st);
1132
1133 ret = input_register_device(input);
1134 if (ret)
1135 goto err;
1136
1137 return ret;
1138
1139err:
1140 input_free_device(st->ts_input);
1141 return ret;
1142}
1143
1144static void at91_ts_unregister(struct at91_adc_state *st)
1145{
1146 input_unregister_device(st->ts_input);
1147}
1148
1149static int at91_adc_probe(struct platform_device *pdev)
1150{
1151 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1152 int ret;
1153 struct iio_dev *idev;
1154 struct at91_adc_state *st;
1155 u32 reg;
1156
1157 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1158 if (!idev)
1159 return -ENOMEM;
1160
1161 st = iio_priv(idev);
1162
1163 if (pdev->dev.of_node)
1164 ret = at91_adc_probe_dt(idev, pdev);
1165 else
1166 ret = at91_adc_probe_pdata(st, pdev);
1167
1168 if (ret) {
1169 dev_err(&pdev->dev, "No platform data available.\n");
1170 return -EINVAL;
1171 }
1172
1173 platform_set_drvdata(pdev, idev);
1174
1175 idev->name = dev_name(&pdev->dev);
1176 idev->modes = INDIO_DIRECT_MODE;
1177 idev->info = &at91_adc_info;
1178
1179 st->irq = platform_get_irq(pdev, 0);
1180 if (st->irq < 0)
1181 return -ENODEV;
1182
1183 st->reg_base = devm_platform_ioremap_resource(pdev, 0);
1184 if (IS_ERR(st->reg_base))
1185 return PTR_ERR(st->reg_base);
1186
1187
1188
1189
1190
1191 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1192 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1193
1194 if (st->caps->has_tsmr)
1195 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1196 pdev->dev.driver->name, idev);
1197 else
1198 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1199 pdev->dev.driver->name, idev);
1200 if (ret) {
1201 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1202 return ret;
1203 }
1204
1205 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1206 if (IS_ERR(st->clk)) {
1207 dev_err(&pdev->dev, "Failed to get the clock.\n");
1208 ret = PTR_ERR(st->clk);
1209 goto error_free_irq;
1210 }
1211
1212 ret = clk_prepare_enable(st->clk);
1213 if (ret) {
1214 dev_err(&pdev->dev,
1215 "Could not prepare or enable the clock.\n");
1216 goto error_free_irq;
1217 }
1218
1219 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1220 if (IS_ERR(st->adc_clk)) {
1221 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1222 ret = PTR_ERR(st->adc_clk);
1223 goto error_disable_clk;
1224 }
1225
1226 ret = clk_prepare_enable(st->adc_clk);
1227 if (ret) {
1228 dev_err(&pdev->dev,
1229 "Could not prepare or enable the ADC clock.\n");
1230 goto error_disable_clk;
1231 }
1232
1233
1234
1235
1236
1237
1238 mstrclk = clk_get_rate(st->clk);
1239 adc_clk = clk_get_rate(st->adc_clk);
1240 adc_clk_khz = adc_clk / 1000;
1241
1242 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1243 mstrclk, adc_clk);
1244
1245 prsc = (mstrclk / (2 * adc_clk)) - 1;
1246
1247 if (!st->startup_time) {
1248 dev_err(&pdev->dev, "No startup time available.\n");
1249 ret = -EINVAL;
1250 goto error_disable_adc_clk;
1251 }
1252 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1253
1254
1255
1256
1257
1258
1259 if (st->sample_hold_time > 0)
1260 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1261 - 1, 1);
1262 else
1263 shtim = 0;
1264
1265 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1266 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1267 if (st->low_res)
1268 reg |= AT91_ADC_LOWRES;
1269 if (st->sleep_mode)
1270 reg |= AT91_ADC_SLEEP;
1271 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1272 at91_adc_writel(st, AT91_ADC_MR, reg);
1273
1274
1275 ret = at91_adc_channel_init(idev);
1276 if (ret < 0) {
1277 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1278 goto error_disable_adc_clk;
1279 }
1280
1281 init_waitqueue_head(&st->wq_data_avail);
1282 mutex_init(&st->lock);
1283
1284
1285
1286
1287
1288
1289 if (!st->touchscreen_type) {
1290 ret = at91_adc_buffer_init(idev);
1291 if (ret < 0) {
1292 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1293 goto error_disable_adc_clk;
1294 }
1295
1296 ret = at91_adc_trigger_init(idev);
1297 if (ret < 0) {
1298 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1299 at91_adc_buffer_remove(idev);
1300 goto error_disable_adc_clk;
1301 }
1302 } else {
1303 ret = at91_ts_register(idev, pdev);
1304 if (ret)
1305 goto error_disable_adc_clk;
1306
1307 at91_ts_hw_init(idev, adc_clk_khz);
1308 }
1309
1310 ret = iio_device_register(idev);
1311 if (ret < 0) {
1312 dev_err(&pdev->dev, "Couldn't register the device.\n");
1313 goto error_iio_device_register;
1314 }
1315
1316 return 0;
1317
1318error_iio_device_register:
1319 if (!st->touchscreen_type) {
1320 at91_adc_trigger_remove(idev);
1321 at91_adc_buffer_remove(idev);
1322 } else {
1323 at91_ts_unregister(st);
1324 }
1325error_disable_adc_clk:
1326 clk_disable_unprepare(st->adc_clk);
1327error_disable_clk:
1328 clk_disable_unprepare(st->clk);
1329error_free_irq:
1330 free_irq(st->irq, idev);
1331 return ret;
1332}
1333
1334static int at91_adc_remove(struct platform_device *pdev)
1335{
1336 struct iio_dev *idev = platform_get_drvdata(pdev);
1337 struct at91_adc_state *st = iio_priv(idev);
1338
1339 iio_device_unregister(idev);
1340 if (!st->touchscreen_type) {
1341 at91_adc_trigger_remove(idev);
1342 at91_adc_buffer_remove(idev);
1343 } else {
1344 at91_ts_unregister(st);
1345 }
1346 clk_disable_unprepare(st->adc_clk);
1347 clk_disable_unprepare(st->clk);
1348 free_irq(st->irq, idev);
1349
1350 return 0;
1351}
1352
1353#ifdef CONFIG_PM_SLEEP
1354static int at91_adc_suspend(struct device *dev)
1355{
1356 struct iio_dev *idev = dev_get_drvdata(dev);
1357 struct at91_adc_state *st = iio_priv(idev);
1358
1359 pinctrl_pm_select_sleep_state(dev);
1360 clk_disable_unprepare(st->clk);
1361
1362 return 0;
1363}
1364
1365static int at91_adc_resume(struct device *dev)
1366{
1367 struct iio_dev *idev = dev_get_drvdata(dev);
1368 struct at91_adc_state *st = iio_priv(idev);
1369
1370 clk_prepare_enable(st->clk);
1371 pinctrl_pm_select_default_state(dev);
1372
1373 return 0;
1374}
1375#endif
1376
1377static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1378
1379static struct at91_adc_caps at91sam9260_caps = {
1380 .calc_startup_ticks = calc_startup_ticks_9260,
1381 .num_channels = 4,
1382 .registers = {
1383 .channel_base = AT91_ADC_CHR(0),
1384 .drdy_mask = AT91_ADC_DRDY,
1385 .status_register = AT91_ADC_SR,
1386 .trigger_register = AT91_ADC_TRGR_9260,
1387 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1388 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1389 },
1390};
1391
1392static struct at91_adc_caps at91sam9rl_caps = {
1393 .has_ts = true,
1394 .calc_startup_ticks = calc_startup_ticks_9260,
1395 .num_channels = 6,
1396 .registers = {
1397 .channel_base = AT91_ADC_CHR(0),
1398 .drdy_mask = AT91_ADC_DRDY,
1399 .status_register = AT91_ADC_SR,
1400 .trigger_register = AT91_ADC_TRGR_9G45,
1401 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1402 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1403 },
1404};
1405
1406static struct at91_adc_caps at91sam9g45_caps = {
1407 .has_ts = true,
1408 .calc_startup_ticks = calc_startup_ticks_9260,
1409 .num_channels = 8,
1410 .registers = {
1411 .channel_base = AT91_ADC_CHR(0),
1412 .drdy_mask = AT91_ADC_DRDY,
1413 .status_register = AT91_ADC_SR,
1414 .trigger_register = AT91_ADC_TRGR_9G45,
1415 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1416 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1417 },
1418};
1419
1420static struct at91_adc_caps at91sam9x5_caps = {
1421 .has_ts = true,
1422 .has_tsmr = true,
1423 .ts_filter_average = 3,
1424 .ts_pen_detect_sensitivity = 2,
1425 .calc_startup_ticks = calc_startup_ticks_9x5,
1426 .num_channels = 12,
1427 .registers = {
1428 .channel_base = AT91_ADC_CDR0_9X5,
1429 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1430 .status_register = AT91_ADC_SR_9X5,
1431 .trigger_register = AT91_ADC_TRGR_9X5,
1432
1433 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1434 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1435 },
1436};
1437
1438static const struct of_device_id at91_adc_dt_ids[] = {
1439 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1440 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1441 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1442 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1443 {},
1444};
1445MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1446
1447static const struct platform_device_id at91_adc_ids[] = {
1448 {
1449 .name = "at91sam9260-adc",
1450 .driver_data = (unsigned long)&at91sam9260_caps,
1451 }, {
1452 .name = "at91sam9rl-adc",
1453 .driver_data = (unsigned long)&at91sam9rl_caps,
1454 }, {
1455 .name = "at91sam9g45-adc",
1456 .driver_data = (unsigned long)&at91sam9g45_caps,
1457 }, {
1458 .name = "at91sam9x5-adc",
1459 .driver_data = (unsigned long)&at91sam9x5_caps,
1460 }, {
1461
1462 }
1463};
1464MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1465
1466static struct platform_driver at91_adc_driver = {
1467 .probe = at91_adc_probe,
1468 .remove = at91_adc_remove,
1469 .id_table = at91_adc_ids,
1470 .driver = {
1471 .name = DRIVER_NAME,
1472 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1473 .pm = &at91_adc_pm_ops,
1474 },
1475};
1476
1477module_platform_driver(at91_adc_driver);
1478
1479MODULE_LICENSE("GPL");
1480MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1481MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1482
