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9#include <linux/bitops.h>
10#include <linux/delay.h>
11#include <linux/iio/iio.h>
12#include <linux/module.h>
13#include <linux/mutex.h>
14#include <linux/of.h>
15#include <linux/regulator/consumer.h>
16#include <linux/gpio/consumer.h>
17#include <linux/gpio/driver.h>
18#include <linux/property.h>
19
20#include <dt-bindings/iio/adi,ad5592r.h>
21
22#include "ad5592r-base.h"
23
24static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
25{
26 struct ad5592r_state *st = gpiochip_get_data(chip);
27 int ret = 0;
28 u8 val;
29
30 mutex_lock(&st->gpio_lock);
31
32 if (st->gpio_out & BIT(offset))
33 val = st->gpio_val;
34 else
35 ret = st->ops->gpio_read(st, &val);
36
37 mutex_unlock(&st->gpio_lock);
38
39 if (ret < 0)
40 return ret;
41
42 return !!(val & BIT(offset));
43}
44
45static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
46{
47 struct ad5592r_state *st = gpiochip_get_data(chip);
48
49 mutex_lock(&st->gpio_lock);
50
51 if (value)
52 st->gpio_val |= BIT(offset);
53 else
54 st->gpio_val &= ~BIT(offset);
55
56 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
57
58 mutex_unlock(&st->gpio_lock);
59}
60
61static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
62{
63 struct ad5592r_state *st = gpiochip_get_data(chip);
64 int ret;
65
66 mutex_lock(&st->gpio_lock);
67
68 st->gpio_out &= ~BIT(offset);
69 st->gpio_in |= BIT(offset);
70
71 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
72 if (ret < 0)
73 goto err_unlock;
74
75 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
76
77err_unlock:
78 mutex_unlock(&st->gpio_lock);
79
80 return ret;
81}
82
83static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
85{
86 struct ad5592r_state *st = gpiochip_get_data(chip);
87 int ret;
88
89 mutex_lock(&st->gpio_lock);
90
91 if (value)
92 st->gpio_val |= BIT(offset);
93 else
94 st->gpio_val &= ~BIT(offset);
95
96 st->gpio_in &= ~BIT(offset);
97 st->gpio_out |= BIT(offset);
98
99 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
100 if (ret < 0)
101 goto err_unlock;
102
103 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
104 if (ret < 0)
105 goto err_unlock;
106
107 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
108
109err_unlock:
110 mutex_unlock(&st->gpio_lock);
111
112 return ret;
113}
114
115static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
116{
117 struct ad5592r_state *st = gpiochip_get_data(chip);
118
119 if (!(st->gpio_map & BIT(offset))) {
120 dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
121 offset);
122 return -ENODEV;
123 }
124
125 return 0;
126}
127
128static int ad5592r_gpio_init(struct ad5592r_state *st)
129{
130 if (!st->gpio_map)
131 return 0;
132
133 st->gpiochip.label = dev_name(st->dev);
134 st->gpiochip.base = -1;
135 st->gpiochip.ngpio = 8;
136 st->gpiochip.parent = st->dev;
137 st->gpiochip.can_sleep = true;
138 st->gpiochip.direction_input = ad5592r_gpio_direction_input;
139 st->gpiochip.direction_output = ad5592r_gpio_direction_output;
140 st->gpiochip.get = ad5592r_gpio_get;
141 st->gpiochip.set = ad5592r_gpio_set;
142 st->gpiochip.request = ad5592r_gpio_request;
143 st->gpiochip.owner = THIS_MODULE;
144
145 mutex_init(&st->gpio_lock);
146
147 return gpiochip_add_data(&st->gpiochip, st);
148}
149
150static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
151{
152 if (st->gpio_map)
153 gpiochip_remove(&st->gpiochip);
154}
155
156static int ad5592r_reset(struct ad5592r_state *st)
157{
158 struct gpio_desc *gpio;
159
160 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
161 if (IS_ERR(gpio))
162 return PTR_ERR(gpio);
163
164 if (gpio) {
165 udelay(1);
166 gpiod_set_value(gpio, 1);
167 } else {
168 mutex_lock(&st->lock);
169
170 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
171 mutex_unlock(&st->lock);
172 }
173
174 udelay(250);
175
176 return 0;
177}
178
179static int ad5592r_get_vref(struct ad5592r_state *st)
180{
181 int ret;
182
183 if (st->reg) {
184 ret = regulator_get_voltage(st->reg);
185 if (ret < 0)
186 return ret;
187
188 return ret / 1000;
189 } else {
190 return 2500;
191 }
192}
193
194static int ad5592r_set_channel_modes(struct ad5592r_state *st)
195{
196 const struct ad5592r_rw_ops *ops = st->ops;
197 int ret;
198 unsigned i;
199 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
200 u16 read_back;
201
202 for (i = 0; i < st->num_channels; i++) {
203 switch (st->channel_modes[i]) {
204 case CH_MODE_DAC:
205 dac |= BIT(i);
206 break;
207
208 case CH_MODE_ADC:
209 adc |= BIT(i);
210 break;
211
212 case CH_MODE_DAC_AND_ADC:
213 dac |= BIT(i);
214 adc |= BIT(i);
215 break;
216
217 case CH_MODE_GPIO:
218 st->gpio_map |= BIT(i);
219 st->gpio_in |= BIT(i);
220 break;
221
222 case CH_MODE_UNUSED:
223 default:
224 switch (st->channel_offstate[i]) {
225 case CH_OFFSTATE_OUT_TRISTATE:
226 tristate |= BIT(i);
227 break;
228
229 case CH_OFFSTATE_OUT_LOW:
230 st->gpio_out |= BIT(i);
231 break;
232
233 case CH_OFFSTATE_OUT_HIGH:
234 st->gpio_out |= BIT(i);
235 st->gpio_val |= BIT(i);
236 break;
237
238 case CH_OFFSTATE_PULLDOWN:
239 default:
240 pulldown |= BIT(i);
241 break;
242 }
243 }
244 }
245
246 mutex_lock(&st->lock);
247
248
249 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
250 if (ret)
251 goto err_unlock;
252
253 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
254 if (ret)
255 goto err_unlock;
256
257
258 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
259 if (ret)
260 goto err_unlock;
261
262 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
263 if (ret)
264 goto err_unlock;
265
266 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
267 if (ret)
268 goto err_unlock;
269
270 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
271 if (ret)
272 goto err_unlock;
273
274 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
275 if (ret)
276 goto err_unlock;
277
278
279 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
280 if (!ret && (read_back & 0xff) != adc)
281 ret = -EIO;
282
283err_unlock:
284 mutex_unlock(&st->lock);
285 return ret;
286}
287
288static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
289{
290 int i;
291
292 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
293 st->channel_modes[i] = CH_MODE_UNUSED;
294
295 return ad5592r_set_channel_modes(st);
296}
297
298static int ad5592r_write_raw(struct iio_dev *iio_dev,
299 struct iio_chan_spec const *chan, int val, int val2, long mask)
300{
301 struct ad5592r_state *st = iio_priv(iio_dev);
302 int ret;
303
304 switch (mask) {
305 case IIO_CHAN_INFO_RAW:
306
307 if (val >= (1 << chan->scan_type.realbits) || val < 0)
308 return -EINVAL;
309
310 if (!chan->output)
311 return -EINVAL;
312
313 mutex_lock(&st->lock);
314 ret = st->ops->write_dac(st, chan->channel, val);
315 if (!ret)
316 st->cached_dac[chan->channel] = val;
317 mutex_unlock(&st->lock);
318 return ret;
319 case IIO_CHAN_INFO_SCALE:
320 if (chan->type == IIO_VOLTAGE) {
321 bool gain;
322
323 if (val == st->scale_avail[0][0] &&
324 val2 == st->scale_avail[0][1])
325 gain = false;
326 else if (val == st->scale_avail[1][0] &&
327 val2 == st->scale_avail[1][1])
328 gain = true;
329 else
330 return -EINVAL;
331
332 mutex_lock(&st->lock);
333
334 ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
335 &st->cached_gp_ctrl);
336 if (ret < 0) {
337 mutex_unlock(&st->lock);
338 return ret;
339 }
340
341 if (chan->output) {
342 if (gain)
343 st->cached_gp_ctrl |=
344 AD5592R_REG_CTRL_DAC_RANGE;
345 else
346 st->cached_gp_ctrl &=
347 ~AD5592R_REG_CTRL_DAC_RANGE;
348 } else {
349 if (gain)
350 st->cached_gp_ctrl |=
351 AD5592R_REG_CTRL_ADC_RANGE;
352 else
353 st->cached_gp_ctrl &=
354 ~AD5592R_REG_CTRL_ADC_RANGE;
355 }
356
357 ret = st->ops->reg_write(st, AD5592R_REG_CTRL,
358 st->cached_gp_ctrl);
359 mutex_unlock(&st->lock);
360
361 return ret;
362 }
363 break;
364 default:
365 return -EINVAL;
366 }
367
368 return 0;
369}
370
371static int ad5592r_read_raw(struct iio_dev *iio_dev,
372 struct iio_chan_spec const *chan,
373 int *val, int *val2, long m)
374{
375 struct ad5592r_state *st = iio_priv(iio_dev);
376 u16 read_val;
377 int ret, mult;
378
379 switch (m) {
380 case IIO_CHAN_INFO_RAW:
381 if (!chan->output) {
382 mutex_lock(&st->lock);
383 ret = st->ops->read_adc(st, chan->channel, &read_val);
384 mutex_unlock(&st->lock);
385 if (ret)
386 return ret;
387
388 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
389 dev_err(st->dev, "Error while reading channel %u\n",
390 chan->channel);
391 return -EIO;
392 }
393
394 read_val &= GENMASK(11, 0);
395
396 } else {
397 mutex_lock(&st->lock);
398 read_val = st->cached_dac[chan->channel];
399 mutex_unlock(&st->lock);
400 }
401
402 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
403 chan->channel, read_val);
404
405 *val = (int) read_val;
406 return IIO_VAL_INT;
407 case IIO_CHAN_INFO_SCALE:
408 *val = ad5592r_get_vref(st);
409
410 if (chan->type == IIO_TEMP) {
411 s64 tmp = *val * (3767897513LL / 25LL);
412 *val = div_s64_rem(tmp, 1000000000LL, val2);
413
414 return IIO_VAL_INT_PLUS_MICRO;
415 }
416
417 mutex_lock(&st->lock);
418
419 if (chan->output)
420 mult = !!(st->cached_gp_ctrl &
421 AD5592R_REG_CTRL_DAC_RANGE);
422 else
423 mult = !!(st->cached_gp_ctrl &
424 AD5592R_REG_CTRL_ADC_RANGE);
425
426 mutex_unlock(&st->lock);
427
428 *val *= ++mult;
429
430 *val2 = chan->scan_type.realbits;
431
432 return IIO_VAL_FRACTIONAL_LOG2;
433 case IIO_CHAN_INFO_OFFSET:
434 ret = ad5592r_get_vref(st);
435
436 mutex_lock(&st->lock);
437
438 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
439 *val = (-34365 * 25) / ret;
440 else
441 *val = (-75365 * 25) / ret;
442
443 mutex_unlock(&st->lock);
444
445 return IIO_VAL_INT;
446 default:
447 return -EINVAL;
448 }
449}
450
451static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
452 struct iio_chan_spec const *chan, long mask)
453{
454 switch (mask) {
455 case IIO_CHAN_INFO_SCALE:
456 return IIO_VAL_INT_PLUS_NANO;
457
458 default:
459 return IIO_VAL_INT_PLUS_MICRO;
460 }
461
462 return -EINVAL;
463}
464
465static const struct iio_info ad5592r_info = {
466 .read_raw = ad5592r_read_raw,
467 .write_raw = ad5592r_write_raw,
468 .write_raw_get_fmt = ad5592r_write_raw_get_fmt,
469};
470
471static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
472 uintptr_t private,
473 const struct iio_chan_spec *chan,
474 char *buf)
475{
476 struct ad5592r_state *st = iio_priv(iio_dev);
477
478 return sprintf(buf, "%d.%09u %d.%09u\n",
479 st->scale_avail[0][0], st->scale_avail[0][1],
480 st->scale_avail[1][0], st->scale_avail[1][1]);
481}
482
483static const struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
484 {
485 .name = "scale_available",
486 .read = ad5592r_show_scale_available,
487 .shared = IIO_SHARED_BY_TYPE,
488 },
489 {},
490};
491
492static void ad5592r_setup_channel(struct iio_dev *iio_dev,
493 struct iio_chan_spec *chan, bool output, unsigned id)
494{
495 chan->type = IIO_VOLTAGE;
496 chan->indexed = 1;
497 chan->output = output;
498 chan->channel = id;
499 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
500 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
501 chan->scan_type.sign = 'u';
502 chan->scan_type.realbits = 12;
503 chan->scan_type.storagebits = 16;
504 chan->ext_info = ad5592r_ext_info;
505}
506
507static int ad5592r_alloc_channels(struct iio_dev *iio_dev)
508{
509 struct ad5592r_state *st = iio_priv(iio_dev);
510 unsigned i, curr_channel = 0,
511 num_channels = st->num_channels;
512 struct iio_chan_spec *channels;
513 struct fwnode_handle *child;
514 u32 reg, tmp;
515 int ret;
516
517 device_for_each_child_node(st->dev, child) {
518 ret = fwnode_property_read_u32(child, "reg", ®);
519 if (ret || reg >= ARRAY_SIZE(st->channel_modes))
520 continue;
521
522 ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
523 if (!ret)
524 st->channel_modes[reg] = tmp;
525
526 fwnode_property_read_u32(child, "adi,off-state", &tmp);
527 if (!ret)
528 st->channel_offstate[reg] = tmp;
529 }
530
531 channels = devm_kcalloc(st->dev,
532 1 + 2 * num_channels, sizeof(*channels),
533 GFP_KERNEL);
534 if (!channels)
535 return -ENOMEM;
536
537 for (i = 0; i < num_channels; i++) {
538 switch (st->channel_modes[i]) {
539 case CH_MODE_DAC:
540 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
541 true, i);
542 curr_channel++;
543 break;
544
545 case CH_MODE_ADC:
546 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
547 false, i);
548 curr_channel++;
549 break;
550
551 case CH_MODE_DAC_AND_ADC:
552 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
553 true, i);
554 curr_channel++;
555 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
556 false, i);
557 curr_channel++;
558 break;
559
560 default:
561 continue;
562 }
563 }
564
565 channels[curr_channel].type = IIO_TEMP;
566 channels[curr_channel].channel = 8;
567 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
568 BIT(IIO_CHAN_INFO_SCALE) |
569 BIT(IIO_CHAN_INFO_OFFSET);
570 curr_channel++;
571
572 iio_dev->num_channels = curr_channel;
573 iio_dev->channels = channels;
574
575 return 0;
576}
577
578static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
579{
580 s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
581
582 st->scale_avail[0][0] =
583 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
584 st->scale_avail[1][0] =
585 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
586}
587
588int ad5592r_probe(struct device *dev, const char *name,
589 const struct ad5592r_rw_ops *ops)
590{
591 struct iio_dev *iio_dev;
592 struct ad5592r_state *st;
593 int ret;
594
595 iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
596 if (!iio_dev)
597 return -ENOMEM;
598
599 st = iio_priv(iio_dev);
600 st->dev = dev;
601 st->ops = ops;
602 st->num_channels = 8;
603 dev_set_drvdata(dev, iio_dev);
604
605 st->reg = devm_regulator_get_optional(dev, "vref");
606 if (IS_ERR(st->reg)) {
607 if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node)
608 return PTR_ERR(st->reg);
609
610 st->reg = NULL;
611 } else {
612 ret = regulator_enable(st->reg);
613 if (ret)
614 return ret;
615 }
616
617 iio_dev->name = name;
618 iio_dev->info = &ad5592r_info;
619 iio_dev->modes = INDIO_DIRECT_MODE;
620
621 mutex_init(&st->lock);
622
623 ad5592r_init_scales(st, ad5592r_get_vref(st));
624
625 ret = ad5592r_reset(st);
626 if (ret)
627 goto error_disable_reg;
628
629 ret = ops->reg_write(st, AD5592R_REG_PD,
630 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
631 if (ret)
632 goto error_disable_reg;
633
634 ret = ad5592r_alloc_channels(iio_dev);
635 if (ret)
636 goto error_disable_reg;
637
638 ret = ad5592r_set_channel_modes(st);
639 if (ret)
640 goto error_reset_ch_modes;
641
642 ret = iio_device_register(iio_dev);
643 if (ret)
644 goto error_reset_ch_modes;
645
646 ret = ad5592r_gpio_init(st);
647 if (ret)
648 goto error_dev_unregister;
649
650 return 0;
651
652error_dev_unregister:
653 iio_device_unregister(iio_dev);
654
655error_reset_ch_modes:
656 ad5592r_reset_channel_modes(st);
657
658error_disable_reg:
659 if (st->reg)
660 regulator_disable(st->reg);
661
662 return ret;
663}
664EXPORT_SYMBOL_GPL(ad5592r_probe);
665
666int ad5592r_remove(struct device *dev)
667{
668 struct iio_dev *iio_dev = dev_get_drvdata(dev);
669 struct ad5592r_state *st = iio_priv(iio_dev);
670
671 iio_device_unregister(iio_dev);
672 ad5592r_reset_channel_modes(st);
673 ad5592r_gpio_cleanup(st);
674
675 if (st->reg)
676 regulator_disable(st->reg);
677
678 return 0;
679}
680EXPORT_SYMBOL_GPL(ad5592r_remove);
681
682MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>");
683MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
684MODULE_LICENSE("GPL v2");
685
