1
2
3
4#include <asm/unaligned.h>
5#include <linux/acpi.h>
6#include <linux/delay.h>
7#include <linux/i2c.h>
8#include <linux/module.h>
9#include <linux/pm_runtime.h>
10#include <linux/nvmem-provider.h>
11#include <linux/regmap.h>
12#include <media/v4l2-ctrls.h>
13#include <media/v4l2-device.h>
14#include <media/v4l2-fwnode.h>
15
16#define OV2740_LINK_FREQ_360MHZ 360000000ULL
17#define OV2740_SCLK 72000000LL
18#define OV2740_MCLK 19200000
19#define OV2740_DATA_LANES 2
20#define OV2740_RGB_DEPTH 10
21
22#define OV2740_REG_CHIP_ID 0x300a
23#define OV2740_CHIP_ID 0x2740
24
25#define OV2740_REG_MODE_SELECT 0x0100
26#define OV2740_MODE_STANDBY 0x00
27#define OV2740_MODE_STREAMING 0x01
28
29
30#define OV2740_REG_VTS 0x380e
31#define OV2740_VTS_DEF 0x088a
32#define OV2740_VTS_MIN 0x0460
33#define OV2740_VTS_MAX 0x7fff
34
35
36#define OV2740_REG_HTS 0x380c
37
38
39#define OV2740_REG_EXPOSURE 0x3500
40#define OV2740_EXPOSURE_MIN 8
41#define OV2740_EXPOSURE_MAX_MARGIN 8
42#define OV2740_EXPOSURE_STEP 1
43
44
45#define OV2740_REG_ANALOG_GAIN 0x3508
46#define OV2740_ANAL_GAIN_MIN 128
47#define OV2740_ANAL_GAIN_MAX 1983
48#define OV2740_ANAL_GAIN_STEP 1
49
50
51#define OV2740_REG_MWB_R_GAIN 0x500a
52#define OV2740_REG_MWB_G_GAIN 0x500c
53#define OV2740_REG_MWB_B_GAIN 0x500e
54#define OV2740_DGTL_GAIN_MIN 0
55#define OV2740_DGTL_GAIN_MAX 4095
56#define OV2740_DGTL_GAIN_STEP 1
57#define OV2740_DGTL_GAIN_DEFAULT 1024
58
59
60#define OV2740_REG_TEST_PATTERN 0x5040
61#define OV2740_TEST_PATTERN_ENABLE BIT(7)
62#define OV2740_TEST_PATTERN_BAR_SHIFT 2
63
64
65#define OV2740_REG_ISP_CTRL00 0x5000
66
67#define OV2740_REG_ISP_CTRL01 0x5001
68
69#define CUSTOMER_USE_OTP_SIZE 0x100
70
71#define OV2740_REG_OTP_CUSTOMER 0x7010
72
73struct nvm_data {
74 char *nvm_buffer;
75 struct nvmem_device *nvmem;
76 struct regmap *regmap;
77};
78
79enum {
80 OV2740_LINK_FREQ_360MHZ_INDEX,
81};
82
83struct ov2740_reg {
84 u16 address;
85 u8 val;
86};
87
88struct ov2740_reg_list {
89 u32 num_of_regs;
90 const struct ov2740_reg *regs;
91};
92
93struct ov2740_link_freq_config {
94 const struct ov2740_reg_list reg_list;
95};
96
97struct ov2740_mode {
98
99 u32 width;
100
101
102 u32 height;
103
104
105 u32 hts;
106
107
108 u32 vts_def;
109
110
111 u32 vts_min;
112
113
114 u32 link_freq_index;
115
116
117 const struct ov2740_reg_list reg_list;
118};
119
120static const struct ov2740_reg mipi_data_rate_720mbps[] = {
121 {0x0103, 0x01},
122 {0x0302, 0x4b},
123 {0x030d, 0x4b},
124 {0x030e, 0x02},
125 {0x030a, 0x01},
126 {0x0312, 0x11},
127};
128
129static const struct ov2740_reg mode_1932x1092_regs[] = {
130 {0x3000, 0x00},
131 {0x3018, 0x32},
132 {0x3031, 0x0a},
133 {0x3080, 0x08},
134 {0x3083, 0xB4},
135 {0x3103, 0x00},
136 {0x3104, 0x01},
137 {0x3106, 0x01},
138 {0x3500, 0x00},
139 {0x3501, 0x44},
140 {0x3502, 0x40},
141 {0x3503, 0x88},
142 {0x3507, 0x00},
143 {0x3508, 0x00},
144 {0x3509, 0x80},
145 {0x350c, 0x00},
146 {0x350d, 0x80},
147 {0x3510, 0x00},
148 {0x3511, 0x00},
149 {0x3512, 0x20},
150 {0x3632, 0x00},
151 {0x3633, 0x10},
152 {0x3634, 0x10},
153 {0x3635, 0x10},
154 {0x3645, 0x13},
155 {0x3646, 0x81},
156 {0x3636, 0x10},
157 {0x3651, 0x0a},
158 {0x3656, 0x02},
159 {0x3659, 0x04},
160 {0x365a, 0xda},
161 {0x365b, 0xa2},
162 {0x365c, 0x04},
163 {0x365d, 0x1d},
164 {0x365e, 0x1a},
165 {0x3662, 0xd7},
166 {0x3667, 0x78},
167 {0x3669, 0x0a},
168 {0x366a, 0x92},
169 {0x3700, 0x54},
170 {0x3702, 0x10},
171 {0x3706, 0x42},
172 {0x3709, 0x30},
173 {0x370b, 0xc2},
174 {0x3714, 0x63},
175 {0x3715, 0x01},
176 {0x3716, 0x00},
177 {0x371a, 0x3e},
178 {0x3732, 0x0e},
179 {0x3733, 0x10},
180 {0x375f, 0x0e},
181 {0x3768, 0x30},
182 {0x3769, 0x44},
183 {0x376a, 0x22},
184 {0x377b, 0x20},
185 {0x377c, 0x00},
186 {0x377d, 0x0c},
187 {0x3798, 0x00},
188 {0x37a1, 0x55},
189 {0x37a8, 0x6d},
190 {0x37c2, 0x04},
191 {0x37c5, 0x00},
192 {0x37c8, 0x00},
193 {0x3800, 0x00},
194 {0x3801, 0x00},
195 {0x3802, 0x00},
196 {0x3803, 0x00},
197 {0x3804, 0x07},
198 {0x3805, 0x8f},
199 {0x3806, 0x04},
200 {0x3807, 0x47},
201 {0x3808, 0x07},
202 {0x3809, 0x88},
203 {0x380a, 0x04},
204 {0x380b, 0x40},
205 {0x380c, 0x04},
206 {0x380d, 0x38},
207 {0x380e, 0x04},
208 {0x380f, 0x60},
209 {0x3810, 0x00},
210 {0x3811, 0x04},
211 {0x3812, 0x00},
212 {0x3813, 0x04},
213 {0x3814, 0x01},
214 {0x3815, 0x01},
215 {0x3820, 0x80},
216 {0x3821, 0x46},
217 {0x3822, 0x84},
218 {0x3829, 0x00},
219 {0x382a, 0x01},
220 {0x382b, 0x01},
221 {0x3830, 0x04},
222 {0x3836, 0x01},
223 {0x3837, 0x08},
224 {0x3839, 0x01},
225 {0x383a, 0x00},
226 {0x383b, 0x08},
227 {0x383c, 0x00},
228 {0x3f0b, 0x00},
229 {0x4001, 0x20},
230 {0x4009, 0x07},
231 {0x4003, 0x10},
232 {0x4010, 0xe0},
233 {0x4016, 0x00},
234 {0x4017, 0x10},
235 {0x4044, 0x02},
236 {0x4304, 0x08},
237 {0x4307, 0x30},
238 {0x4320, 0x80},
239 {0x4322, 0x00},
240 {0x4323, 0x00},
241 {0x4324, 0x00},
242 {0x4325, 0x00},
243 {0x4326, 0x00},
244 {0x4327, 0x00},
245 {0x4328, 0x00},
246 {0x4329, 0x00},
247 {0x432c, 0x03},
248 {0x432d, 0x81},
249 {0x4501, 0x84},
250 {0x4502, 0x40},
251 {0x4503, 0x18},
252 {0x4504, 0x04},
253 {0x4508, 0x02},
254 {0x4601, 0x10},
255 {0x4800, 0x00},
256 {0x4816, 0x52},
257 {0x4837, 0x16},
258 {0x5000, 0x7f},
259 {0x5001, 0x00},
260 {0x5005, 0x38},
261 {0x501e, 0x0d},
262 {0x5040, 0x00},
263 {0x5901, 0x00},
264 {0x3800, 0x00},
265 {0x3801, 0x00},
266 {0x3802, 0x00},
267 {0x3803, 0x00},
268 {0x3804, 0x07},
269 {0x3805, 0x8f},
270 {0x3806, 0x04},
271 {0x3807, 0x47},
272 {0x3808, 0x07},
273 {0x3809, 0x8c},
274 {0x380a, 0x04},
275 {0x380b, 0x44},
276 {0x3810, 0x00},
277 {0x3811, 0x00},
278 {0x3812, 0x00},
279 {0x3813, 0x01},
280};
281
282static const char * const ov2740_test_pattern_menu[] = {
283 "Disabled",
284 "Color Bar",
285 "Top-Bottom Darker Color Bar",
286 "Right-Left Darker Color Bar",
287 "Bottom-Top Darker Color Bar",
288};
289
290static const s64 link_freq_menu_items[] = {
291 OV2740_LINK_FREQ_360MHZ,
292};
293
294static const struct ov2740_link_freq_config link_freq_configs[] = {
295 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
296 .reg_list = {
297 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
298 .regs = mipi_data_rate_720mbps,
299 }
300 },
301};
302
303static const struct ov2740_mode supported_modes[] = {
304 {
305 .width = 1932,
306 .height = 1092,
307 .hts = 1080,
308 .vts_def = OV2740_VTS_DEF,
309 .vts_min = OV2740_VTS_MIN,
310 .reg_list = {
311 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
312 .regs = mode_1932x1092_regs,
313 },
314 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
315 },
316};
317
318struct ov2740 {
319 struct v4l2_subdev sd;
320 struct media_pad pad;
321 struct v4l2_ctrl_handler ctrl_handler;
322
323
324 struct v4l2_ctrl *link_freq;
325 struct v4l2_ctrl *pixel_rate;
326 struct v4l2_ctrl *vblank;
327 struct v4l2_ctrl *hblank;
328 struct v4l2_ctrl *exposure;
329
330
331 const struct ov2740_mode *cur_mode;
332
333
334 struct mutex mutex;
335
336
337 bool streaming;
338};
339
340static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
341{
342 return container_of(subdev, struct ov2740, sd);
343}
344
345static u64 to_pixel_rate(u32 f_index)
346{
347 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
348
349 do_div(pixel_rate, OV2740_RGB_DEPTH);
350
351 return pixel_rate;
352}
353
354static u64 to_pixels_per_line(u32 hts, u32 f_index)
355{
356 u64 ppl = hts * to_pixel_rate(f_index);
357
358 do_div(ppl, OV2740_SCLK);
359
360 return ppl;
361}
362
363static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
364{
365 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
366 struct i2c_msg msgs[2];
367 u8 addr_buf[2];
368 u8 data_buf[4] = {0};
369 int ret = 0;
370
371 if (len > sizeof(data_buf))
372 return -EINVAL;
373
374 put_unaligned_be16(reg, addr_buf);
375 msgs[0].addr = client->addr;
376 msgs[0].flags = 0;
377 msgs[0].len = sizeof(addr_buf);
378 msgs[0].buf = addr_buf;
379 msgs[1].addr = client->addr;
380 msgs[1].flags = I2C_M_RD;
381 msgs[1].len = len;
382 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
383
384 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
385 if (ret != ARRAY_SIZE(msgs))
386 return ret < 0 ? ret : -EIO;
387
388 *val = get_unaligned_be32(data_buf);
389
390 return 0;
391}
392
393static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
394{
395 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
396 u8 buf[6];
397 int ret = 0;
398
399 if (len > 4)
400 return -EINVAL;
401
402 put_unaligned_be16(reg, buf);
403 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
404
405 ret = i2c_master_send(client, buf, len + 2);
406 if (ret != len + 2)
407 return ret < 0 ? ret : -EIO;
408
409 return 0;
410}
411
412static int ov2740_write_reg_list(struct ov2740 *ov2740,
413 const struct ov2740_reg_list *r_list)
414{
415 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
416 unsigned int i;
417 int ret = 0;
418
419 for (i = 0; i < r_list->num_of_regs; i++) {
420 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
421 r_list->regs[i].val);
422 if (ret) {
423 dev_err_ratelimited(&client->dev,
424 "write reg 0x%4.4x return err = %d",
425 r_list->regs[i].address, ret);
426 return ret;
427 }
428 }
429
430 return 0;
431}
432
433static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
434{
435 int ret = 0;
436
437 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
438 if (ret)
439 return ret;
440
441 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
442 if (ret)
443 return ret;
444
445 return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
446}
447
448static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
449{
450 if (pattern)
451 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
452 OV2740_TEST_PATTERN_ENABLE;
453
454 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
455}
456
457static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
458{
459 struct ov2740 *ov2740 = container_of(ctrl->handler,
460 struct ov2740, ctrl_handler);
461 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
462 s64 exposure_max;
463 int ret = 0;
464
465
466 if (ctrl->id == V4L2_CID_VBLANK) {
467
468 exposure_max = ov2740->cur_mode->height + ctrl->val -
469 OV2740_EXPOSURE_MAX_MARGIN;
470 __v4l2_ctrl_modify_range(ov2740->exposure,
471 ov2740->exposure->minimum,
472 exposure_max, ov2740->exposure->step,
473 exposure_max);
474 }
475
476
477 if (!pm_runtime_get_if_in_use(&client->dev))
478 return 0;
479
480 switch (ctrl->id) {
481 case V4L2_CID_ANALOGUE_GAIN:
482 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
483 ctrl->val);
484 break;
485
486 case V4L2_CID_DIGITAL_GAIN:
487 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
488 break;
489
490 case V4L2_CID_EXPOSURE:
491
492 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
493 ctrl->val << 4);
494 break;
495
496 case V4L2_CID_VBLANK:
497 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
498 ov2740->cur_mode->height + ctrl->val);
499 break;
500
501 case V4L2_CID_TEST_PATTERN:
502 ret = ov2740_test_pattern(ov2740, ctrl->val);
503 break;
504
505 default:
506 ret = -EINVAL;
507 break;
508 }
509
510 pm_runtime_put(&client->dev);
511
512 return ret;
513}
514
515static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
516 .s_ctrl = ov2740_set_ctrl,
517};
518
519static int ov2740_init_controls(struct ov2740 *ov2740)
520{
521 struct v4l2_ctrl_handler *ctrl_hdlr;
522 const struct ov2740_mode *cur_mode;
523 s64 exposure_max, h_blank, pixel_rate;
524 u32 vblank_min, vblank_max, vblank_default;
525 int size;
526 int ret = 0;
527
528 ctrl_hdlr = &ov2740->ctrl_handler;
529 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
530 if (ret)
531 return ret;
532
533 ctrl_hdlr->lock = &ov2740->mutex;
534 cur_mode = ov2740->cur_mode;
535 size = ARRAY_SIZE(link_freq_menu_items);
536
537 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
538 V4L2_CID_LINK_FREQ,
539 size - 1, 0,
540 link_freq_menu_items);
541 if (ov2740->link_freq)
542 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
543
544 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
545 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
546 V4L2_CID_PIXEL_RATE, 0,
547 pixel_rate, 1, pixel_rate);
548
549 vblank_min = cur_mode->vts_min - cur_mode->height;
550 vblank_max = OV2740_VTS_MAX - cur_mode->height;
551 vblank_default = cur_mode->vts_def - cur_mode->height;
552 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
553 V4L2_CID_VBLANK, vblank_min,
554 vblank_max, 1, vblank_default);
555
556 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
557 h_blank -= cur_mode->width;
558 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
559 V4L2_CID_HBLANK, h_blank, h_blank, 1,
560 h_blank);
561 if (ov2740->hblank)
562 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
563
564 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
565 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
566 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
567 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
568 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
569 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
570 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
571 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
572 V4L2_CID_EXPOSURE,
573 OV2740_EXPOSURE_MIN, exposure_max,
574 OV2740_EXPOSURE_STEP,
575 exposure_max);
576 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
577 V4L2_CID_TEST_PATTERN,
578 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
579 0, 0, ov2740_test_pattern_menu);
580 if (ctrl_hdlr->error)
581 return ctrl_hdlr->error;
582
583 ov2740->sd.ctrl_handler = ctrl_hdlr;
584
585 return 0;
586}
587
588static void ov2740_update_pad_format(const struct ov2740_mode *mode,
589 struct v4l2_mbus_framefmt *fmt)
590{
591 fmt->width = mode->width;
592 fmt->height = mode->height;
593 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
594 fmt->field = V4L2_FIELD_NONE;
595}
596
597static int ov2740_start_streaming(struct ov2740 *ov2740)
598{
599 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
600 const struct ov2740_reg_list *reg_list;
601 int link_freq_index;
602 int ret = 0;
603
604 link_freq_index = ov2740->cur_mode->link_freq_index;
605 reg_list = &link_freq_configs[link_freq_index].reg_list;
606 ret = ov2740_write_reg_list(ov2740, reg_list);
607 if (ret) {
608 dev_err(&client->dev, "failed to set plls");
609 return ret;
610 }
611
612 reg_list = &ov2740->cur_mode->reg_list;
613 ret = ov2740_write_reg_list(ov2740, reg_list);
614 if (ret) {
615 dev_err(&client->dev, "failed to set mode");
616 return ret;
617 }
618
619 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
620 if (ret)
621 return ret;
622
623 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
624 OV2740_MODE_STREAMING);
625 if (ret)
626 dev_err(&client->dev, "failed to start streaming");
627
628 return ret;
629}
630
631static void ov2740_stop_streaming(struct ov2740 *ov2740)
632{
633 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
634
635 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
636 OV2740_MODE_STANDBY))
637 dev_err(&client->dev, "failed to stop streaming");
638}
639
640static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
641{
642 struct ov2740 *ov2740 = to_ov2740(sd);
643 struct i2c_client *client = v4l2_get_subdevdata(sd);
644 int ret = 0;
645
646 if (ov2740->streaming == enable)
647 return 0;
648
649 mutex_lock(&ov2740->mutex);
650 if (enable) {
651 ret = pm_runtime_get_sync(&client->dev);
652 if (ret < 0) {
653 pm_runtime_put_noidle(&client->dev);
654 mutex_unlock(&ov2740->mutex);
655 return ret;
656 }
657
658 ret = ov2740_start_streaming(ov2740);
659 if (ret) {
660 enable = 0;
661 ov2740_stop_streaming(ov2740);
662 pm_runtime_put(&client->dev);
663 }
664 } else {
665 ov2740_stop_streaming(ov2740);
666 pm_runtime_put(&client->dev);
667 }
668
669 ov2740->streaming = enable;
670 mutex_unlock(&ov2740->mutex);
671
672 return ret;
673}
674
675static int __maybe_unused ov2740_suspend(struct device *dev)
676{
677 struct i2c_client *client = to_i2c_client(dev);
678 struct v4l2_subdev *sd = i2c_get_clientdata(client);
679 struct ov2740 *ov2740 = to_ov2740(sd);
680
681 mutex_lock(&ov2740->mutex);
682 if (ov2740->streaming)
683 ov2740_stop_streaming(ov2740);
684
685 mutex_unlock(&ov2740->mutex);
686
687 return 0;
688}
689
690static int __maybe_unused ov2740_resume(struct device *dev)
691{
692 struct i2c_client *client = to_i2c_client(dev);
693 struct v4l2_subdev *sd = i2c_get_clientdata(client);
694 struct ov2740 *ov2740 = to_ov2740(sd);
695 int ret = 0;
696
697 mutex_lock(&ov2740->mutex);
698 if (!ov2740->streaming)
699 goto exit;
700
701 ret = ov2740_start_streaming(ov2740);
702 if (ret) {
703 ov2740->streaming = false;
704 ov2740_stop_streaming(ov2740);
705 }
706
707exit:
708 mutex_unlock(&ov2740->mutex);
709 return ret;
710}
711
712static int ov2740_set_format(struct v4l2_subdev *sd,
713 struct v4l2_subdev_pad_config *cfg,
714 struct v4l2_subdev_format *fmt)
715{
716 struct ov2740 *ov2740 = to_ov2740(sd);
717 const struct ov2740_mode *mode;
718 s32 vblank_def, h_blank;
719
720 mode = v4l2_find_nearest_size(supported_modes,
721 ARRAY_SIZE(supported_modes), width,
722 height, fmt->format.width,
723 fmt->format.height);
724
725 mutex_lock(&ov2740->mutex);
726 ov2740_update_pad_format(mode, &fmt->format);
727 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
728 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
729 } else {
730 ov2740->cur_mode = mode;
731 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
732 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
733 to_pixel_rate(mode->link_freq_index));
734
735
736 vblank_def = mode->vts_def - mode->height;
737 __v4l2_ctrl_modify_range(ov2740->vblank,
738 mode->vts_min - mode->height,
739 OV2740_VTS_MAX - mode->height, 1,
740 vblank_def);
741 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
742 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
743 mode->width;
744 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
745 h_blank);
746 }
747 mutex_unlock(&ov2740->mutex);
748
749 return 0;
750}
751
752static int ov2740_get_format(struct v4l2_subdev *sd,
753 struct v4l2_subdev_pad_config *cfg,
754 struct v4l2_subdev_format *fmt)
755{
756 struct ov2740 *ov2740 = to_ov2740(sd);
757
758 mutex_lock(&ov2740->mutex);
759 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
760 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, cfg,
761 fmt->pad);
762 else
763 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
764
765 mutex_unlock(&ov2740->mutex);
766
767 return 0;
768}
769
770static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
771 struct v4l2_subdev_pad_config *cfg,
772 struct v4l2_subdev_mbus_code_enum *code)
773{
774 if (code->index > 0)
775 return -EINVAL;
776
777 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
778
779 return 0;
780}
781
782static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
783 struct v4l2_subdev_pad_config *cfg,
784 struct v4l2_subdev_frame_size_enum *fse)
785{
786 if (fse->index >= ARRAY_SIZE(supported_modes))
787 return -EINVAL;
788
789 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
790 return -EINVAL;
791
792 fse->min_width = supported_modes[fse->index].width;
793 fse->max_width = fse->min_width;
794 fse->min_height = supported_modes[fse->index].height;
795 fse->max_height = fse->min_height;
796
797 return 0;
798}
799
800static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
801{
802 struct ov2740 *ov2740 = to_ov2740(sd);
803
804 mutex_lock(&ov2740->mutex);
805 ov2740_update_pad_format(&supported_modes[0],
806 v4l2_subdev_get_try_format(sd, fh->pad, 0));
807 mutex_unlock(&ov2740->mutex);
808
809 return 0;
810}
811
812static const struct v4l2_subdev_video_ops ov2740_video_ops = {
813 .s_stream = ov2740_set_stream,
814};
815
816static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
817 .set_fmt = ov2740_set_format,
818 .get_fmt = ov2740_get_format,
819 .enum_mbus_code = ov2740_enum_mbus_code,
820 .enum_frame_size = ov2740_enum_frame_size,
821};
822
823static const struct v4l2_subdev_ops ov2740_subdev_ops = {
824 .video = &ov2740_video_ops,
825 .pad = &ov2740_pad_ops,
826};
827
828static const struct media_entity_operations ov2740_subdev_entity_ops = {
829 .link_validate = v4l2_subdev_link_validate,
830};
831
832static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
833 .open = ov2740_open,
834};
835
836static int ov2740_identify_module(struct ov2740 *ov2740)
837{
838 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
839 int ret;
840 u32 val;
841
842 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
843 if (ret)
844 return ret;
845
846 if (val != OV2740_CHIP_ID) {
847 dev_err(&client->dev, "chip id mismatch: %x!=%x",
848 OV2740_CHIP_ID, val);
849 return -ENXIO;
850 }
851
852 return 0;
853}
854
855static int ov2740_check_hwcfg(struct device *dev)
856{
857 struct fwnode_handle *ep;
858 struct fwnode_handle *fwnode = dev_fwnode(dev);
859 struct v4l2_fwnode_endpoint bus_cfg = {
860 .bus_type = V4L2_MBUS_CSI2_DPHY
861 };
862 u32 mclk;
863 int ret;
864 unsigned int i, j;
865
866 if (!fwnode)
867 return -ENXIO;
868
869 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
870 if (ret)
871 return ret;
872
873 if (mclk != OV2740_MCLK) {
874 dev_err(dev, "external clock %d is not supported", mclk);
875 return -EINVAL;
876 }
877
878 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
879 if (!ep)
880 return -ENXIO;
881
882 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
883 fwnode_handle_put(ep);
884 if (ret)
885 return ret;
886
887 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
888 dev_err(dev, "number of CSI2 data lanes %d is not supported",
889 bus_cfg.bus.mipi_csi2.num_data_lanes);
890 ret = -EINVAL;
891 goto check_hwcfg_error;
892 }
893
894 if (!bus_cfg.nr_of_link_frequencies) {
895 dev_err(dev, "no link frequencies defined");
896 ret = -EINVAL;
897 goto check_hwcfg_error;
898 }
899
900 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
901 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
902 if (link_freq_menu_items[i] ==
903 bus_cfg.link_frequencies[j])
904 break;
905 }
906
907 if (j == bus_cfg.nr_of_link_frequencies) {
908 dev_err(dev, "no link frequency %lld supported",
909 link_freq_menu_items[i]);
910 ret = -EINVAL;
911 goto check_hwcfg_error;
912 }
913 }
914
915check_hwcfg_error:
916 v4l2_fwnode_endpoint_free(&bus_cfg);
917
918 return ret;
919}
920
921static int ov2740_remove(struct i2c_client *client)
922{
923 struct v4l2_subdev *sd = i2c_get_clientdata(client);
924 struct ov2740 *ov2740 = to_ov2740(sd);
925
926 v4l2_async_unregister_subdev(sd);
927 media_entity_cleanup(&sd->entity);
928 v4l2_ctrl_handler_free(sd->ctrl_handler);
929 pm_runtime_disable(&client->dev);
930 mutex_destroy(&ov2740->mutex);
931
932 return 0;
933}
934
935static int ov2740_load_otp_data(struct i2c_client *client, struct nvm_data *nvm)
936{
937 struct ov2740 *ov2740 = to_ov2740(i2c_get_clientdata(client));
938 u32 isp_ctrl00 = 0;
939 u32 isp_ctrl01 = 0;
940 int ret;
941
942 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
943 if (ret) {
944 dev_err(&client->dev, "failed to read ISP CTRL00\n");
945 goto exit;
946 }
947 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
948 if (ret) {
949 dev_err(&client->dev, "failed to read ISP CTRL01\n");
950 goto exit;
951 }
952
953
954 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
955 isp_ctrl00 & ~BIT(5));
956 if (ret) {
957 dev_err(&client->dev, "failed to write ISP CTRL00\n");
958 goto exit;
959 }
960
961
962 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
963 isp_ctrl01 & ~BIT(7));
964 if (ret) {
965 dev_err(&client->dev, "failed to write ISP CTRL01\n");
966 goto exit;
967 }
968
969 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
970 OV2740_MODE_STREAMING);
971 if (ret) {
972 dev_err(&client->dev, "failed to start streaming\n");
973 goto exit;
974 }
975
976
977
978
979
980 msleep(20);
981
982 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
983 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
984 if (ret) {
985 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
986 goto exit;
987 }
988
989 ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
990 OV2740_MODE_STANDBY);
991 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
992 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
993
994exit:
995 return ret;
996}
997
998static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
999 size_t count)
1000{
1001 struct nvm_data *nvm = priv;
1002
1003 memcpy(val, nvm->nvm_buffer + off, count);
1004
1005 return 0;
1006}
1007
1008static int ov2740_register_nvmem(struct i2c_client *client)
1009{
1010 struct nvm_data *nvm;
1011 struct regmap_config regmap_config = { };
1012 struct nvmem_config nvmem_config = { };
1013 struct regmap *regmap;
1014 struct device *dev = &client->dev;
1015 int ret = 0;
1016
1017 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1018 if (!nvm)
1019 return -ENOMEM;
1020
1021 nvm->nvm_buffer = devm_kzalloc(dev, CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
1022 if (!nvm->nvm_buffer)
1023 return -ENOMEM;
1024
1025 regmap_config.val_bits = 8;
1026 regmap_config.reg_bits = 16;
1027 regmap_config.disable_locking = true;
1028 regmap = devm_regmap_init_i2c(client, ®map_config);
1029 if (IS_ERR(regmap))
1030 return PTR_ERR(regmap);
1031
1032 nvm->regmap = regmap;
1033
1034 ret = ov2740_load_otp_data(client, nvm);
1035 if (ret) {
1036 dev_err(dev, "failed to load OTP data, ret %d\n", ret);
1037 return ret;
1038 }
1039
1040 nvmem_config.name = dev_name(dev);
1041 nvmem_config.dev = dev;
1042 nvmem_config.read_only = true;
1043 nvmem_config.root_only = true;
1044 nvmem_config.owner = THIS_MODULE;
1045 nvmem_config.compat = true;
1046 nvmem_config.base_dev = dev;
1047 nvmem_config.reg_read = ov2740_nvmem_read;
1048 nvmem_config.reg_write = NULL;
1049 nvmem_config.priv = nvm;
1050 nvmem_config.stride = 1;
1051 nvmem_config.word_size = 1;
1052 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1053
1054 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1055
1056 return PTR_ERR_OR_ZERO(nvm->nvmem);
1057}
1058
1059static int ov2740_probe(struct i2c_client *client)
1060{
1061 struct ov2740 *ov2740;
1062 int ret = 0;
1063
1064 ret = ov2740_check_hwcfg(&client->dev);
1065 if (ret) {
1066 dev_err(&client->dev, "failed to check HW configuration: %d",
1067 ret);
1068 return ret;
1069 }
1070
1071 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1072 if (!ov2740)
1073 return -ENOMEM;
1074
1075 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1076 ret = ov2740_identify_module(ov2740);
1077 if (ret) {
1078 dev_err(&client->dev, "failed to find sensor: %d", ret);
1079 return ret;
1080 }
1081
1082 mutex_init(&ov2740->mutex);
1083 ov2740->cur_mode = &supported_modes[0];
1084 ret = ov2740_init_controls(ov2740);
1085 if (ret) {
1086 dev_err(&client->dev, "failed to init controls: %d", ret);
1087 goto probe_error_v4l2_ctrl_handler_free;
1088 }
1089
1090 ov2740->sd.internal_ops = &ov2740_internal_ops;
1091 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1092 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1093 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1094 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1095 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1096 if (ret) {
1097 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1098 goto probe_error_v4l2_ctrl_handler_free;
1099 }
1100
1101 ret = v4l2_async_register_subdev_sensor_common(&ov2740->sd);
1102 if (ret < 0) {
1103 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1104 ret);
1105 goto probe_error_media_entity_cleanup;
1106 }
1107
1108 ret = ov2740_register_nvmem(client);
1109 if (ret)
1110 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1111
1112
1113
1114
1115
1116 pm_runtime_set_active(&client->dev);
1117 pm_runtime_enable(&client->dev);
1118 pm_runtime_idle(&client->dev);
1119
1120 return 0;
1121
1122probe_error_media_entity_cleanup:
1123 media_entity_cleanup(&ov2740->sd.entity);
1124
1125probe_error_v4l2_ctrl_handler_free:
1126 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1127 mutex_destroy(&ov2740->mutex);
1128
1129 return ret;
1130}
1131
1132static const struct dev_pm_ops ov2740_pm_ops = {
1133 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume)
1134};
1135
1136static const struct acpi_device_id ov2740_acpi_ids[] = {
1137 {"INT3474"},
1138 {}
1139};
1140
1141MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1142
1143static struct i2c_driver ov2740_i2c_driver = {
1144 .driver = {
1145 .name = "ov2740",
1146 .pm = &ov2740_pm_ops,
1147 .acpi_match_table = ov2740_acpi_ids,
1148 },
1149 .probe_new = ov2740_probe,
1150 .remove = ov2740_remove,
1151};
1152
1153module_i2c_driver(ov2740_i2c_driver);
1154
1155MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1156MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1157MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1158MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1159MODULE_LICENSE("GPL v2");
1160
