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18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pnp.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/sched.h>
26#include <linux/slab.h>
27#include <media/rc-core.h>
28#include "ene_ir.h"
29
30static int sample_period;
31static bool learning_mode_force;
32static int debug;
33static bool txsim;
34
35static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
36{
37 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
38 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
39}
40
41
42static u8 ene_read_reg(struct ene_device *dev, u16 reg)
43{
44 u8 retval;
45 ene_set_reg_addr(dev, reg);
46 retval = inb(dev->hw_io + ENE_IO);
47 dbg_regs("reg %04x == %02x", reg, retval);
48 return retval;
49}
50
51
52static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
53{
54 dbg_regs("reg %04x <- %02x", reg, value);
55 ene_set_reg_addr(dev, reg);
56 outb(value, dev->hw_io + ENE_IO);
57}
58
59
60static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
61{
62 dbg_regs("reg %04x |= %02x", reg, mask);
63 ene_set_reg_addr(dev, reg);
64 outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
65}
66
67
68static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
69{
70 dbg_regs("reg %04x &= ~%02x ", reg, mask);
71 ene_set_reg_addr(dev, reg);
72 outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
73}
74
75
76static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
77 bool set)
78{
79 if (set)
80 ene_set_reg_mask(dev, reg, mask);
81 else
82 ene_clear_reg_mask(dev, reg, mask);
83}
84
85
86static int ene_hw_detect(struct ene_device *dev)
87{
88 u8 chip_major, chip_minor;
89 u8 hw_revision, old_ver;
90 u8 fw_reg2, fw_reg1;
91
92 ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
93 chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
94 chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
95 ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
96
97 hw_revision = ene_read_reg(dev, ENE_ECHV);
98 old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
99
100 dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
101 (ene_read_reg(dev, ENE_PLLFRL) >> 4);
102
103 if (sample_period != ENE_DEFAULT_SAMPLE_PERIOD)
104 dev->rx_period_adjust =
105 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
106
107 if (hw_revision == 0xFF) {
108 pr_warn("device seems to be disabled\n");
109 pr_warn("send a mail to lirc-list@lists.sourceforge.net\n");
110 pr_warn("please attach output of acpidump and dmidecode\n");
111 return -ENODEV;
112 }
113
114 pr_notice("chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x\n",
115 chip_major, chip_minor, old_ver, hw_revision);
116
117 pr_notice("PLL freq = %d\n", dev->pll_freq);
118
119 if (chip_major == 0x33) {
120 pr_warn("chips 0x33xx aren't supported\n");
121 return -ENODEV;
122 }
123
124 if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) {
125 dev->hw_revision = ENE_HW_C;
126 pr_notice("KB3926C detected\n");
127 } else if (old_ver == 0x24 && hw_revision == 0xC0) {
128 dev->hw_revision = ENE_HW_B;
129 pr_notice("KB3926B detected\n");
130 } else {
131 dev->hw_revision = ENE_HW_D;
132 pr_notice("KB3926D or higher detected\n");
133 }
134
135
136 if (dev->hw_revision < ENE_HW_C)
137 return 0;
138
139 fw_reg1 = ene_read_reg(dev, ENE_FW1);
140 fw_reg2 = ene_read_reg(dev, ENE_FW2);
141
142 pr_notice("Firmware regs: %02x %02x\n", fw_reg1, fw_reg2);
143
144 dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A);
145 dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING);
146 dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF);
147
148 if (dev->hw_learning_and_tx_capable)
149 dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT);
150
151 pr_notice("Hardware features:\n");
152
153 if (dev->hw_learning_and_tx_capable) {
154 pr_notice("* Supports transmitting & learning mode\n");
155 pr_notice(" This feature is rare and therefore,\n");
156 pr_notice(" you are welcome to test it,\n");
157 pr_notice(" and/or contact the author via:\n");
158 pr_notice(" lirc-list@lists.sourceforge.net\n");
159 pr_notice(" or maximlevitsky@gmail.com\n");
160
161 pr_notice("* Uses GPIO %s for IR raw input\n",
162 dev->hw_use_gpio_0a ? "40" : "0A");
163
164 if (dev->hw_fan_input)
165 pr_notice("* Uses unused fan feedback input as source of demodulated IR data\n");
166 }
167
168 if (!dev->hw_fan_input)
169 pr_notice("* Uses GPIO %s for IR demodulated input\n",
170 dev->hw_use_gpio_0a ? "0A" : "40");
171
172 if (dev->hw_extra_buffer)
173 pr_notice("* Uses new style input buffer\n");
174 return 0;
175}
176
177
178static void ene_rx_setup_hw_buffer(struct ene_device *dev)
179{
180 u16 tmp;
181
182 ene_rx_read_hw_pointer(dev);
183 dev->r_pointer = dev->w_pointer;
184
185 if (!dev->hw_extra_buffer) {
186 dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
187 return;
188 }
189
190 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
191 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
192 dev->extra_buf1_address = tmp;
193
194 dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
195
196 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
197 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
198 dev->extra_buf2_address = tmp;
199
200 dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
201
202 dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
203
204 pr_notice("Hardware uses 2 extended buffers:\n");
205 pr_notice(" 0x%04x - len : %d\n",
206 dev->extra_buf1_address, dev->extra_buf1_len);
207 pr_notice(" 0x%04x - len : %d\n",
208 dev->extra_buf2_address, dev->extra_buf2_len);
209
210 pr_notice("Total buffer len = %d\n", dev->buffer_len);
211
212 if (dev->buffer_len > 64 || dev->buffer_len < 16)
213 goto error;
214
215 if (dev->extra_buf1_address > 0xFBFC ||
216 dev->extra_buf1_address < 0xEC00)
217 goto error;
218
219 if (dev->extra_buf2_address > 0xFBFC ||
220 dev->extra_buf2_address < 0xEC00)
221 goto error;
222
223 if (dev->r_pointer > dev->buffer_len)
224 goto error;
225
226 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
227 return;
228error:
229 pr_warn("Error validating extra buffers, device probably won't work\n");
230 dev->hw_extra_buffer = false;
231 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
232}
233
234
235
236static void ene_rx_restore_hw_buffer(struct ene_device *dev)
237{
238 if (!dev->hw_extra_buffer)
239 return;
240
241 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
242 dev->extra_buf1_address & 0xFF);
243 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
244 dev->extra_buf1_address >> 8);
245 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
246
247 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
248 dev->extra_buf2_address & 0xFF);
249 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
250 dev->extra_buf2_address >> 8);
251 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
252 dev->extra_buf2_len);
253 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
254}
255
256
257static void ene_rx_read_hw_pointer(struct ene_device *dev)
258{
259 if (dev->hw_extra_buffer)
260 dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
261 else
262 dev->w_pointer = ene_read_reg(dev, ENE_FW2)
263 & ENE_FW2_BUF_WPTR ? 0 : ENE_FW_PACKET_SIZE;
264
265 dbg_verbose("RB: HW write pointer: %02x, driver read pointer: %02x",
266 dev->w_pointer, dev->r_pointer);
267}
268
269
270static int ene_rx_get_sample_reg(struct ene_device *dev)
271{
272 int r_pointer;
273
274 if (dev->r_pointer == dev->w_pointer) {
275 dbg_verbose("RB: hit end, try update w_pointer");
276 ene_rx_read_hw_pointer(dev);
277 }
278
279 if (dev->r_pointer == dev->w_pointer) {
280 dbg_verbose("RB: end of data at %d", dev->r_pointer);
281 return 0;
282 }
283
284 dbg_verbose("RB: reading at offset %d", dev->r_pointer);
285 r_pointer = dev->r_pointer;
286
287 dev->r_pointer++;
288 if (dev->r_pointer == dev->buffer_len)
289 dev->r_pointer = 0;
290
291 dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
292
293 if (r_pointer < 8) {
294 dbg_verbose("RB: read at main buffer at %d", r_pointer);
295 return ENE_FW_SAMPLE_BUFFER + r_pointer;
296 }
297
298 r_pointer -= 8;
299
300 if (r_pointer < dev->extra_buf1_len) {
301 dbg_verbose("RB: read at 1st extra buffer at %d", r_pointer);
302 return dev->extra_buf1_address + r_pointer;
303 }
304
305 r_pointer -= dev->extra_buf1_len;
306
307 if (r_pointer < dev->extra_buf2_len) {
308 dbg_verbose("RB: read at 2nd extra buffer at %d", r_pointer);
309 return dev->extra_buf2_address + r_pointer;
310 }
311
312 dbg("attempt to read beyond ring buffer end");
313 return 0;
314}
315
316
317static void ene_rx_sense_carrier(struct ene_device *dev)
318{
319 int carrier, duty_cycle;
320 int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
321 int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
322
323 if (!(period & ENE_CIRCAR_PRD_VALID))
324 return;
325
326 period &= ~ENE_CIRCAR_PRD_VALID;
327
328 if (!period)
329 return;
330
331 dbg("RX: hardware carrier period = %02x", period);
332 dbg("RX: hardware carrier pulse period = %02x", hperiod);
333
334 carrier = 2000000 / period;
335 duty_cycle = (hperiod * 100) / period;
336 dbg("RX: sensed carrier = %d Hz, duty cycle %d%%",
337 carrier, duty_cycle);
338 if (dev->carrier_detect_enabled) {
339 struct ir_raw_event ev = {
340 .carrier_report = true,
341 .carrier = carrier,
342 .duty_cycle = duty_cycle
343 };
344 ir_raw_event_store(dev->rdev, &ev);
345 }
346}
347
348
349static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable)
350{
351 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
352 ENE_CIRCFG_RX_EN | ENE_CIRCFG_RX_IRQ, enable);
353}
354
355
356static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a)
357{
358 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
359}
360
361
362
363
364
365static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable)
366{
367 if (!dev->hw_fan_input)
368 return;
369
370 if (!enable)
371 ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
372 else {
373 ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
374 ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
375 }
376}
377
378
379static void ene_rx_setup(struct ene_device *dev)
380{
381 bool learning_mode = dev->learning_mode_enabled ||
382 dev->carrier_detect_enabled;
383 int sample_period_adjust = 0;
384
385 dbg("RX: setup receiver, learning mode = %d", learning_mode);
386
387
388
389 ene_write_reg(dev, ENE_CIRCFG2, 0x00);
390
391
392 if (sample_period == ENE_DEFAULT_SAMPLE_PERIOD)
393 sample_period_adjust =
394 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
395
396 ene_write_reg(dev, ENE_CIRRLC_CFG,
397 (sample_period + sample_period_adjust) |
398 ENE_CIRRLC_CFG_OVERFLOW);
399
400 if (dev->hw_revision < ENE_HW_C)
401 goto select_timeout;
402
403 if (learning_mode) {
404
405 WARN_ON(!dev->hw_learning_and_tx_capable);
406
407
408
409
410
411
412 ene_rx_select_input(dev, !dev->hw_use_gpio_0a);
413 dev->rx_fan_input_inuse = false;
414
415
416 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
417
418
419 ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
420 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
421 dev->carrier_detect_enabled || debug);
422 } else {
423 if (dev->hw_fan_input)
424 dev->rx_fan_input_inuse = true;
425 else
426 ene_rx_select_input(dev, dev->hw_use_gpio_0a);
427
428
429 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
430 ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
431 }
432
433select_timeout:
434 if (dev->rx_fan_input_inuse) {
435 dev->rdev->rx_resolution = ENE_FW_SAMPLE_PERIOD_FAN;
436
437
438
439 dev->rdev->min_timeout = dev->rdev->max_timeout =
440 ENE_FW_SMPL_BUF_FAN_MSK *
441 ENE_FW_SAMPLE_PERIOD_FAN;
442 } else {
443 dev->rdev->rx_resolution = sample_period;
444
445
446
447
448
449
450 dev->rdev->min_timeout = 127 * sample_period;
451 dev->rdev->max_timeout = 200000;
452 }
453
454 if (dev->hw_learning_and_tx_capable)
455 dev->rdev->tx_resolution = sample_period;
456
457 if (dev->rdev->timeout > dev->rdev->max_timeout)
458 dev->rdev->timeout = dev->rdev->max_timeout;
459 if (dev->rdev->timeout < dev->rdev->min_timeout)
460 dev->rdev->timeout = dev->rdev->min_timeout;
461}
462
463
464static void ene_rx_enable_hw(struct ene_device *dev)
465{
466 u8 reg_value;
467
468
469 if (dev->hw_revision < ENE_HW_C) {
470 ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
471 ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
472 } else {
473 reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
474 reg_value |= ENE_IRQ_UNK_EN;
475 reg_value &= ~ENE_IRQ_STATUS;
476 reg_value |= (dev->irq & ENE_IRQ_MASK);
477 ene_write_reg(dev, ENE_IRQ, reg_value);
478 }
479
480
481 ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse);
482 ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse);
483
484
485 ene_irq_status(dev);
486
487
488 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
489
490
491 ir_raw_event_set_idle(dev->rdev, true);
492}
493
494
495static void ene_rx_enable(struct ene_device *dev)
496{
497 ene_rx_enable_hw(dev);
498 dev->rx_enabled = true;
499}
500
501
502static void ene_rx_disable_hw(struct ene_device *dev)
503{
504
505 ene_rx_enable_cir_engine(dev, false);
506 ene_rx_enable_fan_input(dev, false);
507
508
509 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
510 ir_raw_event_set_idle(dev->rdev, true);
511}
512
513
514static void ene_rx_disable(struct ene_device *dev)
515{
516 ene_rx_disable_hw(dev);
517 dev->rx_enabled = false;
518}
519
520
521
522
523static void ene_rx_reset(struct ene_device *dev)
524{
525 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
526 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
527}
528
529
530static void ene_tx_set_carrier(struct ene_device *dev)
531{
532 u8 tx_puls_width;
533 unsigned long flags;
534
535 spin_lock_irqsave(&dev->hw_lock, flags);
536
537 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
538 ENE_CIRCFG_TX_CARR, dev->tx_period > 0);
539
540 if (!dev->tx_period)
541 goto unlock;
542
543 BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0);
544
545 tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
546
547 if (!tx_puls_width)
548 tx_puls_width = 1;
549
550 dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
551 dbg("TX: pulse width = %d * 500 ns", tx_puls_width);
552
553 ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
554 ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
555unlock:
556 spin_unlock_irqrestore(&dev->hw_lock, flags);
557}
558
559
560static void ene_tx_set_transmitters(struct ene_device *dev)
561{
562 unsigned long flags;
563
564 spin_lock_irqsave(&dev->hw_lock, flags);
565 ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
566 !!(dev->transmitter_mask & 0x01));
567 ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
568 !!(dev->transmitter_mask & 0x02));
569 spin_unlock_irqrestore(&dev->hw_lock, flags);
570}
571
572
573static void ene_tx_enable(struct ene_device *dev)
574{
575 u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
576 u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
577
578 dev->saved_conf1 = conf1;
579
580
581 if (fwreg2 & ENE_FW2_EMMITER1_CONN)
582 dbg("TX: Transmitter #1 is connected");
583
584 if (fwreg2 & ENE_FW2_EMMITER2_CONN)
585 dbg("TX: Transmitter #2 is connected");
586
587 if (!(fwreg2 & (ENE_FW2_EMMITER1_CONN | ENE_FW2_EMMITER2_CONN)))
588 pr_warn("TX: transmitter cable isn't connected!\n");
589
590
591 if (dev->hw_revision == ENE_HW_C)
592 conf1 &= ~ENE_CIRCFG_RX_EN;
593
594
595 conf1 |= ENE_CIRCFG_TX_EN | ENE_CIRCFG_TX_IRQ;
596 ene_write_reg(dev, ENE_CIRCFG, conf1);
597}
598
599
600static void ene_tx_disable(struct ene_device *dev)
601{
602 ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
603 dev->tx_buffer = NULL;
604}
605
606
607
608static void ene_tx_sample(struct ene_device *dev)
609{
610 u8 raw_tx;
611 u32 sample;
612 bool pulse = dev->tx_sample_pulse;
613
614 if (!dev->tx_buffer) {
615 pr_warn("TX: BUG: attempt to transmit NULL buffer\n");
616 return;
617 }
618
619
620 if (!dev->tx_sample) {
621
622 if (dev->tx_pos == dev->tx_len) {
623 if (!dev->tx_done) {
624 dbg("TX: no more data to send");
625 dev->tx_done = true;
626 goto exit;
627 } else {
628 dbg("TX: last sample sent by hardware");
629 ene_tx_disable(dev);
630 complete(&dev->tx_complete);
631 return;
632 }
633 }
634
635 sample = dev->tx_buffer[dev->tx_pos++];
636 dev->tx_sample_pulse = !dev->tx_sample_pulse;
637
638 dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
639
640 if (!dev->tx_sample)
641 dev->tx_sample = 1;
642 }
643
644 raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
645 dev->tx_sample -= raw_tx;
646
647 dbg("TX: sample %8d (%s)", raw_tx * sample_period,
648 pulse ? "pulse" : "space");
649 if (pulse)
650 raw_tx |= ENE_CIRRLC_OUT_PULSE;
651
652 ene_write_reg(dev,
653 dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
654
655 dev->tx_reg = !dev->tx_reg;
656exit:
657
658 if (txsim)
659 mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
660}
661
662
663static void ene_tx_irqsim(struct timer_list *t)
664{
665 struct ene_device *dev = from_timer(dev, t, tx_sim_timer);
666 unsigned long flags;
667
668 spin_lock_irqsave(&dev->hw_lock, flags);
669 ene_tx_sample(dev);
670 spin_unlock_irqrestore(&dev->hw_lock, flags);
671}
672
673
674
675static int ene_irq_status(struct ene_device *dev)
676{
677 u8 irq_status;
678 u8 fw_flags1, fw_flags2;
679 int retval = 0;
680
681 fw_flags2 = ene_read_reg(dev, ENE_FW2);
682
683 if (dev->hw_revision < ENE_HW_C) {
684 irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
685
686 if (!(irq_status & ENEB_IRQ_STATUS_IR))
687 return 0;
688
689 ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
690 return ENE_IRQ_RX;
691 }
692
693 irq_status = ene_read_reg(dev, ENE_IRQ);
694 if (!(irq_status & ENE_IRQ_STATUS))
695 return 0;
696
697
698 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
699 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
700
701
702 if (fw_flags2 & ENE_FW2_RXIRQ) {
703 retval |= ENE_IRQ_RX;
704 ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
705 }
706
707
708 fw_flags1 = ene_read_reg(dev, ENE_FW1);
709 if (fw_flags1 & ENE_FW1_TXIRQ) {
710 ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
711 retval |= ENE_IRQ_TX;
712 }
713
714 return retval;
715}
716
717
718static irqreturn_t ene_isr(int irq, void *data)
719{
720 u16 hw_value, reg;
721 int hw_sample, irq_status;
722 bool pulse;
723 unsigned long flags;
724 irqreturn_t retval = IRQ_NONE;
725 struct ene_device *dev = (struct ene_device *)data;
726 struct ir_raw_event ev = {};
727
728 spin_lock_irqsave(&dev->hw_lock, flags);
729
730 dbg_verbose("ISR called");
731 ene_rx_read_hw_pointer(dev);
732 irq_status = ene_irq_status(dev);
733
734 if (!irq_status)
735 goto unlock;
736
737 retval = IRQ_HANDLED;
738
739 if (irq_status & ENE_IRQ_TX) {
740 dbg_verbose("TX interrupt");
741 if (!dev->hw_learning_and_tx_capable) {
742 dbg("TX interrupt on unsupported device!");
743 goto unlock;
744 }
745 ene_tx_sample(dev);
746 }
747
748 if (!(irq_status & ENE_IRQ_RX))
749 goto unlock;
750
751 dbg_verbose("RX interrupt");
752
753 if (dev->hw_learning_and_tx_capable)
754 ene_rx_sense_carrier(dev);
755
756
757
758 if (!dev->hw_extra_buffer)
759 dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
760
761 while (1) {
762
763 reg = ene_rx_get_sample_reg(dev);
764
765 dbg_verbose("next sample to read at: %04x", reg);
766 if (!reg)
767 break;
768
769 hw_value = ene_read_reg(dev, reg);
770
771 if (dev->rx_fan_input_inuse) {
772
773 int offset = ENE_FW_SMPL_BUF_FAN - ENE_FW_SAMPLE_BUFFER;
774
775
776 hw_value |= ene_read_reg(dev, reg + offset) << 8;
777 pulse = hw_value & ENE_FW_SMPL_BUF_FAN_PLS;
778
779
780 hw_value &= ENE_FW_SMPL_BUF_FAN_MSK;
781 hw_sample = hw_value * ENE_FW_SAMPLE_PERIOD_FAN;
782
783 } else {
784 pulse = !(hw_value & ENE_FW_SAMPLE_SPACE);
785 hw_value &= ~ENE_FW_SAMPLE_SPACE;
786 hw_sample = hw_value * sample_period;
787
788 if (dev->rx_period_adjust) {
789 hw_sample *= 100;
790 hw_sample /= (100 + dev->rx_period_adjust);
791 }
792 }
793
794 if (!dev->hw_extra_buffer && !hw_sample) {
795 dev->r_pointer = dev->w_pointer;
796 continue;
797 }
798
799 dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space");
800
801 ev.duration = hw_sample;
802 ev.pulse = pulse;
803 ir_raw_event_store_with_filter(dev->rdev, &ev);
804 }
805
806 ir_raw_event_handle(dev->rdev);
807unlock:
808 spin_unlock_irqrestore(&dev->hw_lock, flags);
809 return retval;
810}
811
812
813static void ene_setup_default_settings(struct ene_device *dev)
814{
815 dev->tx_period = 32;
816 dev->tx_duty_cycle = 50;
817 dev->transmitter_mask = 0x03;
818 dev->learning_mode_enabled = learning_mode_force;
819
820
821 dev->rdev->timeout = MS_TO_US(150);
822}
823
824
825static void ene_setup_hw_settings(struct ene_device *dev)
826{
827 if (dev->hw_learning_and_tx_capable) {
828 ene_tx_set_carrier(dev);
829 ene_tx_set_transmitters(dev);
830 }
831
832 ene_rx_setup(dev);
833}
834
835
836static int ene_open(struct rc_dev *rdev)
837{
838 struct ene_device *dev = rdev->priv;
839 unsigned long flags;
840
841 spin_lock_irqsave(&dev->hw_lock, flags);
842 ene_rx_enable(dev);
843 spin_unlock_irqrestore(&dev->hw_lock, flags);
844 return 0;
845}
846
847
848static void ene_close(struct rc_dev *rdev)
849{
850 struct ene_device *dev = rdev->priv;
851 unsigned long flags;
852 spin_lock_irqsave(&dev->hw_lock, flags);
853
854 ene_rx_disable(dev);
855 spin_unlock_irqrestore(&dev->hw_lock, flags);
856}
857
858
859static int ene_set_tx_mask(struct rc_dev *rdev, u32 tx_mask)
860{
861 struct ene_device *dev = rdev->priv;
862 dbg("TX: attempt to set transmitter mask %02x", tx_mask);
863
864
865 if (!tx_mask || tx_mask & ~0x03) {
866 dbg("TX: invalid mask");
867
868 return 2;
869 }
870
871 dev->transmitter_mask = tx_mask;
872 ene_tx_set_transmitters(dev);
873 return 0;
874}
875
876
877static int ene_set_tx_carrier(struct rc_dev *rdev, u32 carrier)
878{
879 struct ene_device *dev = rdev->priv;
880 u32 period;
881
882 dbg("TX: attempt to set tx carrier to %d kHz", carrier);
883 if (carrier == 0)
884 return -EINVAL;
885
886 period = 2000000 / carrier;
887 if (period && (period > ENE_CIRMOD_PRD_MAX ||
888 period < ENE_CIRMOD_PRD_MIN)) {
889
890 dbg("TX: out of range %d-%d kHz carrier",
891 2000 / ENE_CIRMOD_PRD_MIN, 2000 / ENE_CIRMOD_PRD_MAX);
892 return -EINVAL;
893 }
894
895 dev->tx_period = period;
896 ene_tx_set_carrier(dev);
897 return 0;
898}
899
900
901static int ene_set_tx_duty_cycle(struct rc_dev *rdev, u32 duty_cycle)
902{
903 struct ene_device *dev = rdev->priv;
904 dbg("TX: setting duty cycle to %d%%", duty_cycle);
905 dev->tx_duty_cycle = duty_cycle;
906 ene_tx_set_carrier(dev);
907 return 0;
908}
909
910
911static int ene_set_learning_mode(struct rc_dev *rdev, int enable)
912{
913 struct ene_device *dev = rdev->priv;
914 unsigned long flags;
915 if (enable == dev->learning_mode_enabled)
916 return 0;
917
918 spin_lock_irqsave(&dev->hw_lock, flags);
919 dev->learning_mode_enabled = enable;
920 ene_rx_disable(dev);
921 ene_rx_setup(dev);
922 ene_rx_enable(dev);
923 spin_unlock_irqrestore(&dev->hw_lock, flags);
924 return 0;
925}
926
927static int ene_set_carrier_report(struct rc_dev *rdev, int enable)
928{
929 struct ene_device *dev = rdev->priv;
930 unsigned long flags;
931
932 if (enable == dev->carrier_detect_enabled)
933 return 0;
934
935 spin_lock_irqsave(&dev->hw_lock, flags);
936 dev->carrier_detect_enabled = enable;
937 ene_rx_disable(dev);
938 ene_rx_setup(dev);
939 ene_rx_enable(dev);
940 spin_unlock_irqrestore(&dev->hw_lock, flags);
941 return 0;
942}
943
944
945static void ene_set_idle(struct rc_dev *rdev, bool idle)
946{
947 struct ene_device *dev = rdev->priv;
948
949 if (idle) {
950 ene_rx_reset(dev);
951 dbg("RX: end of data");
952 }
953}
954
955
956static int ene_transmit(struct rc_dev *rdev, unsigned *buf, unsigned n)
957{
958 struct ene_device *dev = rdev->priv;
959 unsigned long flags;
960
961 dev->tx_buffer = buf;
962 dev->tx_len = n;
963 dev->tx_pos = 0;
964 dev->tx_reg = 0;
965 dev->tx_done = 0;
966 dev->tx_sample = 0;
967 dev->tx_sample_pulse = false;
968
969 dbg("TX: %d samples", dev->tx_len);
970
971 spin_lock_irqsave(&dev->hw_lock, flags);
972
973 ene_tx_enable(dev);
974
975
976 ene_tx_sample(dev);
977 ene_tx_sample(dev);
978
979 spin_unlock_irqrestore(&dev->hw_lock, flags);
980
981 if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
982 dbg("TX: timeout");
983 spin_lock_irqsave(&dev->hw_lock, flags);
984 ene_tx_disable(dev);
985 spin_unlock_irqrestore(&dev->hw_lock, flags);
986 } else
987 dbg("TX: done");
988 return n;
989}
990
991
992static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
993{
994 int error = -ENOMEM;
995 struct rc_dev *rdev;
996 struct ene_device *dev;
997
998
999 dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
1000 rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
1001 if (!dev || !rdev)
1002 goto exit_free_dev_rdev;
1003
1004
1005 error = -ENODEV;
1006
1007
1008 dev->hw_io = -1;
1009 dev->irq = -1;
1010
1011 if (!pnp_port_valid(pnp_dev, 0) ||
1012 pnp_port_len(pnp_dev, 0) < ENE_IO_SIZE)
1013 goto exit_free_dev_rdev;
1014
1015 if (!pnp_irq_valid(pnp_dev, 0))
1016 goto exit_free_dev_rdev;
1017
1018 spin_lock_init(&dev->hw_lock);
1019
1020 dev->hw_io = pnp_port_start(pnp_dev, 0);
1021 dev->irq = pnp_irq(pnp_dev, 0);
1022
1023
1024 pnp_set_drvdata(pnp_dev, dev);
1025 dev->pnp_dev = pnp_dev;
1026
1027
1028 if (sample_period < 5 || sample_period > 0x7F)
1029 sample_period = ENE_DEFAULT_SAMPLE_PERIOD;
1030
1031
1032 error = ene_hw_detect(dev);
1033 if (error)
1034 goto exit_free_dev_rdev;
1035
1036 if (!dev->hw_learning_and_tx_capable && txsim) {
1037 dev->hw_learning_and_tx_capable = true;
1038 timer_setup(&dev->tx_sim_timer, ene_tx_irqsim, 0);
1039 pr_warn("Simulation of TX activated\n");
1040 }
1041
1042 if (!dev->hw_learning_and_tx_capable)
1043 learning_mode_force = false;
1044
1045 rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
1046 rdev->priv = dev;
1047 rdev->open = ene_open;
1048 rdev->close = ene_close;
1049 rdev->s_idle = ene_set_idle;
1050 rdev->driver_name = ENE_DRIVER_NAME;
1051 rdev->map_name = RC_MAP_RC6_MCE;
1052 rdev->device_name = "ENE eHome Infrared Remote Receiver";
1053
1054 if (dev->hw_learning_and_tx_capable) {
1055 rdev->s_learning_mode = ene_set_learning_mode;
1056 init_completion(&dev->tx_complete);
1057 rdev->tx_ir = ene_transmit;
1058 rdev->s_tx_mask = ene_set_tx_mask;
1059 rdev->s_tx_carrier = ene_set_tx_carrier;
1060 rdev->s_tx_duty_cycle = ene_set_tx_duty_cycle;
1061 rdev->s_carrier_report = ene_set_carrier_report;
1062 rdev->device_name = "ENE eHome Infrared Remote Transceiver";
1063 }
1064
1065 dev->rdev = rdev;
1066
1067 ene_rx_setup_hw_buffer(dev);
1068 ene_setup_default_settings(dev);
1069 ene_setup_hw_settings(dev);
1070
1071 device_set_wakeup_capable(&pnp_dev->dev, true);
1072 device_set_wakeup_enable(&pnp_dev->dev, true);
1073
1074 error = rc_register_device(rdev);
1075 if (error < 0)
1076 goto exit_free_dev_rdev;
1077
1078
1079 error = -EBUSY;
1080 if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
1081 goto exit_unregister_device;
1082 }
1083
1084 if (request_irq(dev->irq, ene_isr,
1085 IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
1086 goto exit_release_hw_io;
1087 }
1088
1089 pr_notice("driver has been successfully loaded\n");
1090 return 0;
1091
1092exit_release_hw_io:
1093 release_region(dev->hw_io, ENE_IO_SIZE);
1094exit_unregister_device:
1095 rc_unregister_device(rdev);
1096 rdev = NULL;
1097exit_free_dev_rdev:
1098 rc_free_device(rdev);
1099 kfree(dev);
1100 return error;
1101}
1102
1103
1104static void ene_remove(struct pnp_dev *pnp_dev)
1105{
1106 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1107 unsigned long flags;
1108
1109 spin_lock_irqsave(&dev->hw_lock, flags);
1110 ene_rx_disable(dev);
1111 ene_rx_restore_hw_buffer(dev);
1112 spin_unlock_irqrestore(&dev->hw_lock, flags);
1113
1114 free_irq(dev->irq, dev);
1115 release_region(dev->hw_io, ENE_IO_SIZE);
1116 rc_unregister_device(dev->rdev);
1117 kfree(dev);
1118}
1119
1120
1121static void ene_enable_wake(struct ene_device *dev, bool enable)
1122{
1123 dbg("wake on IR %s", enable ? "enabled" : "disabled");
1124 ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
1125}
1126
1127#ifdef CONFIG_PM
1128static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state)
1129{
1130 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1131 bool wake = device_may_wakeup(&dev->pnp_dev->dev);
1132
1133 if (!wake && dev->rx_enabled)
1134 ene_rx_disable_hw(dev);
1135
1136 ene_enable_wake(dev, wake);
1137 return 0;
1138}
1139
1140static int ene_resume(struct pnp_dev *pnp_dev)
1141{
1142 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1143 ene_setup_hw_settings(dev);
1144
1145 if (dev->rx_enabled)
1146 ene_rx_enable(dev);
1147
1148 ene_enable_wake(dev, false);
1149 return 0;
1150}
1151#endif
1152
1153static void ene_shutdown(struct pnp_dev *pnp_dev)
1154{
1155 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1156 ene_enable_wake(dev, true);
1157}
1158
1159static const struct pnp_device_id ene_ids[] = {
1160 {.id = "ENE0100",},
1161 {.id = "ENE0200",},
1162 {.id = "ENE0201",},
1163 {.id = "ENE0202",},
1164 {},
1165};
1166
1167static struct pnp_driver ene_driver = {
1168 .name = ENE_DRIVER_NAME,
1169 .id_table = ene_ids,
1170 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1171
1172 .probe = ene_probe,
1173 .remove = ene_remove,
1174#ifdef CONFIG_PM
1175 .suspend = ene_suspend,
1176 .resume = ene_resume,
1177#endif
1178 .shutdown = ene_shutdown,
1179};
1180
1181module_param(sample_period, int, S_IRUGO);
1182MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)");
1183
1184module_param(learning_mode_force, bool, S_IRUGO);
1185MODULE_PARM_DESC(learning_mode_force, "Enable learning mode by default");
1186
1187module_param(debug, int, S_IRUGO | S_IWUSR);
1188MODULE_PARM_DESC(debug, "Debug level");
1189
1190module_param(txsim, bool, S_IRUGO);
1191MODULE_PARM_DESC(txsim,
1192 "Simulate TX features on unsupported hardware (dangerous)");
1193
1194MODULE_DEVICE_TABLE(pnp, ene_ids);
1195MODULE_DESCRIPTION
1196 ("Infrared input driver for KB3926B/C/D/E/F (aka ENE0100/ENE0200/ENE0201/ENE0202) CIR port");
1197
1198MODULE_AUTHOR("Maxim Levitsky");
1199MODULE_LICENSE("GPL");
1200
1201module_pnp_driver(ene_driver);
1202
