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8#include "goyaP.h"
9#include "../include/goya/goya_coresight.h"
10#include "../include/goya/asic_reg/goya_regs.h"
11#include "../include/goya/asic_reg/goya_masks.h"
12
13#include <uapi/misc/habanalabs.h>
14
15#include <linux/coresight.h>
16
17#define GOYA_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 100)
18
19#define SPMU_SECTION_SIZE DMA_CH_0_CS_SPMU_MAX_OFFSET
20#define SPMU_EVENT_TYPES_OFFSET 0x400
21#define SPMU_MAX_COUNTERS 6
22
23static u64 debug_stm_regs[GOYA_STM_LAST + 1] = {
24 [GOYA_STM_CPU] = mmCPU_STM_BASE,
25 [GOYA_STM_DMA_CH_0_CS] = mmDMA_CH_0_CS_STM_BASE,
26 [GOYA_STM_DMA_CH_1_CS] = mmDMA_CH_1_CS_STM_BASE,
27 [GOYA_STM_DMA_CH_2_CS] = mmDMA_CH_2_CS_STM_BASE,
28 [GOYA_STM_DMA_CH_3_CS] = mmDMA_CH_3_CS_STM_BASE,
29 [GOYA_STM_DMA_CH_4_CS] = mmDMA_CH_4_CS_STM_BASE,
30 [GOYA_STM_DMA_MACRO_CS] = mmDMA_MACRO_CS_STM_BASE,
31 [GOYA_STM_MME1_SBA] = mmMME1_SBA_STM_BASE,
32 [GOYA_STM_MME3_SBB] = mmMME3_SBB_STM_BASE,
33 [GOYA_STM_MME4_WACS2] = mmMME4_WACS2_STM_BASE,
34 [GOYA_STM_MME4_WACS] = mmMME4_WACS_STM_BASE,
35 [GOYA_STM_MMU_CS] = mmMMU_CS_STM_BASE,
36 [GOYA_STM_PCIE] = mmPCIE_STM_BASE,
37 [GOYA_STM_PSOC] = mmPSOC_STM_BASE,
38 [GOYA_STM_TPC0_EML] = mmTPC0_EML_STM_BASE,
39 [GOYA_STM_TPC1_EML] = mmTPC1_EML_STM_BASE,
40 [GOYA_STM_TPC2_EML] = mmTPC2_EML_STM_BASE,
41 [GOYA_STM_TPC3_EML] = mmTPC3_EML_STM_BASE,
42 [GOYA_STM_TPC4_EML] = mmTPC4_EML_STM_BASE,
43 [GOYA_STM_TPC5_EML] = mmTPC5_EML_STM_BASE,
44 [GOYA_STM_TPC6_EML] = mmTPC6_EML_STM_BASE,
45 [GOYA_STM_TPC7_EML] = mmTPC7_EML_STM_BASE
46};
47
48static u64 debug_etf_regs[GOYA_ETF_LAST + 1] = {
49 [GOYA_ETF_CPU_0] = mmCPU_ETF_0_BASE,
50 [GOYA_ETF_CPU_1] = mmCPU_ETF_1_BASE,
51 [GOYA_ETF_CPU_TRACE] = mmCPU_ETF_TRACE_BASE,
52 [GOYA_ETF_DMA_CH_0_CS] = mmDMA_CH_0_CS_ETF_BASE,
53 [GOYA_ETF_DMA_CH_1_CS] = mmDMA_CH_1_CS_ETF_BASE,
54 [GOYA_ETF_DMA_CH_2_CS] = mmDMA_CH_2_CS_ETF_BASE,
55 [GOYA_ETF_DMA_CH_3_CS] = mmDMA_CH_3_CS_ETF_BASE,
56 [GOYA_ETF_DMA_CH_4_CS] = mmDMA_CH_4_CS_ETF_BASE,
57 [GOYA_ETF_DMA_MACRO_CS] = mmDMA_MACRO_CS_ETF_BASE,
58 [GOYA_ETF_MME1_SBA] = mmMME1_SBA_ETF_BASE,
59 [GOYA_ETF_MME3_SBB] = mmMME3_SBB_ETF_BASE,
60 [GOYA_ETF_MME4_WACS2] = mmMME4_WACS2_ETF_BASE,
61 [GOYA_ETF_MME4_WACS] = mmMME4_WACS_ETF_BASE,
62 [GOYA_ETF_MMU_CS] = mmMMU_CS_ETF_BASE,
63 [GOYA_ETF_PCIE] = mmPCIE_ETF_BASE,
64 [GOYA_ETF_PSOC] = mmPSOC_ETF_BASE,
65 [GOYA_ETF_TPC0_EML] = mmTPC0_EML_ETF_BASE,
66 [GOYA_ETF_TPC1_EML] = mmTPC1_EML_ETF_BASE,
67 [GOYA_ETF_TPC2_EML] = mmTPC2_EML_ETF_BASE,
68 [GOYA_ETF_TPC3_EML] = mmTPC3_EML_ETF_BASE,
69 [GOYA_ETF_TPC4_EML] = mmTPC4_EML_ETF_BASE,
70 [GOYA_ETF_TPC5_EML] = mmTPC5_EML_ETF_BASE,
71 [GOYA_ETF_TPC6_EML] = mmTPC6_EML_ETF_BASE,
72 [GOYA_ETF_TPC7_EML] = mmTPC7_EML_ETF_BASE
73};
74
75static u64 debug_funnel_regs[GOYA_FUNNEL_LAST + 1] = {
76 [GOYA_FUNNEL_CPU] = mmCPU_FUNNEL_BASE,
77 [GOYA_FUNNEL_DMA_CH_6_1] = mmDMA_CH_FUNNEL_6_1_BASE,
78 [GOYA_FUNNEL_DMA_MACRO_3_1] = mmDMA_MACRO_FUNNEL_3_1_BASE,
79 [GOYA_FUNNEL_MME0_RTR] = mmMME0_RTR_FUNNEL_BASE,
80 [GOYA_FUNNEL_MME1_RTR] = mmMME1_RTR_FUNNEL_BASE,
81 [GOYA_FUNNEL_MME2_RTR] = mmMME2_RTR_FUNNEL_BASE,
82 [GOYA_FUNNEL_MME3_RTR] = mmMME3_RTR_FUNNEL_BASE,
83 [GOYA_FUNNEL_MME4_RTR] = mmMME4_RTR_FUNNEL_BASE,
84 [GOYA_FUNNEL_MME5_RTR] = mmMME5_RTR_FUNNEL_BASE,
85 [GOYA_FUNNEL_PCIE] = mmPCIE_FUNNEL_BASE,
86 [GOYA_FUNNEL_PSOC] = mmPSOC_FUNNEL_BASE,
87 [GOYA_FUNNEL_TPC0_EML] = mmTPC0_EML_FUNNEL_BASE,
88 [GOYA_FUNNEL_TPC1_EML] = mmTPC1_EML_FUNNEL_BASE,
89 [GOYA_FUNNEL_TPC1_RTR] = mmTPC1_RTR_FUNNEL_BASE,
90 [GOYA_FUNNEL_TPC2_EML] = mmTPC2_EML_FUNNEL_BASE,
91 [GOYA_FUNNEL_TPC2_RTR] = mmTPC2_RTR_FUNNEL_BASE,
92 [GOYA_FUNNEL_TPC3_EML] = mmTPC3_EML_FUNNEL_BASE,
93 [GOYA_FUNNEL_TPC3_RTR] = mmTPC3_RTR_FUNNEL_BASE,
94 [GOYA_FUNNEL_TPC4_EML] = mmTPC4_EML_FUNNEL_BASE,
95 [GOYA_FUNNEL_TPC4_RTR] = mmTPC4_RTR_FUNNEL_BASE,
96 [GOYA_FUNNEL_TPC5_EML] = mmTPC5_EML_FUNNEL_BASE,
97 [GOYA_FUNNEL_TPC5_RTR] = mmTPC5_RTR_FUNNEL_BASE,
98 [GOYA_FUNNEL_TPC6_EML] = mmTPC6_EML_FUNNEL_BASE,
99 [GOYA_FUNNEL_TPC6_RTR] = mmTPC6_RTR_FUNNEL_BASE,
100 [GOYA_FUNNEL_TPC7_EML] = mmTPC7_EML_FUNNEL_BASE
101};
102
103static u64 debug_bmon_regs[GOYA_BMON_LAST + 1] = {
104 [GOYA_BMON_CPU_RD] = mmCPU_RD_BMON_BASE,
105 [GOYA_BMON_CPU_WR] = mmCPU_WR_BMON_BASE,
106 [GOYA_BMON_DMA_CH_0_0] = mmDMA_CH_0_BMON_0_BASE,
107 [GOYA_BMON_DMA_CH_0_1] = mmDMA_CH_0_BMON_1_BASE,
108 [GOYA_BMON_DMA_CH_1_0] = mmDMA_CH_1_BMON_0_BASE,
109 [GOYA_BMON_DMA_CH_1_1] = mmDMA_CH_1_BMON_1_BASE,
110 [GOYA_BMON_DMA_CH_2_0] = mmDMA_CH_2_BMON_0_BASE,
111 [GOYA_BMON_DMA_CH_2_1] = mmDMA_CH_2_BMON_1_BASE,
112 [GOYA_BMON_DMA_CH_3_0] = mmDMA_CH_3_BMON_0_BASE,
113 [GOYA_BMON_DMA_CH_3_1] = mmDMA_CH_3_BMON_1_BASE,
114 [GOYA_BMON_DMA_CH_4_0] = mmDMA_CH_4_BMON_0_BASE,
115 [GOYA_BMON_DMA_CH_4_1] = mmDMA_CH_4_BMON_1_BASE,
116 [GOYA_BMON_DMA_MACRO_0] = mmDMA_MACRO_BMON_0_BASE,
117 [GOYA_BMON_DMA_MACRO_1] = mmDMA_MACRO_BMON_1_BASE,
118 [GOYA_BMON_DMA_MACRO_2] = mmDMA_MACRO_BMON_2_BASE,
119 [GOYA_BMON_DMA_MACRO_3] = mmDMA_MACRO_BMON_3_BASE,
120 [GOYA_BMON_DMA_MACRO_4] = mmDMA_MACRO_BMON_4_BASE,
121 [GOYA_BMON_DMA_MACRO_5] = mmDMA_MACRO_BMON_5_BASE,
122 [GOYA_BMON_DMA_MACRO_6] = mmDMA_MACRO_BMON_6_BASE,
123 [GOYA_BMON_DMA_MACRO_7] = mmDMA_MACRO_BMON_7_BASE,
124 [GOYA_BMON_MME1_SBA_0] = mmMME1_SBA_BMON0_BASE,
125 [GOYA_BMON_MME1_SBA_1] = mmMME1_SBA_BMON1_BASE,
126 [GOYA_BMON_MME3_SBB_0] = mmMME3_SBB_BMON0_BASE,
127 [GOYA_BMON_MME3_SBB_1] = mmMME3_SBB_BMON1_BASE,
128 [GOYA_BMON_MME4_WACS2_0] = mmMME4_WACS2_BMON0_BASE,
129 [GOYA_BMON_MME4_WACS2_1] = mmMME4_WACS2_BMON1_BASE,
130 [GOYA_BMON_MME4_WACS2_2] = mmMME4_WACS2_BMON2_BASE,
131 [GOYA_BMON_MME4_WACS_0] = mmMME4_WACS_BMON0_BASE,
132 [GOYA_BMON_MME4_WACS_1] = mmMME4_WACS_BMON1_BASE,
133 [GOYA_BMON_MME4_WACS_2] = mmMME4_WACS_BMON2_BASE,
134 [GOYA_BMON_MME4_WACS_3] = mmMME4_WACS_BMON3_BASE,
135 [GOYA_BMON_MME4_WACS_4] = mmMME4_WACS_BMON4_BASE,
136 [GOYA_BMON_MME4_WACS_5] = mmMME4_WACS_BMON5_BASE,
137 [GOYA_BMON_MME4_WACS_6] = mmMME4_WACS_BMON6_BASE,
138 [GOYA_BMON_MMU_0] = mmMMU_BMON_0_BASE,
139 [GOYA_BMON_MMU_1] = mmMMU_BMON_1_BASE,
140 [GOYA_BMON_PCIE_MSTR_RD] = mmPCIE_BMON_MSTR_RD_BASE,
141 [GOYA_BMON_PCIE_MSTR_WR] = mmPCIE_BMON_MSTR_WR_BASE,
142 [GOYA_BMON_PCIE_SLV_RD] = mmPCIE_BMON_SLV_RD_BASE,
143 [GOYA_BMON_PCIE_SLV_WR] = mmPCIE_BMON_SLV_WR_BASE,
144 [GOYA_BMON_TPC0_EML_0] = mmTPC0_EML_BUSMON_0_BASE,
145 [GOYA_BMON_TPC0_EML_1] = mmTPC0_EML_BUSMON_1_BASE,
146 [GOYA_BMON_TPC0_EML_2] = mmTPC0_EML_BUSMON_2_BASE,
147 [GOYA_BMON_TPC0_EML_3] = mmTPC0_EML_BUSMON_3_BASE,
148 [GOYA_BMON_TPC1_EML_0] = mmTPC1_EML_BUSMON_0_BASE,
149 [GOYA_BMON_TPC1_EML_1] = mmTPC1_EML_BUSMON_1_BASE,
150 [GOYA_BMON_TPC1_EML_2] = mmTPC1_EML_BUSMON_2_BASE,
151 [GOYA_BMON_TPC1_EML_3] = mmTPC1_EML_BUSMON_3_BASE,
152 [GOYA_BMON_TPC2_EML_0] = mmTPC2_EML_BUSMON_0_BASE,
153 [GOYA_BMON_TPC2_EML_1] = mmTPC2_EML_BUSMON_1_BASE,
154 [GOYA_BMON_TPC2_EML_2] = mmTPC2_EML_BUSMON_2_BASE,
155 [GOYA_BMON_TPC2_EML_3] = mmTPC2_EML_BUSMON_3_BASE,
156 [GOYA_BMON_TPC3_EML_0] = mmTPC3_EML_BUSMON_0_BASE,
157 [GOYA_BMON_TPC3_EML_1] = mmTPC3_EML_BUSMON_1_BASE,
158 [GOYA_BMON_TPC3_EML_2] = mmTPC3_EML_BUSMON_2_BASE,
159 [GOYA_BMON_TPC3_EML_3] = mmTPC3_EML_BUSMON_3_BASE,
160 [GOYA_BMON_TPC4_EML_0] = mmTPC4_EML_BUSMON_0_BASE,
161 [GOYA_BMON_TPC4_EML_1] = mmTPC4_EML_BUSMON_1_BASE,
162 [GOYA_BMON_TPC4_EML_2] = mmTPC4_EML_BUSMON_2_BASE,
163 [GOYA_BMON_TPC4_EML_3] = mmTPC4_EML_BUSMON_3_BASE,
164 [GOYA_BMON_TPC5_EML_0] = mmTPC5_EML_BUSMON_0_BASE,
165 [GOYA_BMON_TPC5_EML_1] = mmTPC5_EML_BUSMON_1_BASE,
166 [GOYA_BMON_TPC5_EML_2] = mmTPC5_EML_BUSMON_2_BASE,
167 [GOYA_BMON_TPC5_EML_3] = mmTPC5_EML_BUSMON_3_BASE,
168 [GOYA_BMON_TPC6_EML_0] = mmTPC6_EML_BUSMON_0_BASE,
169 [GOYA_BMON_TPC6_EML_1] = mmTPC6_EML_BUSMON_1_BASE,
170 [GOYA_BMON_TPC6_EML_2] = mmTPC6_EML_BUSMON_2_BASE,
171 [GOYA_BMON_TPC6_EML_3] = mmTPC6_EML_BUSMON_3_BASE,
172 [GOYA_BMON_TPC7_EML_0] = mmTPC7_EML_BUSMON_0_BASE,
173 [GOYA_BMON_TPC7_EML_1] = mmTPC7_EML_BUSMON_1_BASE,
174 [GOYA_BMON_TPC7_EML_2] = mmTPC7_EML_BUSMON_2_BASE,
175 [GOYA_BMON_TPC7_EML_3] = mmTPC7_EML_BUSMON_3_BASE
176};
177
178static u64 debug_spmu_regs[GOYA_SPMU_LAST + 1] = {
179 [GOYA_SPMU_DMA_CH_0_CS] = mmDMA_CH_0_CS_SPMU_BASE,
180 [GOYA_SPMU_DMA_CH_1_CS] = mmDMA_CH_1_CS_SPMU_BASE,
181 [GOYA_SPMU_DMA_CH_2_CS] = mmDMA_CH_2_CS_SPMU_BASE,
182 [GOYA_SPMU_DMA_CH_3_CS] = mmDMA_CH_3_CS_SPMU_BASE,
183 [GOYA_SPMU_DMA_CH_4_CS] = mmDMA_CH_4_CS_SPMU_BASE,
184 [GOYA_SPMU_DMA_MACRO_CS] = mmDMA_MACRO_CS_SPMU_BASE,
185 [GOYA_SPMU_MME1_SBA] = mmMME1_SBA_SPMU_BASE,
186 [GOYA_SPMU_MME3_SBB] = mmMME3_SBB_SPMU_BASE,
187 [GOYA_SPMU_MME4_WACS2] = mmMME4_WACS2_SPMU_BASE,
188 [GOYA_SPMU_MME4_WACS] = mmMME4_WACS_SPMU_BASE,
189 [GOYA_SPMU_MMU_CS] = mmMMU_CS_SPMU_BASE,
190 [GOYA_SPMU_PCIE] = mmPCIE_SPMU_BASE,
191 [GOYA_SPMU_TPC0_EML] = mmTPC0_EML_SPMU_BASE,
192 [GOYA_SPMU_TPC1_EML] = mmTPC1_EML_SPMU_BASE,
193 [GOYA_SPMU_TPC2_EML] = mmTPC2_EML_SPMU_BASE,
194 [GOYA_SPMU_TPC3_EML] = mmTPC3_EML_SPMU_BASE,
195 [GOYA_SPMU_TPC4_EML] = mmTPC4_EML_SPMU_BASE,
196 [GOYA_SPMU_TPC5_EML] = mmTPC5_EML_SPMU_BASE,
197 [GOYA_SPMU_TPC6_EML] = mmTPC6_EML_SPMU_BASE,
198 [GOYA_SPMU_TPC7_EML] = mmTPC7_EML_SPMU_BASE
199};
200
201static int goya_coresight_timeout(struct hl_device *hdev, u64 addr,
202 int position, bool up)
203{
204 int rc;
205 u32 val, timeout_usec;
206
207 if (hdev->pldm)
208 timeout_usec = GOYA_PLDM_CORESIGHT_TIMEOUT_USEC;
209 else
210 timeout_usec = CORESIGHT_TIMEOUT_USEC;
211
212 rc = hl_poll_timeout(
213 hdev,
214 addr,
215 val,
216 up ? val & BIT(position) : !(val & BIT(position)),
217 1000,
218 timeout_usec);
219
220 if (rc) {
221 dev_err(hdev->dev,
222 "Timeout while waiting for coresight, addr: 0x%llx, position: %d, up: %d\n",
223 addr, position, up);
224 return -EFAULT;
225 }
226
227 return 0;
228}
229
230static int goya_config_stm(struct hl_device *hdev,
231 struct hl_debug_params *params)
232{
233 struct hl_debug_params_stm *input;
234 u64 base_reg;
235 u32 frequency;
236 int rc;
237
238 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) {
239 dev_err(hdev->dev, "Invalid register index in STM\n");
240 return -EINVAL;
241 }
242
243 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE;
244
245 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
246
247 if (params->enable) {
248 input = params->input;
249
250 if (!input)
251 return -EINVAL;
252
253 WREG32(base_reg + 0xE80, 0x80004);
254 WREG32(base_reg + 0xD64, 7);
255 WREG32(base_reg + 0xD60, 0);
256 WREG32(base_reg + 0xD00, lower_32_bits(input->he_mask));
257 WREG32(base_reg + 0xD20, lower_32_bits(input->sp_mask));
258 WREG32(base_reg + 0xD60, 1);
259 WREG32(base_reg + 0xD00, upper_32_bits(input->he_mask));
260 WREG32(base_reg + 0xD20, upper_32_bits(input->sp_mask));
261 WREG32(base_reg + 0xE70, 0x10);
262 WREG32(base_reg + 0xE60, 0);
263 WREG32(base_reg + 0xE64, 0x420000);
264 WREG32(base_reg + 0xE00, 0xFFFFFFFF);
265 WREG32(base_reg + 0xE20, 0xFFFFFFFF);
266 WREG32(base_reg + 0xEF4, input->id);
267 WREG32(base_reg + 0xDF4, 0x80);
268 frequency = hdev->asic_prop.psoc_timestamp_frequency;
269 if (frequency == 0)
270 frequency = input->frequency;
271 WREG32(base_reg + 0xE8C, frequency);
272 WREG32(base_reg + 0xE90, 0x7FF);
273 WREG32(base_reg + 0xE80, 0x27 | (input->id << 16));
274 } else {
275 WREG32(base_reg + 0xE80, 4);
276 WREG32(base_reg + 0xD64, 0);
277 WREG32(base_reg + 0xD60, 1);
278 WREG32(base_reg + 0xD00, 0);
279 WREG32(base_reg + 0xD20, 0);
280 WREG32(base_reg + 0xD60, 0);
281 WREG32(base_reg + 0xE20, 0);
282 WREG32(base_reg + 0xE00, 0);
283 WREG32(base_reg + 0xDF4, 0x80);
284 WREG32(base_reg + 0xE70, 0);
285 WREG32(base_reg + 0xE60, 0);
286 WREG32(base_reg + 0xE64, 0);
287 WREG32(base_reg + 0xE8C, 0);
288
289 rc = goya_coresight_timeout(hdev, base_reg + 0xE80, 23, false);
290 if (rc) {
291 dev_err(hdev->dev,
292 "Failed to disable STM on timeout, error %d\n",
293 rc);
294 return rc;
295 }
296
297 WREG32(base_reg + 0xE80, 4);
298 }
299
300 return 0;
301}
302
303static int goya_config_etf(struct hl_device *hdev,
304 struct hl_debug_params *params)
305{
306 struct hl_debug_params_etf *input;
307 u64 base_reg;
308 u32 val;
309 int rc;
310
311 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) {
312 dev_err(hdev->dev, "Invalid register index in ETF\n");
313 return -EINVAL;
314 }
315
316 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE;
317
318 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
319
320 val = RREG32(base_reg + 0x304);
321 val |= 0x1000;
322 WREG32(base_reg + 0x304, val);
323 val |= 0x40;
324 WREG32(base_reg + 0x304, val);
325
326 rc = goya_coresight_timeout(hdev, base_reg + 0x304, 6, false);
327 if (rc) {
328 dev_err(hdev->dev,
329 "Failed to %s ETF on timeout, error %d\n",
330 params->enable ? "enable" : "disable", rc);
331 return rc;
332 }
333
334 rc = goya_coresight_timeout(hdev, base_reg + 0xC, 2, true);
335 if (rc) {
336 dev_err(hdev->dev,
337 "Failed to %s ETF on timeout, error %d\n",
338 params->enable ? "enable" : "disable", rc);
339 return rc;
340 }
341
342 WREG32(base_reg + 0x20, 0);
343
344 if (params->enable) {
345 input = params->input;
346
347 if (!input)
348 return -EINVAL;
349
350 WREG32(base_reg + 0x34, 0x3FFC);
351 WREG32(base_reg + 0x28, input->sink_mode);
352 WREG32(base_reg + 0x304, 0x4001);
353 WREG32(base_reg + 0x308, 0xA);
354 WREG32(base_reg + 0x20, 1);
355 } else {
356 WREG32(base_reg + 0x34, 0);
357 WREG32(base_reg + 0x28, 0);
358 WREG32(base_reg + 0x304, 0);
359 }
360
361 return 0;
362}
363
364static int goya_etr_validate_address(struct hl_device *hdev, u64 addr,
365 u64 size)
366{
367 struct asic_fixed_properties *prop = &hdev->asic_prop;
368 u64 range_start, range_end;
369
370 if (addr > (addr + size)) {
371 dev_err(hdev->dev,
372 "ETR buffer size %llu overflow\n", size);
373 return false;
374 }
375
376 if (hdev->mmu_enable) {
377 range_start = prop->dmmu.start_addr;
378 range_end = prop->dmmu.end_addr;
379 } else {
380 range_start = prop->dram_user_base_address;
381 range_end = prop->dram_end_address;
382 }
383
384 return hl_mem_area_inside_range(addr, size, range_start, range_end);
385}
386
387static int goya_config_etr(struct hl_device *hdev,
388 struct hl_debug_params *params)
389{
390 struct hl_debug_params_etr *input;
391 u32 val;
392 int rc;
393
394 WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
395
396 val = RREG32(mmPSOC_ETR_FFCR);
397 val |= 0x1000;
398 WREG32(mmPSOC_ETR_FFCR, val);
399 val |= 0x40;
400 WREG32(mmPSOC_ETR_FFCR, val);
401
402 rc = goya_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false);
403 if (rc) {
404 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
405 params->enable ? "enable" : "disable", rc);
406 return rc;
407 }
408
409 rc = goya_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true);
410 if (rc) {
411 dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n",
412 params->enable ? "enable" : "disable", rc);
413 return rc;
414 }
415
416 WREG32(mmPSOC_ETR_CTL, 0);
417
418 if (params->enable) {
419 input = params->input;
420
421 if (!input)
422 return -EINVAL;
423
424 if (input->buffer_size == 0) {
425 dev_err(hdev->dev,
426 "ETR buffer size should be bigger than 0\n");
427 return -EINVAL;
428 }
429
430 if (!goya_etr_validate_address(hdev,
431 input->buffer_address, input->buffer_size)) {
432 dev_err(hdev->dev, "buffer address is not valid\n");
433 return -EINVAL;
434 }
435
436 WREG32(mmPSOC_ETR_BUFWM, 0x3FFC);
437 WREG32(mmPSOC_ETR_RSZ, input->buffer_size);
438 WREG32(mmPSOC_ETR_MODE, input->sink_mode);
439 WREG32(mmPSOC_ETR_AXICTL,
440 0x700 | PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT);
441 WREG32(mmPSOC_ETR_DBALO,
442 lower_32_bits(input->buffer_address));
443 WREG32(mmPSOC_ETR_DBAHI,
444 upper_32_bits(input->buffer_address));
445 WREG32(mmPSOC_ETR_FFCR, 3);
446 WREG32(mmPSOC_ETR_PSCR, 0xA);
447 WREG32(mmPSOC_ETR_CTL, 1);
448 } else {
449 WREG32(mmPSOC_ETR_BUFWM, 0);
450 WREG32(mmPSOC_ETR_RSZ, 0x400);
451 WREG32(mmPSOC_ETR_DBALO, 0);
452 WREG32(mmPSOC_ETR_DBAHI, 0);
453 WREG32(mmPSOC_ETR_PSCR, 0);
454 WREG32(mmPSOC_ETR_MODE, 0);
455 WREG32(mmPSOC_ETR_FFCR, 0);
456
457 if (params->output_size >= sizeof(u64)) {
458 u32 rwp, rwphi;
459
460
461
462
463
464
465 rwp = RREG32(mmPSOC_ETR_RWP);
466 rwphi = RREG32(mmPSOC_ETR_RWPHI) & 0xff;
467 *(u64 *) params->output = ((u64) rwphi << 32) | rwp;
468 }
469 }
470
471 return 0;
472}
473
474static int goya_config_funnel(struct hl_device *hdev,
475 struct hl_debug_params *params)
476{
477 u64 base_reg;
478
479 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) {
480 dev_err(hdev->dev, "Invalid register index in FUNNEL\n");
481 return -EINVAL;
482 }
483
484 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE;
485
486 WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
487
488 WREG32(base_reg, params->enable ? 0x33F : 0);
489
490 return 0;
491}
492
493static int goya_config_bmon(struct hl_device *hdev,
494 struct hl_debug_params *params)
495{
496 struct hl_debug_params_bmon *input;
497 u64 base_reg;
498 u32 pcie_base = 0;
499
500 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) {
501 dev_err(hdev->dev, "Invalid register index in BMON\n");
502 return -EINVAL;
503 }
504
505 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE;
506
507 WREG32(base_reg + 0x104, 1);
508
509 if (params->enable) {
510 input = params->input;
511
512 if (!input)
513 return -EINVAL;
514
515 WREG32(base_reg + 0x200, lower_32_bits(input->start_addr0));
516 WREG32(base_reg + 0x204, upper_32_bits(input->start_addr0));
517 WREG32(base_reg + 0x208, lower_32_bits(input->addr_mask0));
518 WREG32(base_reg + 0x20C, upper_32_bits(input->addr_mask0));
519 WREG32(base_reg + 0x240, lower_32_bits(input->start_addr1));
520 WREG32(base_reg + 0x244, upper_32_bits(input->start_addr1));
521 WREG32(base_reg + 0x248, lower_32_bits(input->addr_mask1));
522 WREG32(base_reg + 0x24C, upper_32_bits(input->addr_mask1));
523 WREG32(base_reg + 0x224, 0);
524 WREG32(base_reg + 0x234, 0);
525 WREG32(base_reg + 0x30C, input->bw_win);
526 WREG32(base_reg + 0x308, input->win_capture);
527
528
529 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD &&
530 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR &&
531 params->reg_idx != GOYA_BMON_PCIE_SLV_RD &&
532 params->reg_idx != GOYA_BMON_PCIE_SLV_WR)
533 pcie_base = 0xA000000;
534
535 WREG32(base_reg + 0x700, pcie_base | 0xB00 | (input->id << 12));
536 WREG32(base_reg + 0x708, pcie_base | 0xA00 | (input->id << 12));
537 WREG32(base_reg + 0x70C, pcie_base | 0xC00 | (input->id << 12));
538
539 WREG32(base_reg + 0x100, 0x11);
540 WREG32(base_reg + 0x304, 0x1);
541 } else {
542 WREG32(base_reg + 0x200, 0);
543 WREG32(base_reg + 0x204, 0);
544 WREG32(base_reg + 0x208, 0xFFFFFFFF);
545 WREG32(base_reg + 0x20C, 0xFFFFFFFF);
546 WREG32(base_reg + 0x240, 0);
547 WREG32(base_reg + 0x244, 0);
548 WREG32(base_reg + 0x248, 0xFFFFFFFF);
549 WREG32(base_reg + 0x24C, 0xFFFFFFFF);
550 WREG32(base_reg + 0x224, 0xFFFFFFFF);
551 WREG32(base_reg + 0x234, 0x1070F);
552 WREG32(base_reg + 0x30C, 0);
553 WREG32(base_reg + 0x308, 0xFFFF);
554 WREG32(base_reg + 0x700, 0xA000B00);
555 WREG32(base_reg + 0x708, 0xA000A00);
556 WREG32(base_reg + 0x70C, 0xA000C00);
557 WREG32(base_reg + 0x100, 1);
558 WREG32(base_reg + 0x304, 0);
559 WREG32(base_reg + 0x104, 0);
560 }
561
562 return 0;
563}
564
565static int goya_config_spmu(struct hl_device *hdev,
566 struct hl_debug_params *params)
567{
568 u64 base_reg;
569 struct hl_debug_params_spmu *input = params->input;
570 u64 *output;
571 u32 output_arr_len;
572 u32 events_num;
573 u32 overflow_idx;
574 u32 cycle_cnt_idx;
575 int i;
576
577 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) {
578 dev_err(hdev->dev, "Invalid register index in SPMU\n");
579 return -EINVAL;
580 }
581
582 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE;
583
584 if (params->enable) {
585 input = params->input;
586
587 if (!input)
588 return -EINVAL;
589
590 if (input->event_types_num < 3) {
591 dev_err(hdev->dev,
592 "not enough event types values for SPMU enable\n");
593 return -EINVAL;
594 }
595
596 if (input->event_types_num > SPMU_MAX_COUNTERS) {
597 dev_err(hdev->dev,
598 "too many event types values for SPMU enable\n");
599 return -EINVAL;
600 }
601
602 WREG32(base_reg + 0xE04, 0x41013046);
603 WREG32(base_reg + 0xE04, 0x41013040);
604
605 for (i = 0 ; i < input->event_types_num ; i++)
606 WREG32(base_reg + SPMU_EVENT_TYPES_OFFSET + i * 4,
607 input->event_types[i]);
608
609 WREG32(base_reg + 0xE04, 0x41013041);
610 WREG32(base_reg + 0xC00, 0x8000003F);
611 } else {
612 output = params->output;
613 output_arr_len = params->output_size / 8;
614 events_num = output_arr_len - 2;
615 overflow_idx = output_arr_len - 2;
616 cycle_cnt_idx = output_arr_len - 1;
617
618 if (!output)
619 return -EINVAL;
620
621 if (output_arr_len < 3) {
622 dev_err(hdev->dev,
623 "not enough values for SPMU disable\n");
624 return -EINVAL;
625 }
626
627 if (events_num > SPMU_MAX_COUNTERS) {
628 dev_err(hdev->dev,
629 "too many events values for SPMU disable\n");
630 return -EINVAL;
631 }
632
633 WREG32(base_reg + 0xE04, 0x41013040);
634
635 for (i = 0 ; i < events_num ; i++)
636 output[i] = RREG32(base_reg + i * 8);
637
638 output[overflow_idx] = RREG32(base_reg + 0xCC0);
639
640 output[cycle_cnt_idx] = RREG32(base_reg + 0xFC);
641 output[cycle_cnt_idx] <<= 32;
642 output[cycle_cnt_idx] |= RREG32(base_reg + 0xF8);
643
644 WREG32(base_reg + 0xCC0, 0);
645 }
646
647 return 0;
648}
649
650int goya_debug_coresight(struct hl_device *hdev, void *data)
651{
652 struct hl_debug_params *params = data;
653 int rc = 0;
654
655 switch (params->op) {
656 case HL_DEBUG_OP_STM:
657 rc = goya_config_stm(hdev, params);
658 break;
659 case HL_DEBUG_OP_ETF:
660 rc = goya_config_etf(hdev, params);
661 break;
662 case HL_DEBUG_OP_ETR:
663 rc = goya_config_etr(hdev, params);
664 break;
665 case HL_DEBUG_OP_FUNNEL:
666 rc = goya_config_funnel(hdev, params);
667 break;
668 case HL_DEBUG_OP_BMON:
669 rc = goya_config_bmon(hdev, params);
670 break;
671 case HL_DEBUG_OP_SPMU:
672 rc = goya_config_spmu(hdev, params);
673 break;
674 case HL_DEBUG_OP_TIMESTAMP:
675
676 break;
677
678 default:
679 dev_err(hdev->dev, "Unknown coresight id %d\n", params->op);
680 return -EINVAL;
681 }
682
683
684 RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
685
686 return rc;
687}
688
689void goya_halt_coresight(struct hl_device *hdev)
690{
691 struct hl_debug_params params = {};
692 int i, rc;
693
694 for (i = GOYA_ETF_FIRST ; i <= GOYA_ETF_LAST ; i++) {
695 params.reg_idx = i;
696 rc = goya_config_etf(hdev, ¶ms);
697 if (rc)
698 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i);
699 }
700
701 rc = goya_config_etr(hdev, ¶ms);
702 if (rc)
703 dev_err(hdev->dev, "halt ETR failed, %d\n", rc);
704}
705
