1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC4_QM_REGS_H_ 14#define ASIC_REG_TPC4_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * TPC4_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmTPC4_QM_GLBL_CFG0 0xF08000 23 24#define mmTPC4_QM_GLBL_CFG1 0xF08004 25 26#define mmTPC4_QM_GLBL_PROT 0xF08008 27 28#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C 29 30#define mmTPC4_QM_GLBL_SECURE_PROPS_0 0xF08010 31 32#define mmTPC4_QM_GLBL_SECURE_PROPS_1 0xF08014 33 34#define mmTPC4_QM_GLBL_SECURE_PROPS_2 0xF08018 35 36#define mmTPC4_QM_GLBL_SECURE_PROPS_3 0xF0801C 37 38#define mmTPC4_QM_GLBL_SECURE_PROPS_4 0xF08020 39 40#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_0 0xF08024 41 42#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_1 0xF08028 43 44#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_2 0xF0802C 45 46#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_3 0xF08030 47 48#define mmTPC4_QM_GLBL_NON_SECURE_PROPS_4 0xF08034 49 50#define mmTPC4_QM_GLBL_STS0 0xF08038 51 52#define mmTPC4_QM_GLBL_STS1_0 0xF08040 53 54#define mmTPC4_QM_GLBL_STS1_1 0xF08044 55 56#define mmTPC4_QM_GLBL_STS1_2 0xF08048 57 58#define mmTPC4_QM_GLBL_STS1_3 0xF0804C 59 60#define mmTPC4_QM_GLBL_STS1_4 0xF08050 61 62#define mmTPC4_QM_GLBL_MSG_EN_0 0xF08054 63 64#define mmTPC4_QM_GLBL_MSG_EN_1 0xF08058 65 66#define mmTPC4_QM_GLBL_MSG_EN_2 0xF0805C 67 68#define mmTPC4_QM_GLBL_MSG_EN_3 0xF08060 69 70#define mmTPC4_QM_GLBL_MSG_EN_4 0xF08068 71 72#define mmTPC4_QM_PQ_BASE_LO_0 0xF08070 73 74#define mmTPC4_QM_PQ_BASE_LO_1 0xF08074 75 76#define mmTPC4_QM_PQ_BASE_LO_2 0xF08078 77 78#define mmTPC4_QM_PQ_BASE_LO_3 0xF0807C 79 80#define mmTPC4_QM_PQ_BASE_HI_0 0xF08080 81 82#define mmTPC4_QM_PQ_BASE_HI_1 0xF08084 83 84#define mmTPC4_QM_PQ_BASE_HI_2 0xF08088 85 86#define mmTPC4_QM_PQ_BASE_HI_3 0xF0808C 87 88#define mmTPC4_QM_PQ_SIZE_0 0xF08090 89 90#define mmTPC4_QM_PQ_SIZE_1 0xF08094 91 92#define mmTPC4_QM_PQ_SIZE_2 0xF08098 93 94#define mmTPC4_QM_PQ_SIZE_3 0xF0809C 95 96#define mmTPC4_QM_PQ_PI_0 0xF080A0 97 98#define mmTPC4_QM_PQ_PI_1 0xF080A4 99 100#define mmTPC4_QM_PQ_PI_2 0xF080A8 101 102#define mmTPC4_QM_PQ_PI_3 0xF080AC 103 104#define mmTPC4_QM_PQ_CI_0 0xF080B0 105 106#define mmTPC4_QM_PQ_CI_1 0xF080B4 107 108#define mmTPC4_QM_PQ_CI_2 0xF080B8 109 110#define mmTPC4_QM_PQ_CI_3 0xF080BC 111 112#define mmTPC4_QM_PQ_CFG0_0 0xF080C0 113 114#define mmTPC4_QM_PQ_CFG0_1 0xF080C4 115 116#define mmTPC4_QM_PQ_CFG0_2 0xF080C8 117 118#define mmTPC4_QM_PQ_CFG0_3 0xF080CC 119 120#define mmTPC4_QM_PQ_CFG1_0 0xF080D0 121 122#define mmTPC4_QM_PQ_CFG1_1 0xF080D4 123 124#define mmTPC4_QM_PQ_CFG1_2 0xF080D8 125 126#define mmTPC4_QM_PQ_CFG1_3 0xF080DC 127 128#define mmTPC4_QM_PQ_ARUSER_31_11_0 0xF080E0 129 130#define mmTPC4_QM_PQ_ARUSER_31_11_1 0xF080E4 131 132#define mmTPC4_QM_PQ_ARUSER_31_11_2 0xF080E8 133 134#define mmTPC4_QM_PQ_ARUSER_31_11_3 0xF080EC 135 136#define mmTPC4_QM_PQ_STS0_0 0xF080F0 137 138#define mmTPC4_QM_PQ_STS0_1 0xF080F4 139 140#define mmTPC4_QM_PQ_STS0_2 0xF080F8 141 142#define mmTPC4_QM_PQ_STS0_3 0xF080FC 143 144#define mmTPC4_QM_PQ_STS1_0 0xF08100 145 146#define mmTPC4_QM_PQ_STS1_1 0xF08104 147 148#define mmTPC4_QM_PQ_STS1_2 0xF08108 149 150#define mmTPC4_QM_PQ_STS1_3 0xF0810C 151 152#define mmTPC4_QM_CQ_CFG0_0 0xF08110 153 154#define mmTPC4_QM_CQ_CFG0_1 0xF08114 155 156#define mmTPC4_QM_CQ_CFG0_2 0xF08118 157 158#define mmTPC4_QM_CQ_CFG0_3 0xF0811C 159 160#define mmTPC4_QM_CQ_CFG0_4 0xF08120 161 162#define mmTPC4_QM_CQ_CFG1_0 0xF08124 163 164#define mmTPC4_QM_CQ_CFG1_1 0xF08128 165 166#define mmTPC4_QM_CQ_CFG1_2 0xF0812C 167 168#define mmTPC4_QM_CQ_CFG1_3 0xF08130 169 170#define mmTPC4_QM_CQ_CFG1_4 0xF08134 171 172#define mmTPC4_QM_CQ_ARUSER_31_11_0 0xF08138 173 174#define mmTPC4_QM_CQ_ARUSER_31_11_1 0xF0813C 175 176#define mmTPC4_QM_CQ_ARUSER_31_11_2 0xF08140 177 178#define mmTPC4_QM_CQ_ARUSER_31_11_3 0xF08144 179 180#define mmTPC4_QM_CQ_ARUSER_31_11_4 0xF08148 181 182#define mmTPC4_QM_CQ_STS0_0 0xF0814C 183 184#define mmTPC4_QM_CQ_STS0_1 0xF08150 185 186#define mmTPC4_QM_CQ_STS0_2 0xF08154 187 188#define mmTPC4_QM_CQ_STS0_3 0xF08158 189 190#define mmTPC4_QM_CQ_STS0_4 0xF0815C 191 192#define mmTPC4_QM_CQ_STS1_0 0xF08160 193 194#define mmTPC4_QM_CQ_STS1_1 0xF08164 195 196#define mmTPC4_QM_CQ_STS1_2 0xF08168 197 198#define mmTPC4_QM_CQ_STS1_3 0xF0816C 199 200#define mmTPC4_QM_CQ_STS1_4 0xF08170 201 202#define mmTPC4_QM_CQ_PTR_LO_0 0xF08174 203 204#define mmTPC4_QM_CQ_PTR_HI_0 0xF08178 205 206#define mmTPC4_QM_CQ_TSIZE_0 0xF0817C 207 208#define mmTPC4_QM_CQ_CTL_0 0xF08180 209 210#define mmTPC4_QM_CQ_PTR_LO_1 0xF08184 211 212#define mmTPC4_QM_CQ_PTR_HI_1 0xF08188 213 214#define mmTPC4_QM_CQ_TSIZE_1 0xF0818C 215 216#define mmTPC4_QM_CQ_CTL_1 0xF08190 217 218#define mmTPC4_QM_CQ_PTR_LO_2 0xF08194 219 220#define mmTPC4_QM_CQ_PTR_HI_2 0xF08198 221 222#define mmTPC4_QM_CQ_TSIZE_2 0xF0819C 223 224#define mmTPC4_QM_CQ_CTL_2 0xF081A0 225 226#define mmTPC4_QM_CQ_PTR_LO_3 0xF081A4 227 228#define mmTPC4_QM_CQ_PTR_HI_3 0xF081A8 229 230#define mmTPC4_QM_CQ_TSIZE_3 0xF081AC 231 232#define mmTPC4_QM_CQ_CTL_3 0xF081B0 233 234#define mmTPC4_QM_CQ_PTR_LO_4 0xF081B4 235 236#define mmTPC4_QM_CQ_PTR_HI_4 0xF081B8 237 238#define mmTPC4_QM_CQ_TSIZE_4 0xF081BC 239 240#define mmTPC4_QM_CQ_CTL_4 0xF081C0 241 242#define mmTPC4_QM_CQ_PTR_LO_STS_0 0xF081C4 243 244#define mmTPC4_QM_CQ_PTR_LO_STS_1 0xF081C8 245 246#define mmTPC4_QM_CQ_PTR_LO_STS_2 0xF081CC 247 248#define mmTPC4_QM_CQ_PTR_LO_STS_3 0xF081D0 249 250#define mmTPC4_QM_CQ_PTR_LO_STS_4 0xF081D4 251 252#define mmTPC4_QM_CQ_PTR_HI_STS_0 0xF081D8 253 254#define mmTPC4_QM_CQ_PTR_HI_STS_1 0xF081DC 255 256#define mmTPC4_QM_CQ_PTR_HI_STS_2 0xF081E0 257 258#define mmTPC4_QM_CQ_PTR_HI_STS_3 0xF081E4 259 260#define mmTPC4_QM_CQ_PTR_HI_STS_4 0xF081E8 261 262#define mmTPC4_QM_CQ_TSIZE_STS_0 0xF081EC 263 264#define mmTPC4_QM_CQ_TSIZE_STS_1 0xF081F0 265 266#define mmTPC4_QM_CQ_TSIZE_STS_2 0xF081F4 267 268#define mmTPC4_QM_CQ_TSIZE_STS_3 0xF081F8 269 270#define mmTPC4_QM_CQ_TSIZE_STS_4 0xF081FC 271 272#define mmTPC4_QM_CQ_CTL_STS_0 0xF08200 273 274#define mmTPC4_QM_CQ_CTL_STS_1 0xF08204 275 276#define mmTPC4_QM_CQ_CTL_STS_2 0xF08208 277 278#define mmTPC4_QM_CQ_CTL_STS_3 0xF0820C 279 280#define mmTPC4_QM_CQ_CTL_STS_4 0xF08210 281 282#define mmTPC4_QM_CQ_IFIFO_CNT_0 0xF08214 283 284#define mmTPC4_QM_CQ_IFIFO_CNT_1 0xF08218 285 286#define mmTPC4_QM_CQ_IFIFO_CNT_2 0xF0821C 287 288#define mmTPC4_QM_CQ_IFIFO_CNT_3 0xF08220 289 290#define mmTPC4_QM_CQ_IFIFO_CNT_4 0xF08224 291 292#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_0 0xF08228 293 294#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_1 0xF0822C 295 296#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_2 0xF08230 297 298#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_3 0xF08234 299 300#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO_4 0xF08238 301 302#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_0 0xF0823C 303 304#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_1 0xF08240 305 306#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_2 0xF08244 307 308#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_3 0xF08248 309 310#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI_4 0xF0824C 311 312#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_0 0xF08250 313 314#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_1 0xF08254 315 316#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_2 0xF08258 317 318#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_3 0xF0825C 319 320#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO_4 0xF08260 321 322#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_0 0xF08264 323 324#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_1 0xF08268 325 326#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_2 0xF0826C 327 328#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_3 0xF08270 329 330#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI_4 0xF08274 331 332#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_0 0xF08278 333 334#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_1 0xF0827C 335 336#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_2 0xF08280 337 338#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_3 0xF08284 339 340#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO_4 0xF08288 341 342#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_0 0xF0828C 343 344#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_1 0xF08290 345 346#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_2 0xF08294 347 348#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_3 0xF08298 349 350#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI_4 0xF0829C 351 352#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_0 0xF082A0 353 354#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_1 0xF082A4 355 356#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_2 0xF082A8 357 358#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_3 0xF082AC 359 360#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO_4 0xF082B0 361 362#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_0 0xF082B4 363 364#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_1 0xF082B8 365 366#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_2 0xF082BC 367 368#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_3 0xF082C0 369 370#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI_4 0xF082C4 371 372#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_0 0xF082C8 373 374#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_1 0xF082CC 375 376#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_2 0xF082D0 377 378#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_3 0xF082D4 379 380#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET_4 0xF082D8 381 382#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xF082E0 383 384#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xF082E4 385 386#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xF082E8 387 388#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xF082EC 389 390#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xF082F0 391 392#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xF082F4 393 394#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xF082F8 395 396#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xF082FC 397 398#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xF08300 399 400#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xF08304 401 402#define mmTPC4_QM_CP_FENCE0_RDATA_0 0xF08308 403 404#define mmTPC4_QM_CP_FENCE0_RDATA_1 0xF0830C 405 406#define mmTPC4_QM_CP_FENCE0_RDATA_2 0xF08310 407 408#define mmTPC4_QM_CP_FENCE0_RDATA_3 0xF08314 409 410#define mmTPC4_QM_CP_FENCE0_RDATA_4 0xF08318 411 412#define mmTPC4_QM_CP_FENCE1_RDATA_0 0xF0831C 413 414#define mmTPC4_QM_CP_FENCE1_RDATA_1 0xF08320 415 416#define mmTPC4_QM_CP_FENCE1_RDATA_2 0xF08324 417 418#define mmTPC4_QM_CP_FENCE1_RDATA_3 0xF08328 419 420#define mmTPC4_QM_CP_FENCE1_RDATA_4 0xF0832C 421 422#define mmTPC4_QM_CP_FENCE2_RDATA_0 0xF08330 423 424#define mmTPC4_QM_CP_FENCE2_RDATA_1 0xF08334 425 426#define mmTPC4_QM_CP_FENCE2_RDATA_2 0xF08338 427 428#define mmTPC4_QM_CP_FENCE2_RDATA_3 0xF0833C 429 430#define mmTPC4_QM_CP_FENCE2_RDATA_4 0xF08340 431 432#define mmTPC4_QM_CP_FENCE3_RDATA_0 0xF08344 433 434#define mmTPC4_QM_CP_FENCE3_RDATA_1 0xF08348 435 436#define mmTPC4_QM_CP_FENCE3_RDATA_2 0xF0834C 437 438#define mmTPC4_QM_CP_FENCE3_RDATA_3 0xF08350 439 440#define mmTPC4_QM_CP_FENCE3_RDATA_4 0xF08354 441 442#define mmTPC4_QM_CP_FENCE0_CNT_0 0xF08358 443 444#define mmTPC4_QM_CP_FENCE0_CNT_1 0xF0835C 445 446#define mmTPC4_QM_CP_FENCE0_CNT_2 0xF08360 447 448#define mmTPC4_QM_CP_FENCE0_CNT_3 0xF08364 449 450#define mmTPC4_QM_CP_FENCE0_CNT_4 0xF08368 451 452#define mmTPC4_QM_CP_FENCE1_CNT_0 0xF0836C 453 454#define mmTPC4_QM_CP_FENCE1_CNT_1 0xF08370 455 456#define mmTPC4_QM_CP_FENCE1_CNT_2 0xF08374 457 458#define mmTPC4_QM_CP_FENCE1_CNT_3 0xF08378 459 460#define mmTPC4_QM_CP_FENCE1_CNT_4 0xF0837C 461 462#define mmTPC4_QM_CP_FENCE2_CNT_0 0xF08380 463 464#define mmTPC4_QM_CP_FENCE2_CNT_1 0xF08384 465 466#define mmTPC4_QM_CP_FENCE2_CNT_2 0xF08388 467 468#define mmTPC4_QM_CP_FENCE2_CNT_3 0xF0838C 469 470#define mmTPC4_QM_CP_FENCE2_CNT_4 0xF08390 471 472#define mmTPC4_QM_CP_FENCE3_CNT_0 0xF08394 473 474#define mmTPC4_QM_CP_FENCE3_CNT_1 0xF08398 475 476#define mmTPC4_QM_CP_FENCE3_CNT_2 0xF0839C 477 478#define mmTPC4_QM_CP_FENCE3_CNT_3 0xF083A0 479 480#define mmTPC4_QM_CP_FENCE3_CNT_4 0xF083A4 481 482#define mmTPC4_QM_CP_STS_0 0xF083A8 483 484#define mmTPC4_QM_CP_STS_1 0xF083AC 485 486#define mmTPC4_QM_CP_STS_2 0xF083B0 487 488#define mmTPC4_QM_CP_STS_3 0xF083B4 489 490#define mmTPC4_QM_CP_STS_4 0xF083B8 491 492#define mmTPC4_QM_CP_CURRENT_INST_LO_0 0xF083BC 493 494#define mmTPC4_QM_CP_CURRENT_INST_LO_1 0xF083C0 495 496#define mmTPC4_QM_CP_CURRENT_INST_LO_2 0xF083C4 497 498#define mmTPC4_QM_CP_CURRENT_INST_LO_3 0xF083C8 499 500#define mmTPC4_QM_CP_CURRENT_INST_LO_4 0xF083CC 501 502#define mmTPC4_QM_CP_CURRENT_INST_HI_0 0xF083D0 503 504#define mmTPC4_QM_CP_CURRENT_INST_HI_1 0xF083D4 505 506#define mmTPC4_QM_CP_CURRENT_INST_HI_2 0xF083D8 507 508#define mmTPC4_QM_CP_CURRENT_INST_HI_3 0xF083DC 509 510#define mmTPC4_QM_CP_CURRENT_INST_HI_4 0xF083E0 511 512#define mmTPC4_QM_CP_BARRIER_CFG_0 0xF083F4 513 514#define mmTPC4_QM_CP_BARRIER_CFG_1 0xF083F8 515 516#define mmTPC4_QM_CP_BARRIER_CFG_2 0xF083FC 517 518#define mmTPC4_QM_CP_BARRIER_CFG_3 0xF08400 519 520#define mmTPC4_QM_CP_BARRIER_CFG_4 0xF08404 521 522#define mmTPC4_QM_CP_DBG_0_0 0xF08408 523 524#define mmTPC4_QM_CP_DBG_0_1 0xF0840C 525 526#define mmTPC4_QM_CP_DBG_0_2 0xF08410 527 528#define mmTPC4_QM_CP_DBG_0_3 0xF08414 529 530#define mmTPC4_QM_CP_DBG_0_4 0xF08418 531 532#define mmTPC4_QM_CP_ARUSER_31_11_0 0xF0841C 533 534#define mmTPC4_QM_CP_ARUSER_31_11_1 0xF08420 535 536#define mmTPC4_QM_CP_ARUSER_31_11_2 0xF08424 537 538#define mmTPC4_QM_CP_ARUSER_31_11_3 0xF08428 539 540#define mmTPC4_QM_CP_ARUSER_31_11_4 0xF0842C 541 542#define mmTPC4_QM_CP_AWUSER_31_11_0 0xF08430 543 544#define mmTPC4_QM_CP_AWUSER_31_11_1 0xF08434 545 546#define mmTPC4_QM_CP_AWUSER_31_11_2 0xF08438 547 548#define mmTPC4_QM_CP_AWUSER_31_11_3 0xF0843C 549 550#define mmTPC4_QM_CP_AWUSER_31_11_4 0xF08440 551 552#define mmTPC4_QM_ARB_CFG_0 0xF08A00 553 554#define mmTPC4_QM_ARB_CHOISE_Q_PUSH 0xF08A04 555 556#define mmTPC4_QM_ARB_WRR_WEIGHT_0 0xF08A08 557 558#define mmTPC4_QM_ARB_WRR_WEIGHT_1 0xF08A0C 559 560#define mmTPC4_QM_ARB_WRR_WEIGHT_2 0xF08A10 561 562#define mmTPC4_QM_ARB_WRR_WEIGHT_3 0xF08A14 563 564#define mmTPC4_QM_ARB_CFG_1 0xF08A18 565 566#define mmTPC4_QM_ARB_MST_AVAIL_CRED_0 0xF08A20 567 568#define mmTPC4_QM_ARB_MST_AVAIL_CRED_1 0xF08A24 569 570#define mmTPC4_QM_ARB_MST_AVAIL_CRED_2 0xF08A28 571 572#define mmTPC4_QM_ARB_MST_AVAIL_CRED_3 0xF08A2C 573 574#define mmTPC4_QM_ARB_MST_AVAIL_CRED_4 0xF08A30 575 576#define mmTPC4_QM_ARB_MST_AVAIL_CRED_5 0xF08A34 577 578#define mmTPC4_QM_ARB_MST_AVAIL_CRED_6 0xF08A38 579 580#define mmTPC4_QM_ARB_MST_AVAIL_CRED_7 0xF08A3C 581 582#define mmTPC4_QM_ARB_MST_AVAIL_CRED_8 0xF08A40 583 584#define mmTPC4_QM_ARB_MST_AVAIL_CRED_9 0xF08A44 585 586#define mmTPC4_QM_ARB_MST_AVAIL_CRED_10 0xF08A48 587 588#define mmTPC4_QM_ARB_MST_AVAIL_CRED_11 0xF08A4C 589 590#define mmTPC4_QM_ARB_MST_AVAIL_CRED_12 0xF08A50 591 592#define mmTPC4_QM_ARB_MST_AVAIL_CRED_13 0xF08A54 593 594#define mmTPC4_QM_ARB_MST_AVAIL_CRED_14 0xF08A58 595 596#define mmTPC4_QM_ARB_MST_AVAIL_CRED_15 0xF08A5C 597 598#define mmTPC4_QM_ARB_MST_AVAIL_CRED_16 0xF08A60 599 600#define mmTPC4_QM_ARB_MST_AVAIL_CRED_17 0xF08A64 601 602#define mmTPC4_QM_ARB_MST_AVAIL_CRED_18 0xF08A68 603 604#define mmTPC4_QM_ARB_MST_AVAIL_CRED_19 0xF08A6C 605 606#define mmTPC4_QM_ARB_MST_AVAIL_CRED_20 0xF08A70 607 608#define mmTPC4_QM_ARB_MST_AVAIL_CRED_21 0xF08A74 609 610#define mmTPC4_QM_ARB_MST_AVAIL_CRED_22 0xF08A78 611 612#define mmTPC4_QM_ARB_MST_AVAIL_CRED_23 0xF08A7C 613 614#define mmTPC4_QM_ARB_MST_AVAIL_CRED_24 0xF08A80 615 616#define mmTPC4_QM_ARB_MST_AVAIL_CRED_25 0xF08A84 617 618#define mmTPC4_QM_ARB_MST_AVAIL_CRED_26 0xF08A88 619 620#define mmTPC4_QM_ARB_MST_AVAIL_CRED_27 0xF08A8C 621 622#define mmTPC4_QM_ARB_MST_AVAIL_CRED_28 0xF08A90 623 624#define mmTPC4_QM_ARB_MST_AVAIL_CRED_29 0xF08A94 625 626#define mmTPC4_QM_ARB_MST_AVAIL_CRED_30 0xF08A98 627 628#define mmTPC4_QM_ARB_MST_AVAIL_CRED_31 0xF08A9C 629 630#define mmTPC4_QM_ARB_MST_CRED_INC 0xF08AA0 631 632#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xF08AA4 633 634#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xF08AA8 635 636#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xF08AAC 637 638#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xF08AB0 639 640#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xF08AB4 641 642#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xF08AB8 643 644#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xF08ABC 645 646#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xF08AC0 647 648#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xF08AC4 649 650#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xF08AC8 651 652#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xF08ACC 653 654#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xF08AD0 655 656#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xF08AD4 657 658#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xF08AD8 659 660#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xF08ADC 661 662#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xF08AE0 663 664#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xF08AE4 665 666#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xF08AE8 667 668#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xF08AEC 669 670#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xF08AF0 671 672#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xF08AF4 673 674#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xF08AF8 675 676#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xF08AFC 677 678#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xF08B00 679 680#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xF08B04 681 682#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xF08B08 683 684#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xF08B0C 685 686#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xF08B10 687 688#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xF08B14 689 690#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xF08B18 691 692#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xF08B1C 693 694#define mmTPC4_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xF08B20 695 696#define mmTPC4_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xF08B28 697 698#define mmTPC4_QM_ARB_MST_SLAVE_EN 0xF08B2C 699 700#define mmTPC4_QM_ARB_MST_QUIET_PER 0xF08B34 701 702#define mmTPC4_QM_ARB_SLV_CHOISE_WDT 0xF08B38 703 704#define mmTPC4_QM_ARB_SLV_ID 0xF08B3C 705 706#define mmTPC4_QM_ARB_MSG_MAX_INFLIGHT 0xF08B44 707 708#define mmTPC4_QM_ARB_MSG_AWUSER_31_11 0xF08B48 709 710#define mmTPC4_QM_ARB_MSG_AWUSER_SEC_PROP 0xF08B4C 711 712#define mmTPC4_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xF08B50 713 714#define mmTPC4_QM_ARB_BASE_LO 0xF08B54 715 716#define mmTPC4_QM_ARB_BASE_HI 0xF08B58 717 718#define mmTPC4_QM_ARB_STATE_STS 0xF08B80 719 720#define mmTPC4_QM_ARB_CHOISE_FULLNESS_STS 0xF08B84 721 722#define mmTPC4_QM_ARB_MSG_STS 0xF08B88 723 724#define mmTPC4_QM_ARB_SLV_CHOISE_Q_HEAD 0xF08B8C 725 726#define mmTPC4_QM_ARB_ERR_CAUSE 0xF08B9C 727 728#define mmTPC4_QM_ARB_ERR_MSG_EN 0xF08BA0 729 730#define mmTPC4_QM_ARB_ERR_STS_DRP 0xF08BA8 731 732#define mmTPC4_QM_ARB_MST_CRED_STS_0 0xF08BB0 733 734#define mmTPC4_QM_ARB_MST_CRED_STS_1 0xF08BB4 735 736#define mmTPC4_QM_ARB_MST_CRED_STS_2 0xF08BB8 737 738#define mmTPC4_QM_ARB_MST_CRED_STS_3 0xF08BBC 739 740#define mmTPC4_QM_ARB_MST_CRED_STS_4 0xF08BC0 741 742#define mmTPC4_QM_ARB_MST_CRED_STS_5 0xF08BC4 743 744#define mmTPC4_QM_ARB_MST_CRED_STS_6 0xF08BC8 745 746#define mmTPC4_QM_ARB_MST_CRED_STS_7 0xF08BCC 747 748#define mmTPC4_QM_ARB_MST_CRED_STS_8 0xF08BD0 749 750#define mmTPC4_QM_ARB_MST_CRED_STS_9 0xF08BD4 751 752#define mmTPC4_QM_ARB_MST_CRED_STS_10 0xF08BD8 753 754#define mmTPC4_QM_ARB_MST_CRED_STS_11 0xF08BDC 755 756#define mmTPC4_QM_ARB_MST_CRED_STS_12 0xF08BE0 757 758#define mmTPC4_QM_ARB_MST_CRED_STS_13 0xF08BE4 759 760#define mmTPC4_QM_ARB_MST_CRED_STS_14 0xF08BE8 761 762#define mmTPC4_QM_ARB_MST_CRED_STS_15 0xF08BEC 763 764#define mmTPC4_QM_ARB_MST_CRED_STS_16 0xF08BF0 765 766#define mmTPC4_QM_ARB_MST_CRED_STS_17 0xF08BF4 767 768#define mmTPC4_QM_ARB_MST_CRED_STS_18 0xF08BF8 769 770#define mmTPC4_QM_ARB_MST_CRED_STS_19 0xF08BFC 771 772#define mmTPC4_QM_ARB_MST_CRED_STS_20 0xF08C00 773 774#define mmTPC4_QM_ARB_MST_CRED_STS_21 0xF08C04 775 776#define mmTPC4_QM_ARB_MST_CRED_STS_22 0xF08C08 777 778#define mmTPC4_QM_ARB_MST_CRED_STS_23 0xF08C0C 779 780#define mmTPC4_QM_ARB_MST_CRED_STS_24 0xF08C10 781 782#define mmTPC4_QM_ARB_MST_CRED_STS_25 0xF08C14 783 784#define mmTPC4_QM_ARB_MST_CRED_STS_26 0xF08C18 785 786#define mmTPC4_QM_ARB_MST_CRED_STS_27 0xF08C1C 787 788#define mmTPC4_QM_ARB_MST_CRED_STS_28 0xF08C20 789 790#define mmTPC4_QM_ARB_MST_CRED_STS_29 0xF08C24 791 792#define mmTPC4_QM_ARB_MST_CRED_STS_30 0xF08C28 793 794#define mmTPC4_QM_ARB_MST_CRED_STS_31 0xF08C2C 795 796#define mmTPC4_QM_CGM_CFG 0xF08C70 797 798#define mmTPC4_QM_CGM_STS 0xF08C74 799 800#define mmTPC4_QM_CGM_CFG1 0xF08C78 801 802#define mmTPC4_QM_LOCAL_RANGE_BASE 0xF08C80 803 804#define mmTPC4_QM_LOCAL_RANGE_SIZE 0xF08C84 805 806#define mmTPC4_QM_CSMR_STRICT_PRIO_CFG 0xF08C90 807 808#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_1 0xF08C94 809 810#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_0 0xF08C98 811 812#define mmTPC4_QM_LBW_WR_RATE_LIM_CFG_1 0xF08C9C 813 814#define mmTPC4_QM_HBW_RD_RATE_LIM_CFG_0 0xF08CA0 815 816#define mmTPC4_QM_GLBL_AXCACHE 0xF08CA4 817 818#define mmTPC4_QM_IND_GW_APB_CFG 0xF08CB0 819 820#define mmTPC4_QM_IND_GW_APB_WDATA 0xF08CB4 821 822#define mmTPC4_QM_IND_GW_APB_RDATA 0xF08CB8 823 824#define mmTPC4_QM_IND_GW_APB_STATUS 0xF08CBC 825 826#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08CD0 827 828#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08CD4 829 830#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08CD8 831 832#define mmTPC4_QM_GLBL_MEM_INIT_BUSY 0xF08D00 833 834#endif /* ASIC_REG_TPC4_QM_REGS_H_ */ 835