1
2
3
4
5
6
7
8#include <linux/init.h>
9#include <linux/export.h>
10#include <linux/module.h>
11#include <linux/device.h>
12#include <linux/platform_device.h>
13#include <linux/ioport.h>
14#include <linux/io.h>
15#include <linux/dma-mapping.h>
16#include <linux/compiler.h>
17#include <linux/stddef.h>
18#include <linux/bitops.h>
19#include <linux/types.h>
20#include <linux/err.h>
21#include <linux/interrupt.h>
22#include <linux/acpi.h>
23#include <linux/pm.h>
24#include <linux/pm_runtime.h>
25#include <linux/delay.h>
26#include <linux/dmi.h>
27
28#include <linux/mmc/host.h>
29#include <linux/mmc/pm.h>
30#include <linux/mmc/slot-gpio.h>
31
32#ifdef CONFIG_X86
33#include <asm/cpu_device_id.h>
34#include <asm/intel-family.h>
35#include <asm/iosf_mbi.h>
36#include <linux/pci.h>
37#endif
38
39#include "sdhci.h"
40
41enum {
42 SDHCI_ACPI_SD_CD = BIT(0),
43 SDHCI_ACPI_RUNTIME_PM = BIT(1),
44 SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
45};
46
47struct sdhci_acpi_chip {
48 const struct sdhci_ops *ops;
49 unsigned int quirks;
50 unsigned int quirks2;
51 unsigned long caps;
52 unsigned int caps2;
53 mmc_pm_flag_t pm_caps;
54};
55
56struct sdhci_acpi_slot {
57 const struct sdhci_acpi_chip *chip;
58 unsigned int quirks;
59 unsigned int quirks2;
60 unsigned long caps;
61 unsigned int caps2;
62 mmc_pm_flag_t pm_caps;
63 unsigned int flags;
64 size_t priv_size;
65 int (*probe_slot)(struct platform_device *, struct acpi_device *);
66 int (*remove_slot)(struct platform_device *);
67 int (*free_slot)(struct platform_device *pdev);
68 int (*setup_host)(struct platform_device *pdev);
69};
70
71struct sdhci_acpi_host {
72 struct sdhci_host *host;
73 const struct sdhci_acpi_slot *slot;
74 struct platform_device *pdev;
75 bool use_runtime_pm;
76 bool is_intel;
77 bool reset_signal_volt_on_suspend;
78 unsigned long private[] ____cacheline_aligned;
79};
80
81enum {
82 DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0),
83 DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1),
84};
85
86static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
87{
88 return (void *)c->private;
89}
90
91static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
92{
93 return c->slot && (c->slot->flags & flag);
94}
95
96#define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
97#define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
98#define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
99#define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
100
101enum {
102 INTEL_DSM_FNS = 0,
103 INTEL_DSM_V18_SWITCH = 3,
104 INTEL_DSM_V33_SWITCH = 4,
105 INTEL_DSM_HS_CAPS = 8,
106};
107
108struct intel_host {
109 u32 dsm_fns;
110 u32 hs_caps;
111};
112
113static const guid_t intel_dsm_guid =
114 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
115 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
116
117static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
118 unsigned int fn, u32 *result)
119{
120 union acpi_object *obj;
121 int err = 0;
122
123 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
124 if (!obj)
125 return -EOPNOTSUPP;
126
127 if (obj->type == ACPI_TYPE_INTEGER) {
128 *result = obj->integer.value;
129 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
130 size_t len = min_t(size_t, obj->buffer.length, 4);
131
132 *result = 0;
133 memcpy(result, obj->buffer.pointer, len);
134 } else {
135 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
136 __func__, fn, obj->type, obj->buffer.length);
137 err = -EINVAL;
138 }
139
140 ACPI_FREE(obj);
141
142 return err;
143}
144
145static int intel_dsm(struct intel_host *intel_host, struct device *dev,
146 unsigned int fn, u32 *result)
147{
148 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
149 return -EOPNOTSUPP;
150
151 return __intel_dsm(intel_host, dev, fn, result);
152}
153
154static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
155 struct mmc_host *mmc)
156{
157 int err;
158
159 intel_host->hs_caps = ~0;
160
161 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
162 if (err) {
163 pr_debug("%s: DSM not supported, error %d\n",
164 mmc_hostname(mmc), err);
165 return;
166 }
167
168 pr_debug("%s: DSM function mask %#x\n",
169 mmc_hostname(mmc), intel_host->dsm_fns);
170
171 intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
172}
173
174static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
175 struct mmc_ios *ios)
176{
177 struct device *dev = mmc_dev(mmc);
178 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
179 struct intel_host *intel_host = sdhci_acpi_priv(c);
180 unsigned int fn;
181 u32 result = 0;
182 int err;
183
184 err = sdhci_start_signal_voltage_switch(mmc, ios);
185 if (err)
186 return err;
187
188 switch (ios->signal_voltage) {
189 case MMC_SIGNAL_VOLTAGE_330:
190 fn = INTEL_DSM_V33_SWITCH;
191 break;
192 case MMC_SIGNAL_VOLTAGE_180:
193 fn = INTEL_DSM_V18_SWITCH;
194 break;
195 default:
196 return 0;
197 }
198
199 err = intel_dsm(intel_host, dev, fn, &result);
200 pr_debug("%s: %s DSM fn %u error %d result %u\n",
201 mmc_hostname(mmc), __func__, fn, err, result);
202
203 return 0;
204}
205
206static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
207{
208 u8 reg;
209
210 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
211 reg |= 0x10;
212 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
213
214 udelay(9);
215 reg &= ~0x10;
216 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
217
218 usleep_range(300, 1000);
219}
220
221static const struct sdhci_ops sdhci_acpi_ops_dflt = {
222 .set_clock = sdhci_set_clock,
223 .set_bus_width = sdhci_set_bus_width,
224 .reset = sdhci_reset,
225 .set_uhs_signaling = sdhci_set_uhs_signaling,
226};
227
228static const struct sdhci_ops sdhci_acpi_ops_int = {
229 .set_clock = sdhci_set_clock,
230 .set_bus_width = sdhci_set_bus_width,
231 .reset = sdhci_reset,
232 .set_uhs_signaling = sdhci_set_uhs_signaling,
233 .hw_reset = sdhci_acpi_int_hw_reset,
234};
235
236static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
237 .ops = &sdhci_acpi_ops_int,
238};
239
240#ifdef CONFIG_X86
241
242static bool sdhci_acpi_byt(void)
243{
244 static const struct x86_cpu_id byt[] = {
245 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
246 {}
247 };
248
249 return x86_match_cpu(byt);
250}
251
252static bool sdhci_acpi_cht(void)
253{
254 static const struct x86_cpu_id cht[] = {
255 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
256 {}
257 };
258
259 return x86_match_cpu(cht);
260}
261
262#define BYT_IOSF_SCCEP 0x63
263#define BYT_IOSF_OCP_NETCTRL0 0x1078
264#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
265
266static void sdhci_acpi_byt_setting(struct device *dev)
267{
268 u32 val = 0;
269
270 if (!sdhci_acpi_byt())
271 return;
272
273 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
274 &val)) {
275 dev_err(dev, "%s read error\n", __func__);
276 return;
277 }
278
279 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
280 return;
281
282 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
283
284 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
285 val)) {
286 dev_err(dev, "%s write error\n", __func__);
287 return;
288 }
289
290 dev_dbg(dev, "%s completed\n", __func__);
291}
292
293static bool sdhci_acpi_byt_defer(struct device *dev)
294{
295 if (!sdhci_acpi_byt())
296 return false;
297
298 if (!iosf_mbi_available())
299 return true;
300
301 sdhci_acpi_byt_setting(dev);
302
303 return false;
304}
305
306static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
307 unsigned int slot, unsigned int parent_slot)
308{
309 struct pci_dev *dev, *parent, *from = NULL;
310
311 while (1) {
312 dev = pci_get_device(vendor, device, from);
313 pci_dev_put(from);
314 if (!dev)
315 break;
316 parent = pci_upstream_bridge(dev);
317 if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
318 parent && PCI_SLOT(parent->devfn) == parent_slot &&
319 !pci_upstream_bridge(parent)) {
320 pci_dev_put(dev);
321 return true;
322 }
323 from = dev;
324 }
325
326 return false;
327}
328
329
330
331
332
333
334
335
336static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
337{
338 return sdhci_acpi_cht() &&
339 acpi_dev_hid_uid_match(adev, "80860F14", "2") &&
340 sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
341}
342
343#else
344
345static inline void sdhci_acpi_byt_setting(struct device *dev)
346{
347}
348
349static inline bool sdhci_acpi_byt_defer(struct device *dev)
350{
351 return false;
352}
353
354static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
355{
356 return false;
357}
358
359#endif
360
361static int bxt_get_cd(struct mmc_host *mmc)
362{
363 int gpio_cd = mmc_gpio_get_cd(mmc);
364 struct sdhci_host *host = mmc_priv(mmc);
365 unsigned long flags;
366 int ret = 0;
367
368 if (!gpio_cd)
369 return 0;
370
371 spin_lock_irqsave(&host->lock, flags);
372
373 if (host->flags & SDHCI_DEVICE_DEAD)
374 goto out;
375
376 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
377out:
378 spin_unlock_irqrestore(&host->lock, flags);
379
380 return ret;
381}
382
383static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
384{
385 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
386 struct intel_host *intel_host = sdhci_acpi_priv(c);
387 struct sdhci_host *host = c->host;
388
389 if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
390 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
391 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
392 host->timeout_clk = 1000;
393
394 if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
395 host->mmc_host_ops.get_cd = bxt_get_cd;
396
397 intel_dsm_init(intel_host, &pdev->dev, host->mmc);
398
399 host->mmc_host_ops.start_signal_voltage_switch =
400 intel_start_signal_voltage_switch;
401
402 c->is_intel = true;
403
404 return 0;
405}
406
407static int intel_setup_host(struct platform_device *pdev)
408{
409 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
410 struct intel_host *intel_host = sdhci_acpi_priv(c);
411
412 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
413 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
414
415 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
416 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
417
418 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
419 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
420
421 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
422 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
423
424 return 0;
425}
426
427static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
428 .chip = &sdhci_acpi_chip_int,
429 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
430 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
431 MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
432 .flags = SDHCI_ACPI_RUNTIME_PM,
433 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
434 SDHCI_QUIRK_NO_LED,
435 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
436 SDHCI_QUIRK2_STOP_WITH_TC |
437 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
438 .probe_slot = intel_probe_slot,
439 .setup_host = intel_setup_host,
440 .priv_size = sizeof(struct intel_host),
441};
442
443static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
444 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
445 SDHCI_QUIRK_NO_LED |
446 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
447 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
448 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
449 MMC_CAP_WAIT_WHILE_BUSY,
450 .flags = SDHCI_ACPI_RUNTIME_PM,
451 .pm_caps = MMC_PM_KEEP_POWER,
452 .probe_slot = intel_probe_slot,
453 .setup_host = intel_setup_host,
454 .priv_size = sizeof(struct intel_host),
455};
456
457static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
458 .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
459 SDHCI_ACPI_RUNTIME_PM,
460 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
461 SDHCI_QUIRK_NO_LED,
462 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
463 SDHCI_QUIRK2_STOP_WITH_TC,
464 .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
465 .probe_slot = intel_probe_slot,
466 .setup_host = intel_setup_host,
467 .priv_size = sizeof(struct intel_host),
468};
469
470#define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8
471#define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac
472static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
473{
474 struct sdhci_host *host = ptr;
475
476 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
477 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
478
479 return IRQ_HANDLED;
480}
481
482static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
483{
484 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
485 struct sdhci_host *host = c->host;
486 int *irq = sdhci_acpi_priv(c);
487
488 *irq = -EINVAL;
489
490 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
491 return 0;
492
493 *irq = platform_get_irq(pdev, 1);
494 if (*irq < 0)
495 return 0;
496
497 return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
498 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
499 "sdhci_qcom", host);
500}
501
502static int qcom_free_slot(struct platform_device *pdev)
503{
504 struct device *dev = &pdev->dev;
505 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
506 struct sdhci_host *host = c->host;
507 struct acpi_device *adev;
508 int *irq = sdhci_acpi_priv(c);
509
510 adev = ACPI_COMPANION(dev);
511 if (!adev)
512 return -ENODEV;
513
514 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
515 return 0;
516
517 if (*irq < 0)
518 return 0;
519
520 free_irq(*irq, host);
521 return 0;
522}
523
524static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
525 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
526 .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
527 .caps = MMC_CAP_NONREMOVABLE,
528 .priv_size = sizeof(int),
529 .probe_slot = qcom_probe_slot,
530 .free_slot = qcom_free_slot,
531};
532
533static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
534 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
535 .caps = MMC_CAP_NONREMOVABLE,
536};
537
538struct amd_sdhci_host {
539 bool tuned_clock;
540 bool dll_enabled;
541};
542
543
544#define SDHCI_AMD_RESET_DLL_REGISTER 0x908
545
546static int amd_select_drive_strength(struct mmc_card *card,
547 unsigned int max_dtr, int host_drv,
548 int card_drv, int *drv_type)
549{
550 *drv_type = MMC_SET_DRIVER_TYPE_A;
551 return MMC_SET_DRIVER_TYPE_A;
552}
553
554static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
555{
556 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
557 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
558
559
560 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
561 usleep_range(10, 20);
562 if (enable)
563 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
564
565 amd_host->dll_enabled = enable;
566}
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
582{
583 struct sdhci_host *host = mmc_priv(mmc);
584 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
585 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
586 unsigned int old_timing = host->timing;
587 u16 val;
588
589 sdhci_set_ios(mmc, ios);
590
591 if (old_timing != host->timing && amd_host->tuned_clock) {
592 if (host->timing == MMC_TIMING_MMC_HS400 ||
593 host->timing == MMC_TIMING_MMC_HS200) {
594 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
595 val |= SDHCI_CTRL_TUNED_CLK;
596 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
597 } else {
598 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
599 val &= ~SDHCI_CTRL_TUNED_CLK;
600 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
601 }
602
603
604 if (host->timing == MMC_TIMING_MMC_HS400 &&
605 !amd_host->dll_enabled)
606 sdhci_acpi_amd_hs400_dll(host, true);
607 }
608}
609
610static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
611{
612 int err;
613 struct sdhci_host *host = mmc_priv(mmc);
614 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
615 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
616
617 amd_host->tuned_clock = false;
618
619 err = sdhci_execute_tuning(mmc, opcode);
620
621 if (!err && !host->tuning_err)
622 amd_host->tuned_clock = true;
623
624 return err;
625}
626
627static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
628{
629 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
630 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
631
632 if (mask & SDHCI_RESET_ALL) {
633 amd_host->tuned_clock = false;
634 sdhci_acpi_amd_hs400_dll(host, false);
635 }
636
637 sdhci_reset(host, mask);
638}
639
640static const struct sdhci_ops sdhci_acpi_ops_amd = {
641 .set_clock = sdhci_set_clock,
642 .set_bus_width = sdhci_set_bus_width,
643 .reset = amd_sdhci_reset,
644 .set_uhs_signaling = sdhci_set_uhs_signaling,
645};
646
647static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
648 .ops = &sdhci_acpi_ops_amd,
649};
650
651static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
652 struct acpi_device *adev)
653{
654 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
655 struct sdhci_host *host = c->host;
656
657 sdhci_read_caps(host);
658 if (host->caps1 & SDHCI_SUPPORT_DDR50)
659 host->mmc->caps = MMC_CAP_1_8V_DDR;
660
661 if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
662 (host->mmc->caps & MMC_CAP_1_8V_DDR))
663 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
701
702 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
703 host->mmc_host_ops.set_ios = amd_set_ios;
704 host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
705 return 0;
706}
707
708static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
709 .chip = &sdhci_acpi_chip_amd,
710 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
711 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
712 SDHCI_QUIRK_32BIT_DMA_SIZE |
713 SDHCI_QUIRK_32BIT_ADMA_SIZE,
714 .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
715 .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
716 .priv_size = sizeof(struct amd_sdhci_host),
717};
718
719struct sdhci_acpi_uid_slot {
720 const char *hid;
721 const char *uid;
722 const struct sdhci_acpi_slot *slot;
723};
724
725static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
726 { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
727 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
728 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
729 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
730 { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
731 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
732 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
733 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
734 { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
735 { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
736 { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
737 { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
738 { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
739 { "PNP0D40" },
740 { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
741 { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
742 { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
743 { },
744};
745
746static const struct acpi_device_id sdhci_acpi_ids[] = {
747 { "80865ACA" },
748 { "80865ACC" },
749 { "80865AD0" },
750 { "80860F14" },
751 { "80860F16" },
752 { "INT33BB" },
753 { "INT33C6" },
754 { "INT3436" },
755 { "INT344D" },
756 { "PNP0D40" },
757 { "QCOM8051" },
758 { "QCOM8052" },
759 { "AMDI0040" },
760 { },
761};
762MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
763
764static const struct dmi_system_id sdhci_acpi_quirks[] = {
765 {
766
767
768
769
770
771
772
773 .matches = {
774 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
775 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
776 },
777 .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
778 },
779 {
780
781
782
783
784
785 .matches = {
786 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
787 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
788 },
789 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
790 },
791 {}
792};
793
794static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
795{
796 const struct sdhci_acpi_uid_slot *u;
797
798 for (u = sdhci_acpi_uids; u->hid; u++) {
799 if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
800 return u->slot;
801 }
802 return NULL;
803}
804
805static int sdhci_acpi_probe(struct platform_device *pdev)
806{
807 struct device *dev = &pdev->dev;
808 const struct sdhci_acpi_slot *slot;
809 struct acpi_device *device, *child;
810 const struct dmi_system_id *id;
811 struct sdhci_acpi_host *c;
812 struct sdhci_host *host;
813 struct resource *iomem;
814 resource_size_t len;
815 size_t priv_size;
816 int quirks = 0;
817 int err;
818
819 device = ACPI_COMPANION(dev);
820 if (!device)
821 return -ENODEV;
822
823 id = dmi_first_match(sdhci_acpi_quirks);
824 if (id)
825 quirks = (long)id->driver_data;
826
827 slot = sdhci_acpi_get_slot(device);
828
829
830 acpi_device_fix_up_power(device);
831 if (!sdhci_acpi_no_fixup_child_power(device)) {
832 list_for_each_entry(child, &device->children, node)
833 if (child->status.present && child->status.enabled)
834 acpi_device_fix_up_power(child);
835 }
836
837 if (sdhci_acpi_byt_defer(dev))
838 return -EPROBE_DEFER;
839
840 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
841 if (!iomem)
842 return -ENOMEM;
843
844 len = resource_size(iomem);
845 if (len < 0x100)
846 dev_err(dev, "Invalid iomem size!\n");
847
848 if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
849 return -ENOMEM;
850
851 priv_size = slot ? slot->priv_size : 0;
852 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
853 if (IS_ERR(host))
854 return PTR_ERR(host);
855
856 c = sdhci_priv(host);
857 c->host = host;
858 c->slot = slot;
859 c->pdev = pdev;
860 c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
861
862 platform_set_drvdata(pdev, c);
863
864 host->hw_name = "ACPI";
865 host->ops = &sdhci_acpi_ops_dflt;
866 host->irq = platform_get_irq(pdev, 0);
867 if (host->irq < 0) {
868 err = -EINVAL;
869 goto err_free;
870 }
871
872 host->ioaddr = devm_ioremap(dev, iomem->start,
873 resource_size(iomem));
874 if (host->ioaddr == NULL) {
875 err = -ENOMEM;
876 goto err_free;
877 }
878
879 if (c->slot) {
880 if (c->slot->probe_slot) {
881 err = c->slot->probe_slot(pdev, device);
882 if (err)
883 goto err_free;
884 }
885 if (c->slot->chip) {
886 host->ops = c->slot->chip->ops;
887 host->quirks |= c->slot->chip->quirks;
888 host->quirks2 |= c->slot->chip->quirks2;
889 host->mmc->caps |= c->slot->chip->caps;
890 host->mmc->caps2 |= c->slot->chip->caps2;
891 host->mmc->pm_caps |= c->slot->chip->pm_caps;
892 }
893 host->quirks |= c->slot->quirks;
894 host->quirks2 |= c->slot->quirks2;
895 host->mmc->caps |= c->slot->caps;
896 host->mmc->caps2 |= c->slot->caps2;
897 host->mmc->pm_caps |= c->slot->pm_caps;
898 }
899
900 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
901
902 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
903 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
904
905 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
906 if (err) {
907 if (err == -EPROBE_DEFER)
908 goto err_free;
909 dev_warn(dev, "failed to setup card detect gpio\n");
910 c->use_runtime_pm = false;
911 }
912
913 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
914 c->reset_signal_volt_on_suspend = true;
915
916 if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
917 host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
918 }
919
920 err = sdhci_setup_host(host);
921 if (err)
922 goto err_free;
923
924 if (c->slot && c->slot->setup_host) {
925 err = c->slot->setup_host(pdev);
926 if (err)
927 goto err_cleanup;
928 }
929
930 err = __sdhci_add_host(host);
931 if (err)
932 goto err_cleanup;
933
934 if (c->use_runtime_pm) {
935 pm_runtime_set_active(dev);
936 pm_suspend_ignore_children(dev, 1);
937 pm_runtime_set_autosuspend_delay(dev, 50);
938 pm_runtime_use_autosuspend(dev);
939 pm_runtime_enable(dev);
940 }
941
942 device_enable_async_suspend(dev);
943
944 return 0;
945
946err_cleanup:
947 sdhci_cleanup_host(c->host);
948err_free:
949 if (c->slot && c->slot->free_slot)
950 c->slot->free_slot(pdev);
951
952 sdhci_free_host(c->host);
953 return err;
954}
955
956static int sdhci_acpi_remove(struct platform_device *pdev)
957{
958 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
959 struct device *dev = &pdev->dev;
960 int dead;
961
962 if (c->use_runtime_pm) {
963 pm_runtime_get_sync(dev);
964 pm_runtime_disable(dev);
965 pm_runtime_put_noidle(dev);
966 }
967
968 if (c->slot && c->slot->remove_slot)
969 c->slot->remove_slot(pdev);
970
971 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
972 sdhci_remove_host(c->host, dead);
973
974 if (c->slot && c->slot->free_slot)
975 c->slot->free_slot(pdev);
976
977 sdhci_free_host(c->host);
978
979 return 0;
980}
981
982static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
983 struct device *dev)
984{
985 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
986 struct sdhci_host *host = c->host;
987
988 if (c->is_intel && c->reset_signal_volt_on_suspend &&
989 host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
990 struct intel_host *intel_host = sdhci_acpi_priv(c);
991 unsigned int fn = INTEL_DSM_V33_SWITCH;
992 u32 result = 0;
993
994 intel_dsm(intel_host, dev, fn, &result);
995 }
996}
997
998#ifdef CONFIG_PM_SLEEP
999
1000static int sdhci_acpi_suspend(struct device *dev)
1001{
1002 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1003 struct sdhci_host *host = c->host;
1004 int ret;
1005
1006 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1007 mmc_retune_needed(host->mmc);
1008
1009 ret = sdhci_suspend_host(host);
1010 if (ret)
1011 return ret;
1012
1013 sdhci_acpi_reset_signal_voltage_if_needed(dev);
1014 return 0;
1015}
1016
1017static int sdhci_acpi_resume(struct device *dev)
1018{
1019 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1020
1021 sdhci_acpi_byt_setting(&c->pdev->dev);
1022
1023 return sdhci_resume_host(c->host);
1024}
1025
1026#endif
1027
1028#ifdef CONFIG_PM
1029
1030static int sdhci_acpi_runtime_suspend(struct device *dev)
1031{
1032 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1033 struct sdhci_host *host = c->host;
1034 int ret;
1035
1036 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1037 mmc_retune_needed(host->mmc);
1038
1039 ret = sdhci_runtime_suspend_host(host);
1040 if (ret)
1041 return ret;
1042
1043 sdhci_acpi_reset_signal_voltage_if_needed(dev);
1044 return 0;
1045}
1046
1047static int sdhci_acpi_runtime_resume(struct device *dev)
1048{
1049 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1050
1051 sdhci_acpi_byt_setting(&c->pdev->dev);
1052
1053 return sdhci_runtime_resume_host(c->host, 0);
1054}
1055
1056#endif
1057
1058static const struct dev_pm_ops sdhci_acpi_pm_ops = {
1059 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
1060 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
1061 sdhci_acpi_runtime_resume, NULL)
1062};
1063
1064static struct platform_driver sdhci_acpi_driver = {
1065 .driver = {
1066 .name = "sdhci-acpi",
1067 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1068 .acpi_match_table = sdhci_acpi_ids,
1069 .pm = &sdhci_acpi_pm_ops,
1070 },
1071 .probe = sdhci_acpi_probe,
1072 .remove = sdhci_acpi_remove,
1073};
1074
1075module_platform_driver(sdhci_acpi_driver);
1076
1077MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
1078MODULE_AUTHOR("Adrian Hunter");
1079MODULE_LICENSE("GPL v2");
1080