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20#include <linux/delay.h>
21#include <linux/export.h>
22#include <linux/gpio.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/platform_data/b53.h>
26#include <linux/phy.h>
27#include <linux/phylink.h>
28#include <linux/etherdevice.h>
29#include <linux/if_bridge.h>
30#include <net/dsa.h>
31
32#include "b53_regs.h"
33#include "b53_priv.h"
34
35struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39};
40
41
42static const struct b53_mib_desc b53_mibs_65[] = {
43 { 8, 0x00, "TxOctets" },
44 { 4, 0x08, "TxDropPkts" },
45 { 4, 0x10, "TxBroadcastPkts" },
46 { 4, 0x14, "TxMulticastPkts" },
47 { 4, 0x18, "TxUnicastPkts" },
48 { 4, 0x1c, "TxCollisions" },
49 { 4, 0x20, "TxSingleCollision" },
50 { 4, 0x24, "TxMultipleCollision" },
51 { 4, 0x28, "TxDeferredTransmit" },
52 { 4, 0x2c, "TxLateCollision" },
53 { 4, 0x30, "TxExcessiveCollision" },
54 { 4, 0x38, "TxPausePkts" },
55 { 8, 0x44, "RxOctets" },
56 { 4, 0x4c, "RxUndersizePkts" },
57 { 4, 0x50, "RxPausePkts" },
58 { 4, 0x54, "Pkts64Octets" },
59 { 4, 0x58, "Pkts65to127Octets" },
60 { 4, 0x5c, "Pkts128to255Octets" },
61 { 4, 0x60, "Pkts256to511Octets" },
62 { 4, 0x64, "Pkts512to1023Octets" },
63 { 4, 0x68, "Pkts1024to1522Octets" },
64 { 4, 0x6c, "RxOversizePkts" },
65 { 4, 0x70, "RxJabbers" },
66 { 4, 0x74, "RxAlignmentErrors" },
67 { 4, 0x78, "RxFCSErrors" },
68 { 8, 0x7c, "RxGoodOctets" },
69 { 4, 0x84, "RxDropPkts" },
70 { 4, 0x88, "RxUnicastPkts" },
71 { 4, 0x8c, "RxMulticastPkts" },
72 { 4, 0x90, "RxBroadcastPkts" },
73 { 4, 0x94, "RxSAChanges" },
74 { 4, 0x98, "RxFragments" },
75};
76
77#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
78
79
80static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123};
124
125#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
126
127
128static const struct b53_mib_desc b53_mibs[] = {
129 { 8, 0x00, "TxOctets" },
130 { 4, 0x08, "TxDropPkts" },
131 { 4, 0x10, "TxBroadcastPkts" },
132 { 4, 0x14, "TxMulticastPkts" },
133 { 4, 0x18, "TxUnicastPkts" },
134 { 4, 0x1c, "TxCollisions" },
135 { 4, 0x20, "TxSingleCollision" },
136 { 4, 0x24, "TxMultipleCollision" },
137 { 4, 0x28, "TxDeferredTransmit" },
138 { 4, 0x2c, "TxLateCollision" },
139 { 4, 0x30, "TxExcessiveCollision" },
140 { 4, 0x38, "TxPausePkts" },
141 { 8, 0x50, "RxOctets" },
142 { 4, 0x58, "RxUndersizePkts" },
143 { 4, 0x5c, "RxPausePkts" },
144 { 4, 0x60, "Pkts64Octets" },
145 { 4, 0x64, "Pkts65to127Octets" },
146 { 4, 0x68, "Pkts128to255Octets" },
147 { 4, 0x6c, "Pkts256to511Octets" },
148 { 4, 0x70, "Pkts512to1023Octets" },
149 { 4, 0x74, "Pkts1024to1522Octets" },
150 { 4, 0x78, "RxOversizePkts" },
151 { 4, 0x7c, "RxJabbers" },
152 { 4, 0x80, "RxAlignmentErrors" },
153 { 4, 0x84, "RxFCSErrors" },
154 { 8, 0x88, "RxGoodOctets" },
155 { 4, 0x90, "RxDropPkts" },
156 { 4, 0x94, "RxUnicastPkts" },
157 { 4, 0x98, "RxMulticastPkts" },
158 { 4, 0x9c, "RxBroadcastPkts" },
159 { 4, 0xa0, "RxSAChanges" },
160 { 4, 0xa4, "RxFragments" },
161 { 4, 0xa8, "RxJumboPkts" },
162 { 4, 0xac, "RxSymbolErrors" },
163 { 4, 0xc0, "RxDiscarded" },
164};
165
166#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
167
168static const struct b53_mib_desc b53_mibs_58xx[] = {
169 { 8, 0x00, "TxOctets" },
170 { 4, 0x08, "TxDropPkts" },
171 { 4, 0x0c, "TxQPKTQ0" },
172 { 4, 0x10, "TxBroadcastPkts" },
173 { 4, 0x14, "TxMulticastPkts" },
174 { 4, 0x18, "TxUnicastPKts" },
175 { 4, 0x1c, "TxCollisions" },
176 { 4, 0x20, "TxSingleCollision" },
177 { 4, 0x24, "TxMultipleCollision" },
178 { 4, 0x28, "TxDeferredCollision" },
179 { 4, 0x2c, "TxLateCollision" },
180 { 4, 0x30, "TxExcessiveCollision" },
181 { 4, 0x34, "TxFrameInDisc" },
182 { 4, 0x38, "TxPausePkts" },
183 { 4, 0x3c, "TxQPKTQ1" },
184 { 4, 0x40, "TxQPKTQ2" },
185 { 4, 0x44, "TxQPKTQ3" },
186 { 4, 0x48, "TxQPKTQ4" },
187 { 4, 0x4c, "TxQPKTQ5" },
188 { 8, 0x50, "RxOctets" },
189 { 4, 0x58, "RxUndersizePkts" },
190 { 4, 0x5c, "RxPausePkts" },
191 { 4, 0x60, "RxPkts64Octets" },
192 { 4, 0x64, "RxPkts65to127Octets" },
193 { 4, 0x68, "RxPkts128to255Octets" },
194 { 4, 0x6c, "RxPkts256to511Octets" },
195 { 4, 0x70, "RxPkts512to1023Octets" },
196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
197 { 4, 0x78, "RxOversizePkts" },
198 { 4, 0x7c, "RxJabbers" },
199 { 4, 0x80, "RxAlignmentErrors" },
200 { 4, 0x84, "RxFCSErrors" },
201 { 8, 0x88, "RxGoodOctets" },
202 { 4, 0x90, "RxDropPkts" },
203 { 4, 0x94, "RxUnicastPkts" },
204 { 4, 0x98, "RxMulticastPkts" },
205 { 4, 0x9c, "RxBroadcastPkts" },
206 { 4, 0xa0, "RxSAChanges" },
207 { 4, 0xa4, "RxFragments" },
208 { 4, 0xa8, "RxJumboPkt" },
209 { 4, 0xac, "RxSymblErr" },
210 { 4, 0xb0, "InRangeErrCount" },
211 { 4, 0xb4, "OutRangeErrCount" },
212 { 4, 0xb8, "EEELpiEvent" },
213 { 4, 0xbc, "EEELpiDuration" },
214 { 4, 0xc0, "RxDiscard" },
215 { 4, 0xc8, "TxQPKTQ6" },
216 { 4, 0xcc, "TxQPKTQ7" },
217 { 4, 0xd0, "TxPkts64Octets" },
218 { 4, 0xd4, "TxPkts65to127Octets" },
219 { 4, 0xd8, "TxPkts128to255Octets" },
220 { 4, 0xdc, "TxPkts256to511Ocets" },
221 { 4, 0xe0, "TxPkts512to1023Ocets" },
222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
223};
224
225#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
226
227static int b53_do_vlan_op(struct b53_device *dev, u8 op)
228{
229 unsigned int i;
230
231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
232
233 for (i = 0; i < 10; i++) {
234 u8 vta;
235
236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
237 if (!(vta & VTA_START_CMD))
238 return 0;
239
240 usleep_range(100, 200);
241 }
242
243 return -EIO;
244}
245
246static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
247 struct b53_vlan *vlan)
248{
249 if (is5325(dev)) {
250 u32 entry = 0;
251
252 if (vlan->members) {
253 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
254 VA_UNTAG_S_25) | vlan->members;
255 if (dev->core_rev >= 3)
256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
257 else
258 entry |= VA_VALID_25;
259 }
260
261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
263 VTA_RW_STATE_WR | VTA_RW_OP_EN);
264 } else if (is5365(dev)) {
265 u16 entry = 0;
266
267 if (vlan->members)
268 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
270
271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
273 VTA_RW_STATE_WR | VTA_RW_OP_EN);
274 } else {
275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
277 (vlan->untag << VTE_UNTAG_S) | vlan->members);
278
279 b53_do_vlan_op(dev, VTA_CMD_WRITE);
280 }
281
282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
283 vid, vlan->members, vlan->untag);
284}
285
286static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
287 struct b53_vlan *vlan)
288{
289 if (is5325(dev)) {
290 u32 entry = 0;
291
292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
293 VTA_RW_STATE_RD | VTA_RW_OP_EN);
294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
295
296 if (dev->core_rev >= 3)
297 vlan->valid = !!(entry & VA_VALID_25_R4);
298 else
299 vlan->valid = !!(entry & VA_VALID_25);
300 vlan->members = entry & VA_MEMBER_MASK;
301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
302
303 } else if (is5365(dev)) {
304 u16 entry = 0;
305
306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
307 VTA_RW_STATE_WR | VTA_RW_OP_EN);
308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
309
310 vlan->valid = !!(entry & VA_VALID_65);
311 vlan->members = entry & VA_MEMBER_MASK;
312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
313 } else {
314 u32 entry = 0;
315
316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
317 b53_do_vlan_op(dev, VTA_CMD_READ);
318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
319 vlan->members = entry & VTE_MEMBERS;
320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
321 vlan->valid = true;
322 }
323}
324
325static void b53_set_forwarding(struct b53_device *dev, int enable)
326{
327 u8 mgmt;
328
329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
330
331 if (enable)
332 mgmt |= SM_SW_FWD_EN;
333 else
334 mgmt &= ~SM_SW_FWD_EN;
335
336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
337
338
339
340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
341 mgmt |= B53_MII_DUMB_FWDG_EN;
342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
343
344
345
346
347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
350}
351
352static void b53_enable_vlan(struct b53_device *dev, bool enable,
353 bool enable_filtering)
354{
355 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
360
361 if (is5325(dev) || is5365(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
364 } else if (is63xx(dev)) {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
367 } else {
368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
370 }
371
372 if (enable) {
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
376 if (enable_filtering) {
377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
378 vc5 |= VC5_DROP_VTABLE_MISS;
379 } else {
380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
381 vc5 &= ~VC5_DROP_VTABLE_MISS;
382 }
383
384 if (is5325(dev))
385 vc0 &= ~VC0_RESERVED_1;
386
387 if (is5325(dev) || is5365(dev))
388 vc1 |= VC1_RX_MCST_TAG_EN;
389
390 } else {
391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
393 vc4 &= ~VC4_ING_VID_CHECK_MASK;
394 vc5 &= ~VC5_DROP_VTABLE_MISS;
395
396 if (is5325(dev) || is5365(dev))
397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
398 else
399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
400
401 if (is5325(dev) || is5365(dev))
402 vc1 &= ~VC1_RX_MCST_TAG_EN;
403 }
404
405 if (!is5325(dev) && !is5365(dev))
406 vc5 &= ~VC5_VID_FFF_EN;
407
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
410
411 if (is5325(dev) || is5365(dev)) {
412
413 if (is5325(dev) && enable)
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
415 VC3_HIGH_8BIT_EN);
416 else
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
418
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
421 } else if (is63xx(dev)) {
422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
425 } else {
426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
429 }
430
431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
432
433 dev->vlan_enabled = enable;
434}
435
436static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
437{
438 u32 port_mask = 0;
439 u16 max_size = JMS_MIN_SIZE;
440
441 if (is5325(dev) || is5365(dev))
442 return -EINVAL;
443
444 if (enable) {
445 port_mask = dev->enabled_ports;
446 max_size = JMS_MAX_SIZE;
447 if (allow_10_100)
448 port_mask |= JPM_10_100_JUMBO_EN;
449 }
450
451 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
452 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
453}
454
455static int b53_flush_arl(struct b53_device *dev, u8 mask)
456{
457 unsigned int i;
458
459 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
460 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
461
462 for (i = 0; i < 10; i++) {
463 u8 fast_age_ctrl;
464
465 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
466 &fast_age_ctrl);
467
468 if (!(fast_age_ctrl & FAST_AGE_DONE))
469 goto out;
470
471 msleep(1);
472 }
473
474 return -ETIMEDOUT;
475out:
476
477 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
478 return 0;
479}
480
481static int b53_fast_age_port(struct b53_device *dev, int port)
482{
483 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
484
485 return b53_flush_arl(dev, FAST_AGE_PORT);
486}
487
488static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
489{
490 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
491
492 return b53_flush_arl(dev, FAST_AGE_VLAN);
493}
494
495void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
496{
497 struct b53_device *dev = ds->priv;
498 unsigned int i;
499 u16 pvlan;
500
501
502
503
504
505 b53_for_each_port(dev, i) {
506 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
507 pvlan |= BIT(cpu_port);
508 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
509 }
510}
511EXPORT_SYMBOL(b53_imp_vlan_setup);
512
513int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
514{
515 struct b53_device *dev = ds->priv;
516 unsigned int cpu_port;
517 int ret = 0;
518 u16 pvlan;
519
520 if (!dsa_is_user_port(ds, port))
521 return 0;
522
523 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
524
525 b53_br_egress_floods(ds, port, true, true);
526
527 if (dev->ops->irq_enable)
528 ret = dev->ops->irq_enable(dev, port);
529 if (ret)
530 return ret;
531
532
533 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
534
535
536
537
538
539 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
540 pvlan &= ~0x1ff;
541 pvlan |= BIT(port);
542 pvlan |= dev->ports[port].vlan_ctl_mask;
543 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
544
545 b53_imp_vlan_setup(ds, cpu_port);
546
547
548 if (dev->ports[port].eee.eee_enabled)
549 b53_eee_enable_set(ds, port, true);
550
551 return 0;
552}
553EXPORT_SYMBOL(b53_enable_port);
554
555void b53_disable_port(struct dsa_switch *ds, int port)
556{
557 struct b53_device *dev = ds->priv;
558 u8 reg;
559
560
561 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
562 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
563 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
564
565 if (dev->ops->irq_disable)
566 dev->ops->irq_disable(dev, port);
567}
568EXPORT_SYMBOL(b53_disable_port);
569
570void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
571{
572 struct b53_device *dev = ds->priv;
573 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
574 u8 hdr_ctl, val;
575 u16 reg;
576
577
578 switch (port) {
579 case 8:
580 val = BRCM_HDR_P8_EN;
581 break;
582 case 7:
583 val = BRCM_HDR_P7_EN;
584 break;
585 case 5:
586 val = BRCM_HDR_P5_EN;
587 break;
588 default:
589 val = 0;
590 break;
591 }
592
593
594 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
595 if (tag_en)
596 hdr_ctl |= SM_SW_FWD_MODE;
597 else
598 hdr_ctl &= ~SM_SW_FWD_MODE;
599 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
600
601
602 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
603 if (port == 8)
604 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
605 else if (port == 5)
606 hdr_ctl |= GC_FRM_MGMT_PORT_M;
607 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
608
609
610 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
611 if (tag_en)
612 hdr_ctl |= val;
613 else
614 hdr_ctl &= ~val;
615 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
616
617
618 if (!is58xx(dev))
619 return;
620
621
622
623
624 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
625 if (tag_en)
626 reg &= ~BIT(port);
627 else
628 reg |= BIT(port);
629 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
630
631
632
633
634 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
635 if (tag_en)
636 reg &= ~BIT(port);
637 else
638 reg |= BIT(port);
639 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
640}
641EXPORT_SYMBOL(b53_brcm_hdr_setup);
642
643static void b53_enable_cpu_port(struct b53_device *dev, int port)
644{
645 u8 port_ctrl;
646
647
648 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
649 port = B53_CPU_PORT;
650
651 port_ctrl = PORT_CTRL_RX_BCST_EN |
652 PORT_CTRL_RX_MCST_EN |
653 PORT_CTRL_RX_UCST_EN;
654 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
655
656 b53_brcm_hdr_setup(dev->ds, port);
657
658 b53_br_egress_floods(dev->ds, port, true, true);
659}
660
661static void b53_enable_mib(struct b53_device *dev)
662{
663 u8 gc;
664
665 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
666 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
667 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
668}
669
670static u16 b53_default_pvid(struct b53_device *dev)
671{
672 if (is5325(dev) || is5365(dev))
673 return 1;
674 else
675 return 0;
676}
677
678int b53_configure_vlan(struct dsa_switch *ds)
679{
680 struct b53_device *dev = ds->priv;
681 struct b53_vlan vl = { 0 };
682 struct b53_vlan *v;
683 int i, def_vid;
684 u16 vid;
685
686 def_vid = b53_default_pvid(dev);
687
688
689 if (is5325(dev) || is5365(dev)) {
690 for (i = def_vid; i < dev->num_vlans; i++)
691 b53_set_vlan_entry(dev, i, &vl);
692 } else {
693 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
694 }
695
696 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering);
697
698 b53_for_each_port(dev, i)
699 b53_write16(dev, B53_VLAN_PAGE,
700 B53_VLAN_PORT_DEF_TAG(i), def_vid);
701
702
703
704
705 for (vid = def_vid; vid < dev->num_vlans; vid++) {
706 v = &dev->vlans[vid];
707
708 if (!v->members)
709 continue;
710
711 b53_set_vlan_entry(dev, vid, v);
712 b53_fast_age_vlan(dev, vid);
713 }
714
715 return 0;
716}
717EXPORT_SYMBOL(b53_configure_vlan);
718
719static void b53_switch_reset_gpio(struct b53_device *dev)
720{
721 int gpio = dev->reset_gpio;
722
723 if (gpio < 0)
724 return;
725
726
727
728 gpio_set_value(gpio, 0);
729 mdelay(50);
730
731 gpio_set_value(gpio, 1);
732 mdelay(20);
733
734 dev->current_page = 0xff;
735}
736
737static int b53_switch_reset(struct b53_device *dev)
738{
739 unsigned int timeout = 1000;
740 u8 mgmt, reg;
741
742 b53_switch_reset_gpio(dev);
743
744 if (is539x(dev)) {
745 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
746 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
747 }
748
749
750
751
752
753
754 if (dev->chip_id == BCM58XX_DEVICE_ID ||
755 dev->chip_id == BCM583XX_DEVICE_ID) {
756 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
757 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
758 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
759
760 do {
761 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
762 if (!(reg & SW_RST))
763 break;
764
765 usleep_range(1000, 2000);
766 } while (timeout-- > 0);
767
768 if (timeout == 0) {
769 dev_err(dev->dev,
770 "Timeout waiting for SW_RST to clear!\n");
771 return -ETIMEDOUT;
772 }
773 }
774
775 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
776
777 if (!(mgmt & SM_SW_FWD_EN)) {
778 mgmt &= ~SM_SW_FWD_MODE;
779 mgmt |= SM_SW_FWD_EN;
780
781 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
782 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
783
784 if (!(mgmt & SM_SW_FWD_EN)) {
785 dev_err(dev->dev, "Failed to enable switch!\n");
786 return -EINVAL;
787 }
788 }
789
790 b53_enable_mib(dev);
791
792 return b53_flush_arl(dev, FAST_AGE_STATIC);
793}
794
795static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
796{
797 struct b53_device *priv = ds->priv;
798 u16 value = 0;
799 int ret;
800
801 if (priv->ops->phy_read16)
802 ret = priv->ops->phy_read16(priv, addr, reg, &value);
803 else
804 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
805 reg * 2, &value);
806
807 return ret ? ret : value;
808}
809
810static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
811{
812 struct b53_device *priv = ds->priv;
813
814 if (priv->ops->phy_write16)
815 return priv->ops->phy_write16(priv, addr, reg, val);
816
817 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
818}
819
820static int b53_reset_switch(struct b53_device *priv)
821{
822
823 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
824 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
825
826 priv->serdes_lane = B53_INVALID_LANE;
827
828 return b53_switch_reset(priv);
829}
830
831static int b53_apply_config(struct b53_device *priv)
832{
833
834 b53_set_forwarding(priv, 0);
835
836 b53_configure_vlan(priv->ds);
837
838
839 b53_set_forwarding(priv, 1);
840
841 return 0;
842}
843
844static void b53_reset_mib(struct b53_device *priv)
845{
846 u8 gc;
847
848 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
849
850 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
851 msleep(1);
852 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
853 msleep(1);
854}
855
856static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
857{
858 if (is5365(dev))
859 return b53_mibs_65;
860 else if (is63xx(dev))
861 return b53_mibs_63xx;
862 else if (is58xx(dev))
863 return b53_mibs_58xx;
864 else
865 return b53_mibs;
866}
867
868static unsigned int b53_get_mib_size(struct b53_device *dev)
869{
870 if (is5365(dev))
871 return B53_MIBS_65_SIZE;
872 else if (is63xx(dev))
873 return B53_MIBS_63XX_SIZE;
874 else if (is58xx(dev))
875 return B53_MIBS_58XX_SIZE;
876 else
877 return B53_MIBS_SIZE;
878}
879
880static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
881{
882
883 switch (port) {
884 case B53_CPU_PORT_25:
885 case 7:
886 case B53_CPU_PORT:
887 return NULL;
888 }
889
890 return mdiobus_get_phy(ds->slave_mii_bus, port);
891}
892
893void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
894 uint8_t *data)
895{
896 struct b53_device *dev = ds->priv;
897 const struct b53_mib_desc *mibs = b53_get_mib(dev);
898 unsigned int mib_size = b53_get_mib_size(dev);
899 struct phy_device *phydev;
900 unsigned int i;
901
902 if (stringset == ETH_SS_STATS) {
903 for (i = 0; i < mib_size; i++)
904 strlcpy(data + i * ETH_GSTRING_LEN,
905 mibs[i].name, ETH_GSTRING_LEN);
906 } else if (stringset == ETH_SS_PHY_STATS) {
907 phydev = b53_get_phy_device(ds, port);
908 if (!phydev)
909 return;
910
911 phy_ethtool_get_strings(phydev, data);
912 }
913}
914EXPORT_SYMBOL(b53_get_strings);
915
916void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
917{
918 struct b53_device *dev = ds->priv;
919 const struct b53_mib_desc *mibs = b53_get_mib(dev);
920 unsigned int mib_size = b53_get_mib_size(dev);
921 const struct b53_mib_desc *s;
922 unsigned int i;
923 u64 val = 0;
924
925 if (is5365(dev) && port == 5)
926 port = 8;
927
928 mutex_lock(&dev->stats_mutex);
929
930 for (i = 0; i < mib_size; i++) {
931 s = &mibs[i];
932
933 if (s->size == 8) {
934 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
935 } else {
936 u32 val32;
937
938 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
939 &val32);
940 val = val32;
941 }
942 data[i] = (u64)val;
943 }
944
945 mutex_unlock(&dev->stats_mutex);
946}
947EXPORT_SYMBOL(b53_get_ethtool_stats);
948
949void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
950{
951 struct phy_device *phydev;
952
953 phydev = b53_get_phy_device(ds, port);
954 if (!phydev)
955 return;
956
957 phy_ethtool_get_stats(phydev, NULL, data);
958}
959EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
960
961int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
962{
963 struct b53_device *dev = ds->priv;
964 struct phy_device *phydev;
965
966 if (sset == ETH_SS_STATS) {
967 return b53_get_mib_size(dev);
968 } else if (sset == ETH_SS_PHY_STATS) {
969 phydev = b53_get_phy_device(ds, port);
970 if (!phydev)
971 return 0;
972
973 return phy_ethtool_get_sset_count(phydev);
974 }
975
976 return 0;
977}
978EXPORT_SYMBOL(b53_get_sset_count);
979
980enum b53_devlink_resource_id {
981 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
982};
983
984static u64 b53_devlink_vlan_table_get(void *priv)
985{
986 struct b53_device *dev = priv;
987 struct b53_vlan *vl;
988 unsigned int i;
989 u64 count = 0;
990
991 for (i = 0; i < dev->num_vlans; i++) {
992 vl = &dev->vlans[i];
993 if (vl->members)
994 count++;
995 }
996
997 return count;
998}
999
1000int b53_setup_devlink_resources(struct dsa_switch *ds)
1001{
1002 struct devlink_resource_size_params size_params;
1003 struct b53_device *dev = ds->priv;
1004 int err;
1005
1006 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1007 dev->num_vlans,
1008 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1009
1010 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1011 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1012 DEVLINK_RESOURCE_ID_PARENT_TOP,
1013 &size_params);
1014 if (err)
1015 goto out;
1016
1017 dsa_devlink_resource_occ_get_register(ds,
1018 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1019 b53_devlink_vlan_table_get, dev);
1020
1021 return 0;
1022out:
1023 dsa_devlink_resources_unregister(ds);
1024 return err;
1025}
1026EXPORT_SYMBOL(b53_setup_devlink_resources);
1027
1028static int b53_setup(struct dsa_switch *ds)
1029{
1030 struct b53_device *dev = ds->priv;
1031 unsigned int port;
1032 int ret;
1033
1034 ret = b53_reset_switch(dev);
1035 if (ret) {
1036 dev_err(ds->dev, "failed to reset switch\n");
1037 return ret;
1038 }
1039
1040 b53_reset_mib(dev);
1041
1042 ret = b53_apply_config(dev);
1043 if (ret) {
1044 dev_err(ds->dev, "failed to apply configuration\n");
1045 return ret;
1046 }
1047
1048
1049
1050
1051 for (port = 0; port < dev->num_ports; port++) {
1052 if (dsa_is_cpu_port(ds, port))
1053 b53_enable_cpu_port(dev, port);
1054 else
1055 b53_disable_port(ds, port);
1056 }
1057
1058
1059
1060
1061
1062
1063 ds->vlan_filtering_is_global = true;
1064
1065 return b53_setup_devlink_resources(ds);
1066}
1067
1068static void b53_teardown(struct dsa_switch *ds)
1069{
1070 dsa_devlink_resources_unregister(ds);
1071}
1072
1073static void b53_force_link(struct b53_device *dev, int port, int link)
1074{
1075 u8 reg, val, off;
1076
1077
1078 if (port == dev->cpu_port) {
1079 off = B53_PORT_OVERRIDE_CTRL;
1080 val = PORT_OVERRIDE_EN;
1081 } else {
1082 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1083 val = GMII_PO_EN;
1084 }
1085
1086 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1087 reg |= val;
1088 if (link)
1089 reg |= PORT_OVERRIDE_LINK;
1090 else
1091 reg &= ~PORT_OVERRIDE_LINK;
1092 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1093}
1094
1095static void b53_force_port_config(struct b53_device *dev, int port,
1096 int speed, int duplex,
1097 bool tx_pause, bool rx_pause)
1098{
1099 u8 reg, val, off;
1100
1101
1102 if (port == dev->cpu_port) {
1103 off = B53_PORT_OVERRIDE_CTRL;
1104 val = PORT_OVERRIDE_EN;
1105 } else {
1106 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1107 val = GMII_PO_EN;
1108 }
1109
1110 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1111 reg |= val;
1112 if (duplex == DUPLEX_FULL)
1113 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1114 else
1115 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1116
1117 switch (speed) {
1118 case 2000:
1119 reg |= PORT_OVERRIDE_SPEED_2000M;
1120 fallthrough;
1121 case SPEED_1000:
1122 reg |= PORT_OVERRIDE_SPEED_1000M;
1123 break;
1124 case SPEED_100:
1125 reg |= PORT_OVERRIDE_SPEED_100M;
1126 break;
1127 case SPEED_10:
1128 reg |= PORT_OVERRIDE_SPEED_10M;
1129 break;
1130 default:
1131 dev_err(dev->dev, "unknown speed: %d\n", speed);
1132 return;
1133 }
1134
1135 if (rx_pause)
1136 reg |= PORT_OVERRIDE_RX_FLOW;
1137 if (tx_pause)
1138 reg |= PORT_OVERRIDE_TX_FLOW;
1139
1140 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1141}
1142
1143static void b53_adjust_link(struct dsa_switch *ds, int port,
1144 struct phy_device *phydev)
1145{
1146 struct b53_device *dev = ds->priv;
1147 struct ethtool_eee *p = &dev->ports[port].eee;
1148 u8 rgmii_ctrl = 0, reg = 0, off;
1149 bool tx_pause = false;
1150 bool rx_pause = false;
1151
1152 if (!phy_is_pseudo_fixed_link(phydev))
1153 return;
1154
1155
1156 if (is5301x(dev) && port == dev->cpu_port)
1157 tx_pause = rx_pause = true;
1158
1159 if (phydev->pause) {
1160 if (phydev->asym_pause)
1161 tx_pause = true;
1162 rx_pause = true;
1163 }
1164
1165 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1166 tx_pause, rx_pause);
1167 b53_force_link(dev, port, phydev->link);
1168
1169 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1170 if (port == 8)
1171 off = B53_RGMII_CTRL_IMP;
1172 else
1173 off = B53_RGMII_CTRL_P(port);
1174
1175
1176
1177
1178 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1179 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1180 RGMII_CTRL_TIMING_SEL);
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1197 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1198 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1199 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1200 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1201 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1202
1203 dev_info(ds->dev, "Configured port %d for %s\n", port,
1204 phy_modes(phydev->interface));
1205 }
1206
1207
1208 if (is5325(dev)) {
1209 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1210 ®);
1211
1212
1213 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1214 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1215 reg | PORT_OVERRIDE_RV_MII_25);
1216 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1217 ®);
1218
1219 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1220 dev_err(ds->dev,
1221 "Failed to enable reverse MII mode\n");
1222 return;
1223 }
1224 }
1225 } else if (is5301x(dev)) {
1226 if (port != dev->cpu_port) {
1227 b53_force_port_config(dev, dev->cpu_port, 2000,
1228 DUPLEX_FULL, true, true);
1229 b53_force_link(dev, dev->cpu_port, 1);
1230 }
1231 }
1232
1233
1234 p->eee_enabled = b53_eee_init(ds, port, phydev);
1235}
1236
1237void b53_port_event(struct dsa_switch *ds, int port)
1238{
1239 struct b53_device *dev = ds->priv;
1240 bool link;
1241 u16 sts;
1242
1243 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1244 link = !!(sts & BIT(port));
1245 dsa_port_phylink_mac_change(ds, port, link);
1246}
1247EXPORT_SYMBOL(b53_port_event);
1248
1249void b53_phylink_validate(struct dsa_switch *ds, int port,
1250 unsigned long *supported,
1251 struct phylink_link_state *state)
1252{
1253 struct b53_device *dev = ds->priv;
1254 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1255
1256 if (dev->ops->serdes_phylink_validate)
1257 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1258
1259
1260 phylink_set(mask, Autoneg);
1261 phylink_set_port_modes(mask);
1262 phylink_set(mask, Pause);
1263 phylink_set(mask, Asym_Pause);
1264
1265
1266
1267
1268 if (state->interface != PHY_INTERFACE_MODE_MII &&
1269 state->interface != PHY_INTERFACE_MODE_REVMII &&
1270 !phy_interface_mode_is_8023z(state->interface) &&
1271 !(is5325(dev) || is5365(dev))) {
1272 phylink_set(mask, 1000baseT_Full);
1273 phylink_set(mask, 1000baseT_Half);
1274 }
1275
1276 if (!phy_interface_mode_is_8023z(state->interface)) {
1277 phylink_set(mask, 10baseT_Half);
1278 phylink_set(mask, 10baseT_Full);
1279 phylink_set(mask, 100baseT_Half);
1280 phylink_set(mask, 100baseT_Full);
1281 }
1282
1283 bitmap_and(supported, supported, mask,
1284 __ETHTOOL_LINK_MODE_MASK_NBITS);
1285 bitmap_and(state->advertising, state->advertising, mask,
1286 __ETHTOOL_LINK_MODE_MASK_NBITS);
1287
1288 phylink_helper_basex_speed(state);
1289}
1290EXPORT_SYMBOL(b53_phylink_validate);
1291
1292int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1293 struct phylink_link_state *state)
1294{
1295 struct b53_device *dev = ds->priv;
1296 int ret = -EOPNOTSUPP;
1297
1298 if ((phy_interface_mode_is_8023z(state->interface) ||
1299 state->interface == PHY_INTERFACE_MODE_SGMII) &&
1300 dev->ops->serdes_link_state)
1301 ret = dev->ops->serdes_link_state(dev, port, state);
1302
1303 return ret;
1304}
1305EXPORT_SYMBOL(b53_phylink_mac_link_state);
1306
1307void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1308 unsigned int mode,
1309 const struct phylink_link_state *state)
1310{
1311 struct b53_device *dev = ds->priv;
1312
1313 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED)
1314 return;
1315
1316 if ((phy_interface_mode_is_8023z(state->interface) ||
1317 state->interface == PHY_INTERFACE_MODE_SGMII) &&
1318 dev->ops->serdes_config)
1319 dev->ops->serdes_config(dev, port, mode, state);
1320}
1321EXPORT_SYMBOL(b53_phylink_mac_config);
1322
1323void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1324{
1325 struct b53_device *dev = ds->priv;
1326
1327 if (dev->ops->serdes_an_restart)
1328 dev->ops->serdes_an_restart(dev, port);
1329}
1330EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1331
1332void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1333 unsigned int mode,
1334 phy_interface_t interface)
1335{
1336 struct b53_device *dev = ds->priv;
1337
1338 if (mode == MLO_AN_PHY)
1339 return;
1340
1341 if (mode == MLO_AN_FIXED) {
1342 b53_force_link(dev, port, false);
1343 return;
1344 }
1345
1346 if (phy_interface_mode_is_8023z(interface) &&
1347 dev->ops->serdes_link_set)
1348 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1349}
1350EXPORT_SYMBOL(b53_phylink_mac_link_down);
1351
1352void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1353 unsigned int mode,
1354 phy_interface_t interface,
1355 struct phy_device *phydev,
1356 int speed, int duplex,
1357 bool tx_pause, bool rx_pause)
1358{
1359 struct b53_device *dev = ds->priv;
1360
1361 if (mode == MLO_AN_PHY)
1362 return;
1363
1364 if (mode == MLO_AN_FIXED) {
1365 b53_force_port_config(dev, port, speed, duplex,
1366 tx_pause, rx_pause);
1367 b53_force_link(dev, port, true);
1368 return;
1369 }
1370
1371 if (phy_interface_mode_is_8023z(interface) &&
1372 dev->ops->serdes_link_set)
1373 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1374}
1375EXPORT_SYMBOL(b53_phylink_mac_link_up);
1376
1377int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1378 struct switchdev_trans *trans)
1379{
1380 struct b53_device *dev = ds->priv;
1381
1382 if (switchdev_trans_ph_prepare(trans))
1383 return 0;
1384
1385 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1386
1387 return 0;
1388}
1389EXPORT_SYMBOL(b53_vlan_filtering);
1390
1391int b53_vlan_prepare(struct dsa_switch *ds, int port,
1392 const struct switchdev_obj_port_vlan *vlan)
1393{
1394 struct b53_device *dev = ds->priv;
1395
1396 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1397 return -EOPNOTSUPP;
1398
1399
1400
1401
1402
1403 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1404 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1405 return -EINVAL;
1406
1407 if (vlan->vid_end > dev->num_vlans)
1408 return -ERANGE;
1409
1410 b53_enable_vlan(dev, true, ds->vlan_filtering);
1411
1412 return 0;
1413}
1414EXPORT_SYMBOL(b53_vlan_prepare);
1415
1416void b53_vlan_add(struct dsa_switch *ds, int port,
1417 const struct switchdev_obj_port_vlan *vlan)
1418{
1419 struct b53_device *dev = ds->priv;
1420 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1421 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1422 struct b53_vlan *vl;
1423 u16 vid;
1424
1425 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1426 vl = &dev->vlans[vid];
1427
1428 b53_get_vlan_entry(dev, vid, vl);
1429
1430 if (vid == 0 && vid == b53_default_pvid(dev))
1431 untagged = true;
1432
1433 vl->members |= BIT(port);
1434 if (untagged && !dsa_is_cpu_port(ds, port))
1435 vl->untag |= BIT(port);
1436 else
1437 vl->untag &= ~BIT(port);
1438
1439 b53_set_vlan_entry(dev, vid, vl);
1440 b53_fast_age_vlan(dev, vid);
1441 }
1442
1443 if (pvid && !dsa_is_cpu_port(ds, port)) {
1444 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1445 vlan->vid_end);
1446 b53_fast_age_vlan(dev, vid);
1447 }
1448}
1449EXPORT_SYMBOL(b53_vlan_add);
1450
1451int b53_vlan_del(struct dsa_switch *ds, int port,
1452 const struct switchdev_obj_port_vlan *vlan)
1453{
1454 struct b53_device *dev = ds->priv;
1455 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1456 struct b53_vlan *vl;
1457 u16 vid;
1458 u16 pvid;
1459
1460 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1461
1462 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1463 vl = &dev->vlans[vid];
1464
1465 b53_get_vlan_entry(dev, vid, vl);
1466
1467 vl->members &= ~BIT(port);
1468
1469 if (pvid == vid)
1470 pvid = b53_default_pvid(dev);
1471
1472 if (untagged && !dsa_is_cpu_port(ds, port))
1473 vl->untag &= ~(BIT(port));
1474
1475 b53_set_vlan_entry(dev, vid, vl);
1476 b53_fast_age_vlan(dev, vid);
1477 }
1478
1479 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1480 b53_fast_age_vlan(dev, pvid);
1481
1482 return 0;
1483}
1484EXPORT_SYMBOL(b53_vlan_del);
1485
1486
1487static int b53_arl_op_wait(struct b53_device *dev)
1488{
1489 unsigned int timeout = 10;
1490 u8 reg;
1491
1492 do {
1493 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1494 if (!(reg & ARLTBL_START_DONE))
1495 return 0;
1496
1497 usleep_range(1000, 2000);
1498 } while (timeout--);
1499
1500 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1501
1502 return -ETIMEDOUT;
1503}
1504
1505static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1506{
1507 u8 reg;
1508
1509 if (op > ARLTBL_RW)
1510 return -EINVAL;
1511
1512 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1513 reg |= ARLTBL_START_DONE;
1514 if (op)
1515 reg |= ARLTBL_RW;
1516 else
1517 reg &= ~ARLTBL_RW;
1518 if (dev->vlan_enabled)
1519 reg &= ~ARLTBL_IVL_SVL_SELECT;
1520 else
1521 reg |= ARLTBL_IVL_SVL_SELECT;
1522 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1523
1524 return b53_arl_op_wait(dev);
1525}
1526
1527static int b53_arl_read(struct b53_device *dev, u64 mac,
1528 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1529{
1530 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1531 unsigned int i;
1532 int ret;
1533
1534 ret = b53_arl_op_wait(dev);
1535 if (ret)
1536 return ret;
1537
1538 bitmap_zero(free_bins, dev->num_arl_bins);
1539
1540
1541 for (i = 0; i < dev->num_arl_bins; i++) {
1542 u64 mac_vid;
1543 u32 fwd_entry;
1544
1545 b53_read64(dev, B53_ARLIO_PAGE,
1546 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1547 b53_read32(dev, B53_ARLIO_PAGE,
1548 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1549 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1550
1551 if (!(fwd_entry & ARLTBL_VALID)) {
1552 set_bit(i, free_bins);
1553 continue;
1554 }
1555 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1556 continue;
1557 if (dev->vlan_enabled &&
1558 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1559 continue;
1560 *idx = i;
1561 return 0;
1562 }
1563
1564 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0)
1565 return -ENOSPC;
1566
1567 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1568
1569 return -ENOENT;
1570}
1571
1572static int b53_arl_op(struct b53_device *dev, int op, int port,
1573 const unsigned char *addr, u16 vid, bool is_valid)
1574{
1575 struct b53_arl_entry ent;
1576 u32 fwd_entry;
1577 u64 mac, mac_vid = 0;
1578 u8 idx = 0;
1579 int ret;
1580
1581
1582 mac = ether_addr_to_u64(addr);
1583
1584
1585 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1586 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1587
1588
1589 ret = b53_arl_rw_op(dev, 1);
1590 if (ret)
1591 return ret;
1592
1593 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1594
1595
1596 if (op)
1597 return ret;
1598
1599 switch (ret) {
1600 case -ETIMEDOUT:
1601 return ret;
1602 case -ENOSPC:
1603 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1604 addr, vid);
1605 return is_valid ? ret : 0;
1606 case -ENOENT:
1607
1608 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1609 addr, vid, idx);
1610 fwd_entry = 0;
1611 break;
1612 default:
1613 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1614 addr, vid, idx);
1615 break;
1616 }
1617
1618
1619
1620
1621 if (!is_multicast_ether_addr(addr)) {
1622 ent.port = port;
1623 ent.is_valid = is_valid;
1624 } else {
1625 if (is_valid)
1626 ent.port |= BIT(port);
1627 else
1628 ent.port &= ~BIT(port);
1629
1630 ent.is_valid = !!(ent.port);
1631 }
1632
1633 ent.vid = vid;
1634 ent.is_static = true;
1635 ent.is_age = false;
1636 memcpy(ent.mac, addr, ETH_ALEN);
1637 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1638
1639 b53_write64(dev, B53_ARLIO_PAGE,
1640 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1641 b53_write32(dev, B53_ARLIO_PAGE,
1642 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1643
1644 return b53_arl_rw_op(dev, 0);
1645}
1646
1647int b53_fdb_add(struct dsa_switch *ds, int port,
1648 const unsigned char *addr, u16 vid)
1649{
1650 struct b53_device *priv = ds->priv;
1651
1652
1653
1654
1655 if (is5325(priv) || is5365(priv))
1656 return -EOPNOTSUPP;
1657
1658 return b53_arl_op(priv, 0, port, addr, vid, true);
1659}
1660EXPORT_SYMBOL(b53_fdb_add);
1661
1662int b53_fdb_del(struct dsa_switch *ds, int port,
1663 const unsigned char *addr, u16 vid)
1664{
1665 struct b53_device *priv = ds->priv;
1666
1667 return b53_arl_op(priv, 0, port, addr, vid, false);
1668}
1669EXPORT_SYMBOL(b53_fdb_del);
1670
1671static int b53_arl_search_wait(struct b53_device *dev)
1672{
1673 unsigned int timeout = 1000;
1674 u8 reg;
1675
1676 do {
1677 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1678 if (!(reg & ARL_SRCH_STDN))
1679 return 0;
1680
1681 if (reg & ARL_SRCH_VLID)
1682 return 0;
1683
1684 usleep_range(1000, 2000);
1685 } while (timeout--);
1686
1687 return -ETIMEDOUT;
1688}
1689
1690static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1691 struct b53_arl_entry *ent)
1692{
1693 u64 mac_vid;
1694 u32 fwd_entry;
1695
1696 b53_read64(dev, B53_ARLIO_PAGE,
1697 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1698 b53_read32(dev, B53_ARLIO_PAGE,
1699 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1700 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1701}
1702
1703static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1704 dsa_fdb_dump_cb_t *cb, void *data)
1705{
1706 if (!ent->is_valid)
1707 return 0;
1708
1709 if (port != ent->port)
1710 return 0;
1711
1712 return cb(ent->mac, ent->vid, ent->is_static, data);
1713}
1714
1715int b53_fdb_dump(struct dsa_switch *ds, int port,
1716 dsa_fdb_dump_cb_t *cb, void *data)
1717{
1718 struct b53_device *priv = ds->priv;
1719 struct b53_arl_entry results[2];
1720 unsigned int count = 0;
1721 int ret;
1722 u8 reg;
1723
1724
1725 reg = ARL_SRCH_STDN;
1726 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1727
1728 do {
1729 ret = b53_arl_search_wait(priv);
1730 if (ret)
1731 return ret;
1732
1733 b53_arl_search_rd(priv, 0, &results[0]);
1734 ret = b53_fdb_copy(port, &results[0], cb, data);
1735 if (ret)
1736 return ret;
1737
1738 if (priv->num_arl_bins > 2) {
1739 b53_arl_search_rd(priv, 1, &results[1]);
1740 ret = b53_fdb_copy(port, &results[1], cb, data);
1741 if (ret)
1742 return ret;
1743
1744 if (!results[0].is_valid && !results[1].is_valid)
1745 break;
1746 }
1747
1748 } while (count++ < b53_max_arl_entries(priv) / 2);
1749
1750 return 0;
1751}
1752EXPORT_SYMBOL(b53_fdb_dump);
1753
1754int b53_mdb_prepare(struct dsa_switch *ds, int port,
1755 const struct switchdev_obj_port_mdb *mdb)
1756{
1757 struct b53_device *priv = ds->priv;
1758
1759
1760
1761
1762 if (is5325(priv) || is5365(priv))
1763 return -EOPNOTSUPP;
1764
1765 return 0;
1766}
1767EXPORT_SYMBOL(b53_mdb_prepare);
1768
1769void b53_mdb_add(struct dsa_switch *ds, int port,
1770 const struct switchdev_obj_port_mdb *mdb)
1771{
1772 struct b53_device *priv = ds->priv;
1773 int ret;
1774
1775 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1776 if (ret)
1777 dev_err(ds->dev, "failed to add MDB entry\n");
1778}
1779EXPORT_SYMBOL(b53_mdb_add);
1780
1781int b53_mdb_del(struct dsa_switch *ds, int port,
1782 const struct switchdev_obj_port_mdb *mdb)
1783{
1784 struct b53_device *priv = ds->priv;
1785 int ret;
1786
1787 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1788 if (ret)
1789 dev_err(ds->dev, "failed to delete MDB entry\n");
1790
1791 return ret;
1792}
1793EXPORT_SYMBOL(b53_mdb_del);
1794
1795int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1796{
1797 struct b53_device *dev = ds->priv;
1798 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1799 u16 pvlan, reg;
1800 unsigned int i;
1801
1802
1803
1804
1805 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1806 return -EINVAL;
1807
1808
1809
1810
1811 if (is58xx(dev)) {
1812 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1813 reg &= ~BIT(port);
1814 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1815 reg &= ~BIT(cpu_port);
1816 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1817 }
1818
1819 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1820
1821 b53_for_each_port(dev, i) {
1822 if (dsa_to_port(ds, i)->bridge_dev != br)
1823 continue;
1824
1825
1826
1827
1828 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1829 reg |= BIT(port);
1830 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1831 dev->ports[i].vlan_ctl_mask = reg;
1832
1833 pvlan |= BIT(i);
1834 }
1835
1836
1837
1838
1839 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1840 dev->ports[port].vlan_ctl_mask = pvlan;
1841
1842 return 0;
1843}
1844EXPORT_SYMBOL(b53_br_join);
1845
1846void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1847{
1848 struct b53_device *dev = ds->priv;
1849 struct b53_vlan *vl = &dev->vlans[0];
1850 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1851 unsigned int i;
1852 u16 pvlan, reg, pvid;
1853
1854 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1855
1856 b53_for_each_port(dev, i) {
1857
1858 if (dsa_to_port(ds, i)->bridge_dev != br)
1859 continue;
1860
1861 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1862 reg &= ~BIT(port);
1863 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1864 dev->ports[port].vlan_ctl_mask = reg;
1865
1866
1867 if (port != i)
1868 pvlan &= ~BIT(i);
1869 }
1870
1871 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1872 dev->ports[port].vlan_ctl_mask = pvlan;
1873
1874 pvid = b53_default_pvid(dev);
1875
1876
1877 if (is58xx(dev)) {
1878 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1879 reg |= BIT(port);
1880 if (!(reg & BIT(cpu_port)))
1881 reg |= BIT(cpu_port);
1882 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1883 } else {
1884 b53_get_vlan_entry(dev, pvid, vl);
1885 vl->members |= BIT(port) | BIT(cpu_port);
1886 vl->untag |= BIT(port) | BIT(cpu_port);
1887 b53_set_vlan_entry(dev, pvid, vl);
1888 }
1889}
1890EXPORT_SYMBOL(b53_br_leave);
1891
1892void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1893{
1894 struct b53_device *dev = ds->priv;
1895 u8 hw_state;
1896 u8 reg;
1897
1898 switch (state) {
1899 case BR_STATE_DISABLED:
1900 hw_state = PORT_CTRL_DIS_STATE;
1901 break;
1902 case BR_STATE_LISTENING:
1903 hw_state = PORT_CTRL_LISTEN_STATE;
1904 break;
1905 case BR_STATE_LEARNING:
1906 hw_state = PORT_CTRL_LEARN_STATE;
1907 break;
1908 case BR_STATE_FORWARDING:
1909 hw_state = PORT_CTRL_FWD_STATE;
1910 break;
1911 case BR_STATE_BLOCKING:
1912 hw_state = PORT_CTRL_BLOCK_STATE;
1913 break;
1914 default:
1915 dev_err(ds->dev, "invalid STP state: %d\n", state);
1916 return;
1917 }
1918
1919 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1920 reg &= ~PORT_CTRL_STP_STATE_MASK;
1921 reg |= hw_state;
1922 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1923}
1924EXPORT_SYMBOL(b53_br_set_stp_state);
1925
1926void b53_br_fast_age(struct dsa_switch *ds, int port)
1927{
1928 struct b53_device *dev = ds->priv;
1929
1930 if (b53_fast_age_port(dev, port))
1931 dev_err(ds->dev, "fast ageing failed\n");
1932}
1933EXPORT_SYMBOL(b53_br_fast_age);
1934
1935int b53_br_egress_floods(struct dsa_switch *ds, int port,
1936 bool unicast, bool multicast)
1937{
1938 struct b53_device *dev = ds->priv;
1939 u16 uc, mc;
1940
1941 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
1942 if (unicast)
1943 uc |= BIT(port);
1944 else
1945 uc &= ~BIT(port);
1946 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
1947
1948 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
1949 if (multicast)
1950 mc |= BIT(port);
1951 else
1952 mc &= ~BIT(port);
1953 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
1954
1955 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
1956 if (multicast)
1957 mc |= BIT(port);
1958 else
1959 mc &= ~BIT(port);
1960 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
1961
1962 return 0;
1963
1964}
1965EXPORT_SYMBOL(b53_br_egress_floods);
1966
1967static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
1968{
1969
1970
1971
1972 switch (port) {
1973 case B53_CPU_PORT_25:
1974 case 7:
1975 case B53_CPU_PORT:
1976 return true;
1977 }
1978
1979 return false;
1980}
1981
1982static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
1983 enum dsa_tag_protocol tag_protocol)
1984{
1985 bool ret = b53_possible_cpu_port(ds, port);
1986
1987 if (!ret) {
1988 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1989 port);
1990 return ret;
1991 }
1992
1993 switch (tag_protocol) {
1994 case DSA_TAG_PROTO_BRCM:
1995 case DSA_TAG_PROTO_BRCM_PREPEND:
1996 dev_warn(ds->dev,
1997 "Port %d is stacked to Broadcom tag switch\n", port);
1998 ret = false;
1999 break;
2000 default:
2001 ret = true;
2002 break;
2003 }
2004
2005 return ret;
2006}
2007
2008enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2009 enum dsa_tag_protocol mprot)
2010{
2011 struct b53_device *dev = ds->priv;
2012
2013
2014
2015
2016 if (is5325(dev) || is5365(dev) ||
2017 !b53_can_enable_brcm_tags(ds, port, mprot)) {
2018 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2019 goto out;
2020 }
2021
2022
2023
2024
2025 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2026 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2027 goto out;
2028 }
2029
2030 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2031out:
2032 return dev->tag_protocol;
2033}
2034EXPORT_SYMBOL(b53_get_tag_protocol);
2035
2036int b53_mirror_add(struct dsa_switch *ds, int port,
2037 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
2038{
2039 struct b53_device *dev = ds->priv;
2040 u16 reg, loc;
2041
2042 if (ingress)
2043 loc = B53_IG_MIR_CTL;
2044 else
2045 loc = B53_EG_MIR_CTL;
2046
2047 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2048 reg |= BIT(port);
2049 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2050
2051 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2052 reg &= ~CAP_PORT_MASK;
2053 reg |= mirror->to_local_port;
2054 reg |= MIRROR_EN;
2055 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2056
2057 return 0;
2058}
2059EXPORT_SYMBOL(b53_mirror_add);
2060
2061void b53_mirror_del(struct dsa_switch *ds, int port,
2062 struct dsa_mall_mirror_tc_entry *mirror)
2063{
2064 struct b53_device *dev = ds->priv;
2065 bool loc_disable = false, other_loc_disable = false;
2066 u16 reg, loc;
2067
2068 if (mirror->ingress)
2069 loc = B53_IG_MIR_CTL;
2070 else
2071 loc = B53_EG_MIR_CTL;
2072
2073
2074 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2075 reg &= ~BIT(port);
2076 if (!(reg & MIRROR_MASK))
2077 loc_disable = true;
2078 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2079
2080
2081
2082
2083 if (mirror->ingress)
2084 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2085 else
2086 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2087 if (!(reg & MIRROR_MASK))
2088 other_loc_disable = true;
2089
2090 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2091
2092 if (loc_disable && other_loc_disable) {
2093 reg &= ~MIRROR_EN;
2094 reg &= ~mirror->to_local_port;
2095 }
2096 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2097}
2098EXPORT_SYMBOL(b53_mirror_del);
2099
2100void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2101{
2102 struct b53_device *dev = ds->priv;
2103 u16 reg;
2104
2105 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
2106 if (enable)
2107 reg |= BIT(port);
2108 else
2109 reg &= ~BIT(port);
2110 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2111}
2112EXPORT_SYMBOL(b53_eee_enable_set);
2113
2114
2115
2116
2117int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2118{
2119 int ret;
2120
2121 ret = phy_init_eee(phy, 0);
2122 if (ret)
2123 return 0;
2124
2125 b53_eee_enable_set(ds, port, true);
2126
2127 return 1;
2128}
2129EXPORT_SYMBOL(b53_eee_init);
2130
2131int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2132{
2133 struct b53_device *dev = ds->priv;
2134 struct ethtool_eee *p = &dev->ports[port].eee;
2135 u16 reg;
2136
2137 if (is5325(dev) || is5365(dev))
2138 return -EOPNOTSUPP;
2139
2140 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®);
2141 e->eee_enabled = p->eee_enabled;
2142 e->eee_active = !!(reg & BIT(port));
2143
2144 return 0;
2145}
2146EXPORT_SYMBOL(b53_get_mac_eee);
2147
2148int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2149{
2150 struct b53_device *dev = ds->priv;
2151 struct ethtool_eee *p = &dev->ports[port].eee;
2152
2153 if (is5325(dev) || is5365(dev))
2154 return -EOPNOTSUPP;
2155
2156 p->eee_enabled = e->eee_enabled;
2157 b53_eee_enable_set(ds, port, e->eee_enabled);
2158
2159 return 0;
2160}
2161EXPORT_SYMBOL(b53_set_mac_eee);
2162
2163static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2164{
2165 struct b53_device *dev = ds->priv;
2166 bool enable_jumbo;
2167 bool allow_10_100;
2168
2169 if (is5325(dev) || is5365(dev))
2170 return -EOPNOTSUPP;
2171
2172 enable_jumbo = (mtu >= JMS_MIN_SIZE);
2173 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2174
2175 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2176}
2177
2178static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2179{
2180 return JMS_MAX_SIZE;
2181}
2182
2183static const struct dsa_switch_ops b53_switch_ops = {
2184 .get_tag_protocol = b53_get_tag_protocol,
2185 .setup = b53_setup,
2186 .teardown = b53_teardown,
2187 .get_strings = b53_get_strings,
2188 .get_ethtool_stats = b53_get_ethtool_stats,
2189 .get_sset_count = b53_get_sset_count,
2190 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2191 .phy_read = b53_phy_read16,
2192 .phy_write = b53_phy_write16,
2193 .adjust_link = b53_adjust_link,
2194 .phylink_validate = b53_phylink_validate,
2195 .phylink_mac_link_state = b53_phylink_mac_link_state,
2196 .phylink_mac_config = b53_phylink_mac_config,
2197 .phylink_mac_an_restart = b53_phylink_mac_an_restart,
2198 .phylink_mac_link_down = b53_phylink_mac_link_down,
2199 .phylink_mac_link_up = b53_phylink_mac_link_up,
2200 .port_enable = b53_enable_port,
2201 .port_disable = b53_disable_port,
2202 .get_mac_eee = b53_get_mac_eee,
2203 .set_mac_eee = b53_set_mac_eee,
2204 .port_bridge_join = b53_br_join,
2205 .port_bridge_leave = b53_br_leave,
2206 .port_stp_state_set = b53_br_set_stp_state,
2207 .port_fast_age = b53_br_fast_age,
2208 .port_egress_floods = b53_br_egress_floods,
2209 .port_vlan_filtering = b53_vlan_filtering,
2210 .port_vlan_prepare = b53_vlan_prepare,
2211 .port_vlan_add = b53_vlan_add,
2212 .port_vlan_del = b53_vlan_del,
2213 .port_fdb_dump = b53_fdb_dump,
2214 .port_fdb_add = b53_fdb_add,
2215 .port_fdb_del = b53_fdb_del,
2216 .port_mirror_add = b53_mirror_add,
2217 .port_mirror_del = b53_mirror_del,
2218 .port_mdb_prepare = b53_mdb_prepare,
2219 .port_mdb_add = b53_mdb_add,
2220 .port_mdb_del = b53_mdb_del,
2221 .port_max_mtu = b53_get_max_mtu,
2222 .port_change_mtu = b53_change_mtu,
2223};
2224
2225struct b53_chip_data {
2226 u32 chip_id;
2227 const char *dev_name;
2228 u16 vlans;
2229 u16 enabled_ports;
2230 u8 cpu_port;
2231 u8 vta_regs[3];
2232 u8 arl_bins;
2233 u16 arl_buckets;
2234 u8 duplex_reg;
2235 u8 jumbo_pm_reg;
2236 u8 jumbo_size_reg;
2237};
2238
2239#define B53_VTA_REGS \
2240 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2241#define B53_VTA_REGS_9798 \
2242 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2243#define B53_VTA_REGS_63XX \
2244 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2245
2246static const struct b53_chip_data b53_switch_chips[] = {
2247 {
2248 .chip_id = BCM5325_DEVICE_ID,
2249 .dev_name = "BCM5325",
2250 .vlans = 16,
2251 .enabled_ports = 0x1f,
2252 .arl_bins = 2,
2253 .arl_buckets = 1024,
2254 .cpu_port = B53_CPU_PORT_25,
2255 .duplex_reg = B53_DUPLEX_STAT_FE,
2256 },
2257 {
2258 .chip_id = BCM5365_DEVICE_ID,
2259 .dev_name = "BCM5365",
2260 .vlans = 256,
2261 .enabled_ports = 0x1f,
2262 .arl_bins = 2,
2263 .arl_buckets = 1024,
2264 .cpu_port = B53_CPU_PORT_25,
2265 .duplex_reg = B53_DUPLEX_STAT_FE,
2266 },
2267 {
2268 .chip_id = BCM5389_DEVICE_ID,
2269 .dev_name = "BCM5389",
2270 .vlans = 4096,
2271 .enabled_ports = 0x1f,
2272 .arl_bins = 4,
2273 .arl_buckets = 1024,
2274 .cpu_port = B53_CPU_PORT,
2275 .vta_regs = B53_VTA_REGS,
2276 .duplex_reg = B53_DUPLEX_STAT_GE,
2277 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2278 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2279 },
2280 {
2281 .chip_id = BCM5395_DEVICE_ID,
2282 .dev_name = "BCM5395",
2283 .vlans = 4096,
2284 .enabled_ports = 0x1f,
2285 .arl_bins = 4,
2286 .arl_buckets = 1024,
2287 .cpu_port = B53_CPU_PORT,
2288 .vta_regs = B53_VTA_REGS,
2289 .duplex_reg = B53_DUPLEX_STAT_GE,
2290 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2291 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2292 },
2293 {
2294 .chip_id = BCM5397_DEVICE_ID,
2295 .dev_name = "BCM5397",
2296 .vlans = 4096,
2297 .enabled_ports = 0x1f,
2298 .arl_bins = 4,
2299 .arl_buckets = 1024,
2300 .cpu_port = B53_CPU_PORT,
2301 .vta_regs = B53_VTA_REGS_9798,
2302 .duplex_reg = B53_DUPLEX_STAT_GE,
2303 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2304 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2305 },
2306 {
2307 .chip_id = BCM5398_DEVICE_ID,
2308 .dev_name = "BCM5398",
2309 .vlans = 4096,
2310 .enabled_ports = 0x7f,
2311 .arl_bins = 4,
2312 .arl_buckets = 1024,
2313 .cpu_port = B53_CPU_PORT,
2314 .vta_regs = B53_VTA_REGS_9798,
2315 .duplex_reg = B53_DUPLEX_STAT_GE,
2316 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2317 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2318 },
2319 {
2320 .chip_id = BCM53115_DEVICE_ID,
2321 .dev_name = "BCM53115",
2322 .vlans = 4096,
2323 .enabled_ports = 0x1f,
2324 .arl_bins = 4,
2325 .arl_buckets = 1024,
2326 .vta_regs = B53_VTA_REGS,
2327 .cpu_port = B53_CPU_PORT,
2328 .duplex_reg = B53_DUPLEX_STAT_GE,
2329 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2330 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2331 },
2332 {
2333 .chip_id = BCM53125_DEVICE_ID,
2334 .dev_name = "BCM53125",
2335 .vlans = 4096,
2336 .enabled_ports = 0xff,
2337 .arl_bins = 4,
2338 .arl_buckets = 1024,
2339 .cpu_port = B53_CPU_PORT,
2340 .vta_regs = B53_VTA_REGS,
2341 .duplex_reg = B53_DUPLEX_STAT_GE,
2342 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2343 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2344 },
2345 {
2346 .chip_id = BCM53128_DEVICE_ID,
2347 .dev_name = "BCM53128",
2348 .vlans = 4096,
2349 .enabled_ports = 0x1ff,
2350 .arl_bins = 4,
2351 .arl_buckets = 1024,
2352 .cpu_port = B53_CPU_PORT,
2353 .vta_regs = B53_VTA_REGS,
2354 .duplex_reg = B53_DUPLEX_STAT_GE,
2355 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2356 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2357 },
2358 {
2359 .chip_id = BCM63XX_DEVICE_ID,
2360 .dev_name = "BCM63xx",
2361 .vlans = 4096,
2362 .enabled_ports = 0,
2363 .arl_bins = 4,
2364 .arl_buckets = 1024,
2365 .cpu_port = B53_CPU_PORT,
2366 .vta_regs = B53_VTA_REGS_63XX,
2367 .duplex_reg = B53_DUPLEX_STAT_63XX,
2368 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2369 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2370 },
2371 {
2372 .chip_id = BCM53010_DEVICE_ID,
2373 .dev_name = "BCM53010",
2374 .vlans = 4096,
2375 .enabled_ports = 0x1f,
2376 .arl_bins = 4,
2377 .arl_buckets = 1024,
2378 .cpu_port = B53_CPU_PORT_25,
2379 .vta_regs = B53_VTA_REGS,
2380 .duplex_reg = B53_DUPLEX_STAT_GE,
2381 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2382 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2383 },
2384 {
2385 .chip_id = BCM53011_DEVICE_ID,
2386 .dev_name = "BCM53011",
2387 .vlans = 4096,
2388 .enabled_ports = 0x1bf,
2389 .arl_bins = 4,
2390 .arl_buckets = 1024,
2391 .cpu_port = B53_CPU_PORT_25,
2392 .vta_regs = B53_VTA_REGS,
2393 .duplex_reg = B53_DUPLEX_STAT_GE,
2394 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2395 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2396 },
2397 {
2398 .chip_id = BCM53012_DEVICE_ID,
2399 .dev_name = "BCM53012",
2400 .vlans = 4096,
2401 .enabled_ports = 0x1bf,
2402 .arl_bins = 4,
2403 .arl_buckets = 1024,
2404 .cpu_port = B53_CPU_PORT_25,
2405 .vta_regs = B53_VTA_REGS,
2406 .duplex_reg = B53_DUPLEX_STAT_GE,
2407 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2408 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2409 },
2410 {
2411 .chip_id = BCM53018_DEVICE_ID,
2412 .dev_name = "BCM53018",
2413 .vlans = 4096,
2414 .enabled_ports = 0x1f,
2415 .arl_bins = 4,
2416 .arl_buckets = 1024,
2417 .cpu_port = B53_CPU_PORT_25,
2418 .vta_regs = B53_VTA_REGS,
2419 .duplex_reg = B53_DUPLEX_STAT_GE,
2420 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2421 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2422 },
2423 {
2424 .chip_id = BCM53019_DEVICE_ID,
2425 .dev_name = "BCM53019",
2426 .vlans = 4096,
2427 .enabled_ports = 0x1f,
2428 .arl_bins = 4,
2429 .arl_buckets = 1024,
2430 .cpu_port = B53_CPU_PORT_25,
2431 .vta_regs = B53_VTA_REGS,
2432 .duplex_reg = B53_DUPLEX_STAT_GE,
2433 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2434 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2435 },
2436 {
2437 .chip_id = BCM58XX_DEVICE_ID,
2438 .dev_name = "BCM585xx/586xx/88312",
2439 .vlans = 4096,
2440 .enabled_ports = 0x1ff,
2441 .arl_bins = 4,
2442 .arl_buckets = 1024,
2443 .cpu_port = B53_CPU_PORT,
2444 .vta_regs = B53_VTA_REGS,
2445 .duplex_reg = B53_DUPLEX_STAT_GE,
2446 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2447 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2448 },
2449 {
2450 .chip_id = BCM583XX_DEVICE_ID,
2451 .dev_name = "BCM583xx/11360",
2452 .vlans = 4096,
2453 .enabled_ports = 0x103,
2454 .arl_bins = 4,
2455 .arl_buckets = 1024,
2456 .cpu_port = B53_CPU_PORT,
2457 .vta_regs = B53_VTA_REGS,
2458 .duplex_reg = B53_DUPLEX_STAT_GE,
2459 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2460 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2461 },
2462 {
2463 .chip_id = BCM7445_DEVICE_ID,
2464 .dev_name = "BCM7445",
2465 .vlans = 4096,
2466 .enabled_ports = 0x1ff,
2467 .arl_bins = 4,
2468 .arl_buckets = 1024,
2469 .cpu_port = B53_CPU_PORT,
2470 .vta_regs = B53_VTA_REGS,
2471 .duplex_reg = B53_DUPLEX_STAT_GE,
2472 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2473 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2474 },
2475 {
2476 .chip_id = BCM7278_DEVICE_ID,
2477 .dev_name = "BCM7278",
2478 .vlans = 4096,
2479 .enabled_ports = 0x1ff,
2480 .arl_bins = 4,
2481 .arl_buckets = 256,
2482 .cpu_port = B53_CPU_PORT,
2483 .vta_regs = B53_VTA_REGS,
2484 .duplex_reg = B53_DUPLEX_STAT_GE,
2485 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2486 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2487 },
2488};
2489
2490static int b53_switch_init(struct b53_device *dev)
2491{
2492 unsigned int i;
2493 int ret;
2494
2495 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2496 const struct b53_chip_data *chip = &b53_switch_chips[i];
2497
2498 if (chip->chip_id == dev->chip_id) {
2499 if (!dev->enabled_ports)
2500 dev->enabled_ports = chip->enabled_ports;
2501 dev->name = chip->dev_name;
2502 dev->duplex_reg = chip->duplex_reg;
2503 dev->vta_regs[0] = chip->vta_regs[0];
2504 dev->vta_regs[1] = chip->vta_regs[1];
2505 dev->vta_regs[2] = chip->vta_regs[2];
2506 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2507 dev->cpu_port = chip->cpu_port;
2508 dev->num_vlans = chip->vlans;
2509 dev->num_arl_bins = chip->arl_bins;
2510 dev->num_arl_buckets = chip->arl_buckets;
2511 break;
2512 }
2513 }
2514
2515
2516 if (is5325(dev)) {
2517 u8 vc4;
2518
2519 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2520
2521
2522 switch (vc4 & 3) {
2523 case 1:
2524
2525 break;
2526 case 3:
2527
2528 dev->enabled_ports &= ~BIT(4);
2529 break;
2530 default:
2531
2532#ifndef CONFIG_BCM47XX
2533
2534 return -EINVAL;
2535#else
2536 break;
2537#endif
2538 }
2539 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2540 u64 strap_value;
2541
2542 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2543
2544 if (strap_value & SV_GMII_CTRL_115)
2545 dev->cpu_port = 5;
2546 }
2547
2548
2549 dev->num_ports = dev->cpu_port + 1;
2550 dev->enabled_ports |= BIT(dev->cpu_port);
2551
2552
2553 if (is539x(dev) || is531x5(dev)) {
2554 for (i = 0; i < dev->num_ports; i++) {
2555 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2556 !b53_possible_cpu_port(dev->ds, i))
2557 dev->ds->phys_mii_mask |= BIT(i);
2558 }
2559 }
2560
2561 dev->ports = devm_kcalloc(dev->dev,
2562 dev->num_ports, sizeof(struct b53_port),
2563 GFP_KERNEL);
2564 if (!dev->ports)
2565 return -ENOMEM;
2566
2567 dev->vlans = devm_kcalloc(dev->dev,
2568 dev->num_vlans, sizeof(struct b53_vlan),
2569 GFP_KERNEL);
2570 if (!dev->vlans)
2571 return -ENOMEM;
2572
2573 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2574 if (dev->reset_gpio >= 0) {
2575 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2576 GPIOF_OUT_INIT_HIGH, "robo_reset");
2577 if (ret)
2578 return ret;
2579 }
2580
2581 return 0;
2582}
2583
2584struct b53_device *b53_switch_alloc(struct device *base,
2585 const struct b53_io_ops *ops,
2586 void *priv)
2587{
2588 struct dsa_switch *ds;
2589 struct b53_device *dev;
2590
2591 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2592 if (!ds)
2593 return NULL;
2594
2595 ds->dev = base;
2596 ds->num_ports = DSA_MAX_PORTS;
2597
2598 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2599 if (!dev)
2600 return NULL;
2601
2602 ds->priv = dev;
2603 dev->dev = base;
2604
2605 dev->ds = ds;
2606 dev->priv = priv;
2607 dev->ops = ops;
2608 ds->ops = &b53_switch_ops;
2609 ds->configure_vlan_while_not_filtering = true;
2610 ds->untag_bridge_pvid = true;
2611 dev->vlan_enabled = ds->configure_vlan_while_not_filtering;
2612 mutex_init(&dev->reg_mutex);
2613 mutex_init(&dev->stats_mutex);
2614
2615 return dev;
2616}
2617EXPORT_SYMBOL(b53_switch_alloc);
2618
2619int b53_switch_detect(struct b53_device *dev)
2620{
2621 u32 id32;
2622 u16 tmp;
2623 u8 id8;
2624 int ret;
2625
2626 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2627 if (ret)
2628 return ret;
2629
2630 switch (id8) {
2631 case 0:
2632
2633
2634
2635
2636
2637
2638
2639 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2640 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2641
2642 if (tmp == 0xf)
2643 dev->chip_id = BCM5325_DEVICE_ID;
2644 else
2645 dev->chip_id = BCM5365_DEVICE_ID;
2646 break;
2647 case BCM5389_DEVICE_ID:
2648 case BCM5395_DEVICE_ID:
2649 case BCM5397_DEVICE_ID:
2650 case BCM5398_DEVICE_ID:
2651 dev->chip_id = id8;
2652 break;
2653 default:
2654 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2655 if (ret)
2656 return ret;
2657
2658 switch (id32) {
2659 case BCM53115_DEVICE_ID:
2660 case BCM53125_DEVICE_ID:
2661 case BCM53128_DEVICE_ID:
2662 case BCM53010_DEVICE_ID:
2663 case BCM53011_DEVICE_ID:
2664 case BCM53012_DEVICE_ID:
2665 case BCM53018_DEVICE_ID:
2666 case BCM53019_DEVICE_ID:
2667 dev->chip_id = id32;
2668 break;
2669 default:
2670 dev_err(dev->dev,
2671 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2672 id8, id32);
2673 return -ENODEV;
2674 }
2675 }
2676
2677 if (dev->chip_id == BCM5325_DEVICE_ID)
2678 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2679 &dev->core_rev);
2680 else
2681 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2682 &dev->core_rev);
2683}
2684EXPORT_SYMBOL(b53_switch_detect);
2685
2686int b53_switch_register(struct b53_device *dev)
2687{
2688 int ret;
2689
2690 if (dev->pdata) {
2691 dev->chip_id = dev->pdata->chip_id;
2692 dev->enabled_ports = dev->pdata->enabled_ports;
2693 }
2694
2695 if (!dev->chip_id && b53_switch_detect(dev))
2696 return -EINVAL;
2697
2698 ret = b53_switch_init(dev);
2699 if (ret)
2700 return ret;
2701
2702 dev_info(dev->dev, "found switch: %s, rev %i\n",
2703 dev->name, dev->core_rev);
2704
2705 return dsa_register_switch(dev->ds);
2706}
2707EXPORT_SYMBOL(b53_switch_register);
2708
2709MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2710MODULE_DESCRIPTION("B53 switch library");
2711MODULE_LICENSE("Dual BSD/GPL");
2712
