1/* 2 * B53 register definitions 3 * 4 * Copyright (C) 2004 Broadcom Corporation 5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#ifndef __B53_REGS_H 21#define __B53_REGS_H 22 23/* Management Port (SMP) Page offsets */ 24#define B53_CTRL_PAGE 0x00 /* Control */ 25#define B53_STAT_PAGE 0x01 /* Status */ 26#define B53_MGMT_PAGE 0x02 /* Management Mode */ 27#define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */ 28#define B53_ARLCTRL_PAGE 0x04 /* ARL Control */ 29#define B53_ARLIO_PAGE 0x05 /* ARL Access */ 30#define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ 31#define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ 32 33/* PHY Registers */ 34#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ 35#define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ 36#define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ 37 38/* MIB registers */ 39#define B53_MIB_PAGE(i) (0x20 + (i)) 40 41/* Quality of Service (QoS) Registers */ 42#define B53_QOS_PAGE 0x30 43 44/* Port VLAN Page */ 45#define B53_PVLAN_PAGE 0x31 46 47/* VLAN Registers */ 48#define B53_VLAN_PAGE 0x34 49 50/* Jumbo Frame Registers */ 51#define B53_JUMBO_PAGE 0x40 52 53/* EEE Control Registers Page */ 54#define B53_EEE_PAGE 0x92 55 56/* CFP Configuration Registers Page */ 57#define B53_CFP_PAGE 0xa1 58 59/************************************************************************* 60 * Control Page registers 61 *************************************************************************/ 62 63/* Port Control Register (8 bit) */ 64#define B53_PORT_CTRL(i) (0x00 + (i)) 65#define PORT_CTRL_RX_DISABLE BIT(0) 66#define PORT_CTRL_TX_DISABLE BIT(1) 67#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ 68#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ 69#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ 70#define PORT_CTRL_STP_STATE_S 5 71#define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S) 72#define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S) 73#define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S) 74#define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S) 75#define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S) 76#define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S) 77#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) 78 79/* SMP Control Register (8 bit) */ 80#define B53_SMP_CTRL 0x0a 81 82/* Switch Mode Control Register (8 bit) */ 83#define B53_SWITCH_MODE 0x0b 84#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ 85#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ 86 87/* IMP Port state override register (8 bit) */ 88#define B53_PORT_OVERRIDE_CTRL 0x0e 89#define PORT_OVERRIDE_LINK BIT(0) 90#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 91#define PORT_OVERRIDE_SPEED_S 2 92#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) 93#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) 94#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) 95#define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ 96#define PORT_OVERRIDE_RX_FLOW BIT(4) 97#define PORT_OVERRIDE_TX_FLOW BIT(5) 98#define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ 99#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ 100 101/* Power-down mode control */ 102#define B53_PD_MODE_CTRL_25 0x0f 103 104/* IP Multicast control (8 bit) */ 105#define B53_IP_MULTICAST_CTRL 0x21 106#define B53_IPMC_FWD_EN BIT(1) 107#define B53_UC_FWD_EN BIT(6) 108#define B53_MC_FWD_EN BIT(7) 109 110/* Switch control (8 bit) */ 111#define B53_SWITCH_CTRL 0x22 112#define B53_MII_DUMB_FWDG_EN BIT(6) 113 114/* (16 bit) */ 115#define B53_UC_FLOOD_MASK 0x32 116#define B53_MC_FLOOD_MASK 0x34 117#define B53_IPMC_FLOOD_MASK 0x36 118 119/* 120 * Override Ports 0-7 State on devices with xMII interfaces (8 bit) 121 * 122 * For port 8 still use B53_PORT_OVERRIDE_CTRL 123 * Please note that not all ports are available on every hardware, e.g. BCM5301X 124 * don't include overriding port 6, BCM63xx also have some limitations. 125 */ 126#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) 127#define GMII_PO_LINK BIT(0) 128#define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ 129#define GMII_PO_SPEED_S 2 130#define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S) 131#define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S) 132#define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S) 133#define GMII_PO_RX_FLOW BIT(4) 134#define GMII_PO_TX_FLOW BIT(5) 135#define GMII_PO_EN BIT(6) /* Use the register contents */ 136#define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ 137 138#define B53_RGMII_CTRL_IMP 0x60 139#define RGMII_CTRL_ENABLE_GMII BIT(7) 140#define RGMII_CTRL_TIMING_SEL BIT(2) 141#define RGMII_CTRL_DLL_RXC BIT(1) 142#define RGMII_CTRL_DLL_TXC BIT(0) 143 144#define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i)) 145 146/* Software reset register (8 bit) */ 147#define B53_SOFTRESET 0x79 148#define SW_RST BIT(7) 149#define EN_CH_RST BIT(6) 150#define EN_SW_RST BIT(4) 151 152/* Fast Aging Control register (8 bit) */ 153#define B53_FAST_AGE_CTRL 0x88 154#define FAST_AGE_STATIC BIT(0) 155#define FAST_AGE_DYNAMIC BIT(1) 156#define FAST_AGE_PORT BIT(2) 157#define FAST_AGE_VLAN BIT(3) 158#define FAST_AGE_STP BIT(4) 159#define FAST_AGE_MC BIT(5) 160#define FAST_AGE_DONE BIT(7) 161 162/* Fast Aging Port Control register (8 bit) */ 163#define B53_FAST_AGE_PORT_CTRL 0x89 164 165/* Fast Aging VID Control register (16 bit) */ 166#define B53_FAST_AGE_VID_CTRL 0x8a 167 168/************************************************************************* 169 * Status Page registers 170 *************************************************************************/ 171 172/* Link Status Summary Register (16bit) */ 173#define B53_LINK_STAT 0x00 174 175/* Link Status Change Register (16 bit) */ 176#define B53_LINK_STAT_CHANGE 0x02 177 178/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ 179#define B53_SPEED_STAT 0x04 180#define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) 181#define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) 182#define SPEED_STAT_10M 0 183#define SPEED_STAT_100M 1 184#define SPEED_STAT_1000M 2 185 186/* Duplex Status Summary (16 bit) */ 187#define B53_DUPLEX_STAT_FE 0x06 188#define B53_DUPLEX_STAT_GE 0x08 189#define B53_DUPLEX_STAT_63XX 0x0c 190 191/* Revision ID register for BCM5325 */ 192#define B53_REV_ID_25 0x50 193 194/* Strap Value (48 bit) */ 195#define B53_STRAP_VALUE 0x70 196#define SV_GMII_CTRL_115 BIT(27) 197 198/************************************************************************* 199 * Management Mode Page Registers 200 *************************************************************************/ 201 202/* Global Management Config Register (8 bit) */ 203#define B53_GLOBAL_CONFIG 0x00 204#define GC_RESET_MIB 0x01 205#define GC_RX_BPDU_EN 0x02 206#define GC_MIB_AC_HDR_EN 0x10 207#define GC_MIB_AC_EN 0x20 208#define GC_FRM_MGMT_PORT_M 0xC0 209#define GC_FRM_MGMT_PORT_04 0x00 210#define GC_FRM_MGMT_PORT_MII 0x80 211 212/* Broadcom Header control register (8 bit) */ 213#define B53_BRCM_HDR 0x03 214#define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ 215#define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ 216#define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */ 217 218/* Mirror capture control register (16 bit) */ 219#define B53_MIR_CAP_CTL 0x10 220#define CAP_PORT_MASK 0xf 221#define BLK_NOT_MIR BIT(14) 222#define MIRROR_EN BIT(15) 223 224/* Ingress mirror control register (16 bit) */ 225#define B53_IG_MIR_CTL 0x12 226#define MIRROR_MASK 0x1ff 227#define DIV_EN BIT(13) 228#define MIRROR_FILTER_MASK 0x3 229#define MIRROR_FILTER_SHIFT 14 230#define MIRROR_ALL 0 231#define MIRROR_DA 1 232#define MIRROR_SA 2 233 234/* Ingress mirror divider register (16 bit) */ 235#define B53_IG_MIR_DIV 0x14 236#define IN_MIRROR_DIV_MASK 0x3ff 237 238/* Ingress mirror MAC address register (48 bit) */ 239#define B53_IG_MIR_MAC 0x16 240 241/* Egress mirror control register (16 bit) */ 242#define B53_EG_MIR_CTL 0x1C 243 244/* Egress mirror divider register (16 bit) */ 245#define B53_EG_MIR_DIV 0x1E 246 247/* Egress mirror MAC address register (48 bit) */ 248#define B53_EG_MIR_MAC 0x20 249 250/* Device ID register (8 or 32 bit) */ 251#define B53_DEVICE_ID 0x30 252 253/* Revision ID register (8 bit) */ 254#define B53_REV_ID 0x40 255 256/* Broadcom header RX control (16 bit) */ 257#define B53_BRCM_HDR_RX_DIS 0x60 258 259/* Broadcom header TX control (16 bit) */ 260#define B53_BRCM_HDR_TX_DIS 0x62 261 262/************************************************************************* 263 * ARL Access Page Registers 264 *************************************************************************/ 265 266/* VLAN Table Access Register (8 bit) */ 267#define B53_VT_ACCESS 0x80 268#define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */ 269#define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */ 270#define VTA_CMD_WRITE 0 271#define VTA_CMD_READ 1 272#define VTA_CMD_CLEAR 2 273#define VTA_START_CMD BIT(7) 274 275/* VLAN Table Index Register (16 bit) */ 276#define B53_VT_INDEX 0x81 277#define B53_VT_INDEX_9798 0x61 278#define B53_VT_INDEX_63XX 0x62 279 280/* VLAN Table Entry Register (32 bit) */ 281#define B53_VT_ENTRY 0x83 282#define B53_VT_ENTRY_9798 0x63 283#define B53_VT_ENTRY_63XX 0x64 284#define VTE_MEMBERS 0x1ff 285#define VTE_UNTAG_S 9 286#define VTE_UNTAG (0x1ff << 9) 287 288/************************************************************************* 289 * ARL I/O Registers 290 *************************************************************************/ 291 292/* ARL Table Read/Write Register (8 bit) */ 293#define B53_ARLTBL_RW_CTRL 0x00 294#define ARLTBL_RW BIT(0) 295#define ARLTBL_IVL_SVL_SELECT BIT(6) 296#define ARLTBL_START_DONE BIT(7) 297 298/* MAC Address Index Register (48 bit) */ 299#define B53_MAC_ADDR_IDX 0x02 300 301/* VLAN ID Index Register (16 bit) */ 302#define B53_VLAN_ID_IDX 0x08 303 304/* ARL Table MAC/VID Entry N Registers (64 bit) 305 * 306 * BCM5325 and BCM5365 share most definitions below 307 */ 308#define B53_ARLTBL_MAC_VID_ENTRY(n) ((0x10 * (n)) + 0x10) 309#define ARLTBL_MAC_MASK 0xffffffffffffULL 310#define ARLTBL_VID_S 48 311#define ARLTBL_VID_MASK_25 0xff 312#define ARLTBL_VID_MASK 0xfff 313#define ARLTBL_DATA_PORT_ID_S_25 48 314#define ARLTBL_DATA_PORT_ID_MASK_25 0xf 315#define ARLTBL_AGE_25 BIT(61) 316#define ARLTBL_STATIC_25 BIT(62) 317#define ARLTBL_VALID_25 BIT(63) 318 319/* ARL Table Data Entry N Registers (32 bit) */ 320#define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x18) 321#define ARLTBL_DATA_PORT_ID_MASK 0x1ff 322#define ARLTBL_TC(tc) ((3 & tc) << 11) 323#define ARLTBL_AGE BIT(14) 324#define ARLTBL_STATIC BIT(15) 325#define ARLTBL_VALID BIT(16) 326 327/* Maximum number of bin entries in the ARL for all switches */ 328#define B53_ARLTBL_MAX_BIN_ENTRIES 4 329 330/* ARL Search Control Register (8 bit) */ 331#define B53_ARL_SRCH_CTL 0x50 332#define B53_ARL_SRCH_CTL_25 0x20 333#define ARL_SRCH_VLID BIT(0) 334#define ARL_SRCH_STDN BIT(7) 335 336/* ARL Search Address Register (16 bit) */ 337#define B53_ARL_SRCH_ADDR 0x51 338#define B53_ARL_SRCH_ADDR_25 0x22 339#define B53_ARL_SRCH_ADDR_65 0x24 340#define ARL_ADDR_MASK GENMASK(14, 0) 341 342/* ARL Search MAC/VID Result (64 bit) */ 343#define B53_ARL_SRCH_RSTL_0_MACVID 0x60 344 345/* Single register search result on 5325 */ 346#define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24 347/* Single register search result on 5365 */ 348#define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30 349 350/* ARL Search Data Result (32 bit) */ 351#define B53_ARL_SRCH_RSTL_0 0x68 352 353#define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10)) 354#define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10)) 355 356/************************************************************************* 357 * Port VLAN Registers 358 *************************************************************************/ 359 360/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ 361#define B53_PVLAN_PORT_MASK(i) ((i) * 2) 362 363/* Join all VLANs register (16 bit) */ 364#define B53_JOIN_ALL_VLAN_EN 0x50 365 366/************************************************************************* 367 * 802.1Q Page Registers 368 *************************************************************************/ 369 370/* Global QoS Control (8 bit) */ 371#define B53_QOS_GLOBAL_CTL 0x00 372 373/* Enable 802.1Q for individual Ports (16 bit) */ 374#define B53_802_1P_EN 0x04 375 376/************************************************************************* 377 * VLAN Page Registers 378 *************************************************************************/ 379 380/* VLAN Control 0 (8 bit) */ 381#define B53_VLAN_CTRL0 0x00 382#define VC0_8021PF_CTRL_MASK 0x3 383#define VC0_8021PF_CTRL_NONE 0x0 384#define VC0_8021PF_CTRL_CHANGE_PRI 0x1 385#define VC0_8021PF_CTRL_CHANGE_VID 0x2 386#define VC0_8021PF_CTRL_CHANGE_BOTH 0x3 387#define VC0_8021QF_CTRL_MASK 0xc 388#define VC0_8021QF_CTRL_CHANGE_PRI 0x1 389#define VC0_8021QF_CTRL_CHANGE_VID 0x2 390#define VC0_8021QF_CTRL_CHANGE_BOTH 0x3 391#define VC0_RESERVED_1 BIT(1) 392#define VC0_DROP_VID_MISS BIT(4) 393#define VC0_VID_HASH_VID BIT(5) 394#define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ 395#define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ 396 397/* VLAN Control 1 (8 bit) */ 398#define B53_VLAN_CTRL1 0x01 399#define VC1_RX_MCST_TAG_EN BIT(1) 400#define VC1_RX_MCST_FWD_EN BIT(2) 401#define VC1_RX_MCST_UNTAG_EN BIT(3) 402 403/* VLAN Control 2 (8 bit) */ 404#define B53_VLAN_CTRL2 0x02 405 406/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ 407#define B53_VLAN_CTRL3 0x03 408#define B53_VLAN_CTRL3_63XX 0x04 409#define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ 410#define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ 411 412/* VLAN Control 4 (8 bit) */ 413#define B53_VLAN_CTRL4 0x05 414#define B53_VLAN_CTRL4_25 0x04 415#define B53_VLAN_CTRL4_63XX 0x06 416#define VC4_ING_VID_CHECK_S 6 417#define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S) 418#define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */ 419#define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */ 420#define VC4_NO_ING_VID_CHK 2 /* do not check */ 421#define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */ 422 423/* VLAN Control 5 (8 bit) */ 424#define B53_VLAN_CTRL5 0x06 425#define B53_VLAN_CTRL5_25 0x05 426#define B53_VLAN_CTRL5_63XX 0x07 427#define VC5_VID_FFF_EN BIT(2) 428#define VC5_DROP_VTABLE_MISS BIT(3) 429 430/* VLAN Control 6 (8 bit) */ 431#define B53_VLAN_CTRL6 0x07 432#define B53_VLAN_CTRL6_63XX 0x08 433 434/* VLAN Table Access Register (16 bit) */ 435#define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */ 436#define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */ 437#define VTA_VID_LOW_MASK_25 0xf 438#define VTA_VID_LOW_MASK_65 0xff 439#define VTA_VID_HIGH_S_25 4 440#define VTA_VID_HIGH_S_65 8 441#define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E) 442#define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65) 443#define VTA_RW_STATE BIT(12) 444#define VTA_RW_STATE_RD 0 445#define VTA_RW_STATE_WR BIT(12) 446#define VTA_RW_OP_EN BIT(13) 447 448/* VLAN Read/Write Registers for (16/32 bit) */ 449#define B53_VLAN_WRITE_25 0x08 450#define B53_VLAN_WRITE_65 0x0a 451#define B53_VLAN_READ 0x0c 452#define VA_MEMBER_MASK 0x3f 453#define VA_UNTAG_S_25 6 454#define VA_UNTAG_MASK_25 0x3f 455#define VA_UNTAG_S_65 7 456#define VA_UNTAG_MASK_65 0x1f 457#define VA_VID_HIGH_S 12 458#define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S) 459#define VA_VALID_25 BIT(20) 460#define VA_VALID_25_R4 BIT(24) 461#define VA_VALID_65 BIT(14) 462 463/* VLAN Port Default Tag (16 bit) */ 464#define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) 465 466/************************************************************************* 467 * Jumbo Frame Page Registers 468 *************************************************************************/ 469 470/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ 471#define B53_JUMBO_PORT_MASK 0x01 472#define B53_JUMBO_PORT_MASK_63XX 0x04 473#define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ 474 475/* Good Frame Max Size without 802.1Q TAG (16 bit) */ 476#define B53_JUMBO_MAX_SIZE 0x05 477#define B53_JUMBO_MAX_SIZE_63XX 0x08 478#define JMS_MIN_SIZE 1518 479#define JMS_MAX_SIZE 9724 480 481/************************************************************************* 482 * EEE Configuration Page Registers 483 *************************************************************************/ 484 485/* EEE Enable control register (16 bit) */ 486#define B53_EEE_EN_CTRL 0x00 487 488/* EEE LPI assert status register (16 bit) */ 489#define B53_EEE_LPI_ASSERT_STS 0x02 490 491/* EEE LPI indicate status register (16 bit) */ 492#define B53_EEE_LPI_INDICATE 0x4 493 494/* EEE Receiving idle symbols status register (16 bit) */ 495#define B53_EEE_RX_IDLE_SYM_STS 0x6 496 497/* EEE Pipeline timer register (32 bit) */ 498#define B53_EEE_PIP_TIMER 0xC 499 500/* EEE Sleep timer Gig register (32 bit) */ 501#define B53_EEE_SLEEP_TIMER_GIG(i) (0x10 + 4 * (i)) 502 503/* EEE Sleep timer FE register (32 bit) */ 504#define B53_EEE_SLEEP_TIMER_FE(i) (0x34 + 4 * (i)) 505 506/* EEE Minimum LP timer Gig register (32 bit) */ 507#define B53_EEE_MIN_LP_TIMER_GIG(i) (0x58 + 4 * (i)) 508 509/* EEE Minimum LP timer FE register (32 bit) */ 510#define B53_EEE_MIN_LP_TIMER_FE(i) (0x7c + 4 * (i)) 511 512/* EEE Wake timer Gig register (16 bit) */ 513#define B53_EEE_WAKE_TIMER_GIG(i) (0xa0 + 2 * (i)) 514 515/* EEE Wake timer FE register (16 bit) */ 516#define B53_EEE_WAKE_TIMER_FE(i) (0xb2 + 2 * (i)) 517 518 519/************************************************************************* 520 * CFP Configuration Page Registers 521 *************************************************************************/ 522 523/* CFP Control Register with ports map (8 bit) */ 524#define B53_CFP_CTRL 0x00 525 526#endif /* !__B53_REGS_H */ 527