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35
36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38#include <linux/module.h>
39#include <linux/moduleparam.h>
40#include <linux/init.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/debugfs.h>
46#include <linux/ethtool.h>
47#include <linux/mdio.h>
48
49#include "t4vf_common.h"
50#include "t4vf_defs.h"
51
52#include "../cxgb4/t4_regs.h"
53#include "../cxgb4/t4_msg.h"
54
55
56
57
58#define DRV_DESC "Chelsio T4/T5/T6 Virtual Function (VF) Network Driver"
59
60
61
62
63
64
65
66
67
68#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
69 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
70 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
71
72
73
74
75
76
77
78
79
80
81
82
83
84#define MSI_MSIX 2
85#define MSI_MSI 1
86#define MSI_DEFAULT MSI_MSIX
87
88static int msi = MSI_DEFAULT;
89
90module_param(msi, int, 0644);
91MODULE_PARM_DESC(msi, "whether to use MSI-X or MSI");
92
93
94
95
96
97
98enum {
99 MAX_TXQ_ENTRIES = 16384,
100 MAX_RSPQ_ENTRIES = 16384,
101 MAX_RX_BUFFERS = 16384,
102
103 MIN_TXQ_ENTRIES = 32,
104 MIN_RSPQ_ENTRIES = 128,
105 MIN_FL_ENTRIES = 16,
106
107
108
109
110
111
112
113
114
115
116
117 EQ_UNIT = SGE_EQ_IDXSIZE,
118 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
119 MIN_FL_RESID = FL_PER_EQ_UNIT,
120};
121
122
123
124
125
126
127static struct dentry *cxgb4vf_debugfs_root;
128
129
130
131
132
133
134
135
136
137void t4vf_os_link_changed(struct adapter *adapter, int pidx, int link_ok)
138{
139 struct net_device *dev = adapter->port[pidx];
140
141
142
143
144
145 if (!netif_running(dev) || link_ok == netif_carrier_ok(dev))
146 return;
147
148
149
150
151
152 if (link_ok) {
153 const char *s;
154 const char *fc;
155 const struct port_info *pi = netdev_priv(dev);
156
157 netif_carrier_on(dev);
158
159 switch (pi->link_cfg.speed) {
160 case 100:
161 s = "100Mbps";
162 break;
163 case 1000:
164 s = "1Gbps";
165 break;
166 case 10000:
167 s = "10Gbps";
168 break;
169 case 25000:
170 s = "25Gbps";
171 break;
172 case 40000:
173 s = "40Gbps";
174 break;
175 case 100000:
176 s = "100Gbps";
177 break;
178
179 default:
180 s = "unknown";
181 break;
182 }
183
184 switch ((int)pi->link_cfg.fc) {
185 case PAUSE_RX:
186 fc = "RX";
187 break;
188
189 case PAUSE_TX:
190 fc = "TX";
191 break;
192
193 case PAUSE_RX | PAUSE_TX:
194 fc = "RX/TX";
195 break;
196
197 default:
198 fc = "no";
199 break;
200 }
201
202 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, fc);
203 } else {
204 netif_carrier_off(dev);
205 netdev_info(dev, "link down\n");
206 }
207}
208
209
210
211
212
213void t4vf_os_portmod_changed(struct adapter *adapter, int pidx)
214{
215 static const char * const mod_str[] = {
216 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
217 };
218 const struct net_device *dev = adapter->port[pidx];
219 const struct port_info *pi = netdev_priv(dev);
220
221 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
222 dev_info(adapter->pdev_dev, "%s: port module unplugged\n",
223 dev->name);
224 else if (pi->mod_type < ARRAY_SIZE(mod_str))
225 dev_info(adapter->pdev_dev, "%s: %s port module inserted\n",
226 dev->name, mod_str[pi->mod_type]);
227 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
228 dev_info(adapter->pdev_dev, "%s: unsupported optical port "
229 "module inserted\n", dev->name);
230 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
231 dev_info(adapter->pdev_dev, "%s: unknown port module inserted,"
232 "forcing TWINAX\n", dev->name);
233 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
234 dev_info(adapter->pdev_dev, "%s: transceiver module error\n",
235 dev->name);
236 else
237 dev_info(adapter->pdev_dev, "%s: unknown module type %d "
238 "inserted\n", dev->name, pi->mod_type);
239}
240
241static int cxgb4vf_set_addr_hash(struct port_info *pi)
242{
243 struct adapter *adapter = pi->adapter;
244 u64 vec = 0;
245 bool ucast = false;
246 struct hash_mac_addr *entry;
247
248
249 list_for_each_entry(entry, &adapter->mac_hlist, list) {
250 ucast |= is_unicast_ether_addr(entry->addr);
251 vec |= (1ULL << hash_mac_addr(entry->addr));
252 }
253 return t4vf_set_addr_hash(adapter, pi->viid, ucast, vec, false);
254}
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272static int cxgb4vf_change_mac(struct port_info *pi, unsigned int viid,
273 int *tcam_idx, const u8 *addr, bool persistent)
274{
275 struct hash_mac_addr *new_entry, *entry;
276 struct adapter *adapter = pi->adapter;
277 int ret;
278
279 ret = t4vf_change_mac(adapter, viid, *tcam_idx, addr, persistent);
280
281 if (ret == -ENOMEM) {
282
283
284
285 list_for_each_entry(entry, &adapter->mac_hlist, list) {
286 if (entry->iface_mac) {
287 ether_addr_copy(entry->addr, addr);
288 goto set_hash;
289 }
290 }
291 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
292 if (!new_entry)
293 return -ENOMEM;
294 ether_addr_copy(new_entry->addr, addr);
295 new_entry->iface_mac = true;
296 list_add_tail(&new_entry->list, &adapter->mac_hlist);
297set_hash:
298 ret = cxgb4vf_set_addr_hash(pi);
299 } else if (ret >= 0) {
300 *tcam_idx = ret;
301 ret = 0;
302 }
303
304 return ret;
305}
306
307
308
309
310
311
312
313
314
315
316
317
318
319static int link_start(struct net_device *dev)
320{
321 int ret;
322 struct port_info *pi = netdev_priv(dev);
323
324
325
326
327
328 ret = t4vf_set_rxmode(pi->adapter, pi->viid, dev->mtu, -1, -1, -1, 1,
329 true);
330 if (ret == 0)
331 ret = cxgb4vf_change_mac(pi, pi->viid,
332 &pi->xact_addr_filt,
333 dev->dev_addr, true);
334
335
336
337
338
339
340 if (ret == 0)
341 ret = t4vf_enable_pi(pi->adapter, pi, true, true);
342
343 return ret;
344}
345
346
347
348
349static void name_msix_vecs(struct adapter *adapter)
350{
351 int namelen = sizeof(adapter->msix_info[0].desc) - 1;
352 int pidx;
353
354
355
356
357 snprintf(adapter->msix_info[MSIX_FW].desc, namelen,
358 "%s-FWeventq", adapter->name);
359 adapter->msix_info[MSIX_FW].desc[namelen] = 0;
360
361
362
363
364 for_each_port(adapter, pidx) {
365 struct net_device *dev = adapter->port[pidx];
366 const struct port_info *pi = netdev_priv(dev);
367 int qs, msi;
368
369 for (qs = 0, msi = MSIX_IQFLINT; qs < pi->nqsets; qs++, msi++) {
370 snprintf(adapter->msix_info[msi].desc, namelen,
371 "%s-%d", dev->name, qs);
372 adapter->msix_info[msi].desc[namelen] = 0;
373 }
374 }
375}
376
377
378
379
380static int request_msix_queue_irqs(struct adapter *adapter)
381{
382 struct sge *s = &adapter->sge;
383 int rxq, msi, err;
384
385
386
387
388 err = request_irq(adapter->msix_info[MSIX_FW].vec, t4vf_sge_intr_msix,
389 0, adapter->msix_info[MSIX_FW].desc, &s->fw_evtq);
390 if (err)
391 return err;
392
393
394
395
396 msi = MSIX_IQFLINT;
397 for_each_ethrxq(s, rxq) {
398 err = request_irq(adapter->msix_info[msi].vec,
399 t4vf_sge_intr_msix, 0,
400 adapter->msix_info[msi].desc,
401 &s->ethrxq[rxq].rspq);
402 if (err)
403 goto err_free_irqs;
404 msi++;
405 }
406 return 0;
407
408err_free_irqs:
409 while (--rxq >= 0)
410 free_irq(adapter->msix_info[--msi].vec, &s->ethrxq[rxq].rspq);
411 free_irq(adapter->msix_info[MSIX_FW].vec, &s->fw_evtq);
412 return err;
413}
414
415
416
417
418static void free_msix_queue_irqs(struct adapter *adapter)
419{
420 struct sge *s = &adapter->sge;
421 int rxq, msi;
422
423 free_irq(adapter->msix_info[MSIX_FW].vec, &s->fw_evtq);
424 msi = MSIX_IQFLINT;
425 for_each_ethrxq(s, rxq)
426 free_irq(adapter->msix_info[msi++].vec,
427 &s->ethrxq[rxq].rspq);
428}
429
430
431
432
433static void qenable(struct sge_rspq *rspq)
434{
435 napi_enable(&rspq->napi);
436
437
438
439
440
441 t4_write_reg(rspq->adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
442 CIDXINC_V(0) |
443 SEINTARM_V(rspq->intr_params) |
444 INGRESSQID_V(rspq->cntxt_id));
445}
446
447
448
449
450static void enable_rx(struct adapter *adapter)
451{
452 int rxq;
453 struct sge *s = &adapter->sge;
454
455 for_each_ethrxq(s, rxq)
456 qenable(&s->ethrxq[rxq].rspq);
457 qenable(&s->fw_evtq);
458
459
460
461
462
463 if (adapter->flags & CXGB4VF_USING_MSI)
464 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
465 CIDXINC_V(0) |
466 SEINTARM_V(s->intrq.intr_params) |
467 INGRESSQID_V(s->intrq.cntxt_id));
468
469}
470
471
472
473
474static void quiesce_rx(struct adapter *adapter)
475{
476 struct sge *s = &adapter->sge;
477 int rxq;
478
479 for_each_ethrxq(s, rxq)
480 napi_disable(&s->ethrxq[rxq].rspq.napi);
481 napi_disable(&s->fw_evtq.napi);
482}
483
484
485
486
487static int fwevtq_handler(struct sge_rspq *rspq, const __be64 *rsp,
488 const struct pkt_gl *gl)
489{
490
491
492
493 struct adapter *adapter = rspq->adapter;
494 u8 opcode = ((const struct rss_header *)rsp)->opcode;
495 void *cpl = (void *)(rsp + 1);
496
497 switch (opcode) {
498 case CPL_FW6_MSG: {
499
500
501
502 const struct cpl_fw6_msg *fw_msg = cpl;
503 if (fw_msg->type == FW6_TYPE_CMD_RPL)
504 t4vf_handle_fw_rpl(adapter, fw_msg->data);
505 break;
506 }
507
508 case CPL_FW4_MSG: {
509
510
511 const struct cpl_sge_egr_update *p = (void *)(rsp + 3);
512 opcode = CPL_OPCODE_G(ntohl(p->opcode_qid));
513 if (opcode != CPL_SGE_EGR_UPDATE) {
514 dev_err(adapter->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
515 , opcode);
516 break;
517 }
518 cpl = (void *)p;
519 }
520 fallthrough;
521
522 case CPL_SGE_EGR_UPDATE: {
523
524
525
526
527
528
529
530
531
532 const struct cpl_sge_egr_update *p = cpl;
533 unsigned int qid = EGR_QID_G(be32_to_cpu(p->opcode_qid));
534 struct sge *s = &adapter->sge;
535 struct sge_txq *tq;
536 struct sge_eth_txq *txq;
537 unsigned int eq_idx;
538
539
540
541
542
543
544
545
546 eq_idx = EQ_IDX(s, qid);
547 if (unlikely(eq_idx >= MAX_EGRQ)) {
548 dev_err(adapter->pdev_dev,
549 "Egress Update QID %d out of range\n", qid);
550 break;
551 }
552 tq = s->egr_map[eq_idx];
553 if (unlikely(tq == NULL)) {
554 dev_err(adapter->pdev_dev,
555 "Egress Update QID %d TXQ=NULL\n", qid);
556 break;
557 }
558 txq = container_of(tq, struct sge_eth_txq, q);
559 if (unlikely(tq->abs_id != qid)) {
560 dev_err(adapter->pdev_dev,
561 "Egress Update QID %d refers to TXQ %d\n",
562 qid, tq->abs_id);
563 break;
564 }
565
566
567
568
569
570 txq->q.restarts++;
571 netif_tx_wake_queue(txq->txq);
572 break;
573 }
574
575 default:
576 dev_err(adapter->pdev_dev,
577 "unexpected CPL %#x on FW event queue\n", opcode);
578 }
579
580 return 0;
581}
582
583
584
585
586
587
588static int setup_sge_queues(struct adapter *adapter)
589{
590 struct sge *s = &adapter->sge;
591 int err, pidx, msix;
592
593
594
595
596
597 bitmap_zero(s->starving_fl, MAX_EGRQ);
598
599
600
601
602
603
604
605
606
607 if (adapter->flags & CXGB4VF_USING_MSI) {
608 err = t4vf_sge_alloc_rxq(adapter, &s->intrq, false,
609 adapter->port[0], 0, NULL, NULL);
610 if (err)
611 goto err_free_queues;
612 }
613
614
615
616
617 err = t4vf_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->port[0],
618 MSIX_FW, NULL, fwevtq_handler);
619 if (err)
620 goto err_free_queues;
621
622
623
624
625
626
627
628 msix = MSIX_IQFLINT;
629 for_each_port(adapter, pidx) {
630 struct net_device *dev = adapter->port[pidx];
631 struct port_info *pi = netdev_priv(dev);
632 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset];
633 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset];
634 int qs;
635
636 for (qs = 0; qs < pi->nqsets; qs++, rxq++, txq++) {
637 err = t4vf_sge_alloc_rxq(adapter, &rxq->rspq, false,
638 dev, msix++,
639 &rxq->fl, t4vf_ethrx_handler);
640 if (err)
641 goto err_free_queues;
642
643 err = t4vf_sge_alloc_eth_txq(adapter, txq, dev,
644 netdev_get_tx_queue(dev, qs),
645 s->fw_evtq.cntxt_id);
646 if (err)
647 goto err_free_queues;
648
649 rxq->rspq.idx = qs;
650 memset(&rxq->stats, 0, sizeof(rxq->stats));
651 }
652 }
653
654
655
656
657 s->egr_base = s->ethtxq[0].q.abs_id - s->ethtxq[0].q.cntxt_id;
658 s->ingr_base = s->ethrxq[0].rspq.abs_id - s->ethrxq[0].rspq.cntxt_id;
659 IQ_MAP(s, s->fw_evtq.abs_id) = &s->fw_evtq;
660 for_each_port(adapter, pidx) {
661 struct net_device *dev = adapter->port[pidx];
662 struct port_info *pi = netdev_priv(dev);
663 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset];
664 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset];
665 int qs;
666
667 for (qs = 0; qs < pi->nqsets; qs++, rxq++, txq++) {
668 IQ_MAP(s, rxq->rspq.abs_id) = &rxq->rspq;
669 EQ_MAP(s, txq->q.abs_id) = &txq->q;
670
671
672
673
674
675
676
677
678
679
680 rxq->fl.abs_id = rxq->fl.cntxt_id + s->egr_base;
681 EQ_MAP(s, rxq->fl.abs_id) = &rxq->fl;
682 }
683 }
684 return 0;
685
686err_free_queues:
687 t4vf_free_sge_resources(adapter);
688 return err;
689}
690
691
692
693
694
695
696
697
698
699static int setup_rss(struct adapter *adapter)
700{
701 int pidx;
702
703 for_each_port(adapter, pidx) {
704 struct port_info *pi = adap2pinfo(adapter, pidx);
705 struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[pi->first_qset];
706 u16 rss[MAX_PORT_QSETS];
707 int qs, err;
708
709 for (qs = 0; qs < pi->nqsets; qs++)
710 rss[qs] = rxq[qs].rspq.abs_id;
711
712 err = t4vf_config_rss_range(adapter, pi->viid,
713 0, pi->rss_size, rss, pi->nqsets);
714 if (err)
715 return err;
716
717
718
719
720 switch (adapter->params.rss.mode) {
721 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL:
722
723
724
725
726
727
728
729 if (!adapter->params.rss.u.basicvirtual.tnlalllookup) {
730 union rss_vi_config config;
731 err = t4vf_read_rss_vi_config(adapter,
732 pi->viid,
733 &config);
734 if (err)
735 return err;
736 config.basicvirtual.defaultq =
737 rxq[0].rspq.abs_id;
738 err = t4vf_write_rss_vi_config(adapter,
739 pi->viid,
740 &config);
741 if (err)
742 return err;
743 }
744 break;
745 }
746 }
747
748 return 0;
749}
750
751
752
753
754
755
756
757
758static int adapter_up(struct adapter *adapter)
759{
760 int err;
761
762
763
764
765
766
767 if ((adapter->flags & CXGB4VF_FULL_INIT_DONE) == 0) {
768 err = setup_sge_queues(adapter);
769 if (err)
770 return err;
771 err = setup_rss(adapter);
772 if (err) {
773 t4vf_free_sge_resources(adapter);
774 return err;
775 }
776
777 if (adapter->flags & CXGB4VF_USING_MSIX)
778 name_msix_vecs(adapter);
779
780 adapter->flags |= CXGB4VF_FULL_INIT_DONE;
781 }
782
783
784
785
786 BUG_ON((adapter->flags &
787 (CXGB4VF_USING_MSIX | CXGB4VF_USING_MSI)) == 0);
788 if (adapter->flags & CXGB4VF_USING_MSIX)
789 err = request_msix_queue_irqs(adapter);
790 else
791 err = request_irq(adapter->pdev->irq,
792 t4vf_intr_handler(adapter), 0,
793 adapter->name, adapter);
794 if (err) {
795 dev_err(adapter->pdev_dev, "request_irq failed, err %d\n",
796 err);
797 return err;
798 }
799
800
801
802
803 enable_rx(adapter);
804 t4vf_sge_start(adapter);
805
806 return 0;
807}
808
809
810
811
812
813
814static void adapter_down(struct adapter *adapter)
815{
816
817
818
819 if (adapter->flags & CXGB4VF_USING_MSIX)
820 free_msix_queue_irqs(adapter);
821 else
822 free_irq(adapter->pdev->irq, adapter);
823
824
825
826
827 quiesce_rx(adapter);
828}
829
830
831
832
833static int cxgb4vf_open(struct net_device *dev)
834{
835 int err;
836 struct port_info *pi = netdev_priv(dev);
837 struct adapter *adapter = pi->adapter;
838
839
840
841
842
843 if (!(adapter->flags & CXGB4VF_FW_OK))
844 return -ENXIO;
845
846
847
848
849
850 if (adapter->open_device_map == 0) {
851 err = adapter_up(adapter);
852 if (err)
853 return err;
854 }
855
856
857
858
859 err = t4vf_update_port_info(pi);
860 if (err < 0)
861 return err;
862
863
864
865
866 err = link_start(dev);
867 if (err)
868 goto err_unwind;
869
870 pi->vlan_id = t4vf_get_vf_vlan_acl(adapter);
871
872 netif_tx_start_all_queues(dev);
873 set_bit(pi->port_id, &adapter->open_device_map);
874 return 0;
875
876err_unwind:
877 if (adapter->open_device_map == 0)
878 adapter_down(adapter);
879 return err;
880}
881
882
883
884
885
886static int cxgb4vf_stop(struct net_device *dev)
887{
888 struct port_info *pi = netdev_priv(dev);
889 struct adapter *adapter = pi->adapter;
890
891 netif_tx_stop_all_queues(dev);
892 netif_carrier_off(dev);
893 t4vf_enable_pi(adapter, pi, false, false);
894
895 clear_bit(pi->port_id, &adapter->open_device_map);
896 if (adapter->open_device_map == 0)
897 adapter_down(adapter);
898 return 0;
899}
900
901
902
903
904static struct net_device_stats *cxgb4vf_get_stats(struct net_device *dev)
905{
906 struct t4vf_port_stats stats;
907 struct port_info *pi = netdev2pinfo(dev);
908 struct adapter *adapter = pi->adapter;
909 struct net_device_stats *ns = &dev->stats;
910 int err;
911
912 spin_lock(&adapter->stats_lock);
913 err = t4vf_get_port_stats(adapter, pi->pidx, &stats);
914 spin_unlock(&adapter->stats_lock);
915
916 memset(ns, 0, sizeof(*ns));
917 if (err)
918 return ns;
919
920 ns->tx_bytes = (stats.tx_bcast_bytes + stats.tx_mcast_bytes +
921 stats.tx_ucast_bytes + stats.tx_offload_bytes);
922 ns->tx_packets = (stats.tx_bcast_frames + stats.tx_mcast_frames +
923 stats.tx_ucast_frames + stats.tx_offload_frames);
924 ns->rx_bytes = (stats.rx_bcast_bytes + stats.rx_mcast_bytes +
925 stats.rx_ucast_bytes);
926 ns->rx_packets = (stats.rx_bcast_frames + stats.rx_mcast_frames +
927 stats.rx_ucast_frames);
928 ns->multicast = stats.rx_mcast_frames;
929 ns->tx_errors = stats.tx_drop_frames;
930 ns->rx_errors = stats.rx_err_frames;
931
932 return ns;
933}
934
935static int cxgb4vf_mac_sync(struct net_device *netdev, const u8 *mac_addr)
936{
937 struct port_info *pi = netdev_priv(netdev);
938 struct adapter *adapter = pi->adapter;
939 int ret;
940 u64 mhash = 0;
941 u64 uhash = 0;
942 bool free = false;
943 bool ucast = is_unicast_ether_addr(mac_addr);
944 const u8 *maclist[1] = {mac_addr};
945 struct hash_mac_addr *new_entry;
946
947 ret = t4vf_alloc_mac_filt(adapter, pi->viid, free, 1, maclist,
948 NULL, ucast ? &uhash : &mhash, false);
949 if (ret < 0)
950 goto out;
951
952
953
954
955 if (uhash || mhash) {
956 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
957 if (!new_entry)
958 return -ENOMEM;
959 ether_addr_copy(new_entry->addr, mac_addr);
960 list_add_tail(&new_entry->list, &adapter->mac_hlist);
961 ret = cxgb4vf_set_addr_hash(pi);
962 }
963out:
964 return ret < 0 ? ret : 0;
965}
966
967static int cxgb4vf_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
968{
969 struct port_info *pi = netdev_priv(netdev);
970 struct adapter *adapter = pi->adapter;
971 int ret;
972 const u8 *maclist[1] = {mac_addr};
973 struct hash_mac_addr *entry, *tmp;
974
975
976
977
978 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist, list) {
979 if (ether_addr_equal(entry->addr, mac_addr)) {
980 list_del(&entry->list);
981 kfree(entry);
982 return cxgb4vf_set_addr_hash(pi);
983 }
984 }
985
986 ret = t4vf_free_mac_filt(adapter, pi->viid, 1, maclist, false);
987 return ret < 0 ? -EINVAL : 0;
988}
989
990
991
992
993
994static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
995{
996 struct port_info *pi = netdev_priv(dev);
997
998 __dev_uc_sync(dev, cxgb4vf_mac_sync, cxgb4vf_mac_unsync);
999 __dev_mc_sync(dev, cxgb4vf_mac_sync, cxgb4vf_mac_unsync);
1000 return t4vf_set_rxmode(pi->adapter, pi->viid, -1,
1001 (dev->flags & IFF_PROMISC) != 0,
1002 (dev->flags & IFF_ALLMULTI) != 0,
1003 1, -1, sleep_ok);
1004}
1005
1006
1007
1008
1009static void cxgb4vf_set_rxmode(struct net_device *dev)
1010{
1011
1012 set_rxmode(dev, -1, false);
1013}
1014
1015
1016
1017
1018
1019static int closest_timer(const struct sge *s, int us)
1020{
1021 int i, timer_idx = 0, min_delta = INT_MAX;
1022
1023 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1024 int delta = us - s->timer_val[i];
1025 if (delta < 0)
1026 delta = -delta;
1027 if (delta < min_delta) {
1028 min_delta = delta;
1029 timer_idx = i;
1030 }
1031 }
1032 return timer_idx;
1033}
1034
1035static int closest_thres(const struct sge *s, int thres)
1036{
1037 int i, delta, pktcnt_idx = 0, min_delta = INT_MAX;
1038
1039 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1040 delta = thres - s->counter_val[i];
1041 if (delta < 0)
1042 delta = -delta;
1043 if (delta < min_delta) {
1044 min_delta = delta;
1045 pktcnt_idx = i;
1046 }
1047 }
1048 return pktcnt_idx;
1049}
1050
1051
1052
1053
1054static unsigned int qtimer_val(const struct adapter *adapter,
1055 const struct sge_rspq *rspq)
1056{
1057 unsigned int timer_idx = QINTR_TIMER_IDX_G(rspq->intr_params);
1058
1059 return timer_idx < SGE_NTIMERS
1060 ? adapter->sge.timer_val[timer_idx]
1061 : 0;
1062}
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075static int set_rxq_intr_params(struct adapter *adapter, struct sge_rspq *rspq,
1076 unsigned int us, unsigned int cnt)
1077{
1078 unsigned int timer_idx;
1079
1080
1081
1082
1083
1084 if ((us | cnt) == 0)
1085 cnt = 1;
1086
1087
1088
1089
1090
1091
1092
1093 if (cnt) {
1094 int err;
1095 u32 v, pktcnt_idx;
1096
1097 pktcnt_idx = closest_thres(&adapter->sge, cnt);
1098 if (rspq->desc && rspq->pktcnt_idx != pktcnt_idx) {
1099 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1100 FW_PARAMS_PARAM_X_V(
1101 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1102 FW_PARAMS_PARAM_YZ_V(rspq->cntxt_id);
1103 err = t4vf_set_params(adapter, 1, &v, &pktcnt_idx);
1104 if (err)
1105 return err;
1106 }
1107 rspq->pktcnt_idx = pktcnt_idx;
1108 }
1109
1110
1111
1112
1113
1114 timer_idx = (us == 0
1115 ? SGE_TIMER_RSTRT_CNTR
1116 : closest_timer(&adapter->sge, us));
1117
1118
1119
1120
1121
1122 rspq->intr_params = (QINTR_TIMER_IDX_V(timer_idx) |
1123 QINTR_CNT_EN_V(cnt > 0));
1124 return 0;
1125}
1126
1127
1128
1129
1130
1131
1132static inline unsigned int mk_adap_vers(const struct adapter *adapter)
1133{
1134
1135
1136
1137 return CHELSIO_CHIP_VERSION(adapter->params.chip) | (0x3f << 10);
1138}
1139
1140
1141
1142
1143static int cxgb4vf_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1144{
1145 int ret = 0;
1146
1147 switch (cmd) {
1148
1149
1150
1151
1152
1153
1154 default:
1155 ret = -EOPNOTSUPP;
1156 break;
1157 }
1158 return ret;
1159}
1160
1161
1162
1163
1164static int cxgb4vf_change_mtu(struct net_device *dev, int new_mtu)
1165{
1166 int ret;
1167 struct port_info *pi = netdev_priv(dev);
1168
1169 ret = t4vf_set_rxmode(pi->adapter, pi->viid, new_mtu,
1170 -1, -1, -1, -1, true);
1171 if (!ret)
1172 dev->mtu = new_mtu;
1173 return ret;
1174}
1175
1176static netdev_features_t cxgb4vf_fix_features(struct net_device *dev,
1177 netdev_features_t features)
1178{
1179
1180
1181
1182
1183 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1184 features |= NETIF_F_HW_VLAN_CTAG_TX;
1185 else
1186 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1187
1188 return features;
1189}
1190
1191static int cxgb4vf_set_features(struct net_device *dev,
1192 netdev_features_t features)
1193{
1194 struct port_info *pi = netdev_priv(dev);
1195 netdev_features_t changed = dev->features ^ features;
1196
1197 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1198 t4vf_set_rxmode(pi->adapter, pi->viid, -1, -1, -1, -1,
1199 features & NETIF_F_HW_VLAN_CTAG_TX, 0);
1200
1201 return 0;
1202}
1203
1204
1205
1206
1207static int cxgb4vf_set_mac_addr(struct net_device *dev, void *_addr)
1208{
1209 int ret;
1210 struct sockaddr *addr = _addr;
1211 struct port_info *pi = netdev_priv(dev);
1212
1213 if (!is_valid_ether_addr(addr->sa_data))
1214 return -EADDRNOTAVAIL;
1215
1216 ret = cxgb4vf_change_mac(pi, pi->viid, &pi->xact_addr_filt,
1217 addr->sa_data, true);
1218 if (ret < 0)
1219 return ret;
1220
1221 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1222 return 0;
1223}
1224
1225#ifdef CONFIG_NET_POLL_CONTROLLER
1226
1227
1228
1229
1230static void cxgb4vf_poll_controller(struct net_device *dev)
1231{
1232 struct port_info *pi = netdev_priv(dev);
1233 struct adapter *adapter = pi->adapter;
1234
1235 if (adapter->flags & CXGB4VF_USING_MSIX) {
1236 struct sge_eth_rxq *rxq;
1237 int nqsets;
1238
1239 rxq = &adapter->sge.ethrxq[pi->first_qset];
1240 for (nqsets = pi->nqsets; nqsets; nqsets--) {
1241 t4vf_sge_intr_msix(0, &rxq->rspq);
1242 rxq++;
1243 }
1244 } else
1245 t4vf_intr_handler(adapter)(0, adapter);
1246}
1247#endif
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264static int from_fw_port_mod_type(enum fw_port_type port_type,
1265 enum fw_port_module_type mod_type)
1266{
1267 if (port_type == FW_PORT_TYPE_BT_SGMII ||
1268 port_type == FW_PORT_TYPE_BT_XFI ||
1269 port_type == FW_PORT_TYPE_BT_XAUI) {
1270 return PORT_TP;
1271 } else if (port_type == FW_PORT_TYPE_FIBER_XFI ||
1272 port_type == FW_PORT_TYPE_FIBER_XAUI) {
1273 return PORT_FIBRE;
1274 } else if (port_type == FW_PORT_TYPE_SFP ||
1275 port_type == FW_PORT_TYPE_QSFP_10G ||
1276 port_type == FW_PORT_TYPE_QSA ||
1277 port_type == FW_PORT_TYPE_QSFP ||
1278 port_type == FW_PORT_TYPE_CR4_QSFP ||
1279 port_type == FW_PORT_TYPE_CR_QSFP ||
1280 port_type == FW_PORT_TYPE_CR2_QSFP ||
1281 port_type == FW_PORT_TYPE_SFP28) {
1282 if (mod_type == FW_PORT_MOD_TYPE_LR ||
1283 mod_type == FW_PORT_MOD_TYPE_SR ||
1284 mod_type == FW_PORT_MOD_TYPE_ER ||
1285 mod_type == FW_PORT_MOD_TYPE_LRM)
1286 return PORT_FIBRE;
1287 else if (mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
1288 mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
1289 return PORT_DA;
1290 else
1291 return PORT_OTHER;
1292 } else if (port_type == FW_PORT_TYPE_KR4_100G ||
1293 port_type == FW_PORT_TYPE_KR_SFP28 ||
1294 port_type == FW_PORT_TYPE_KR_XLAUI) {
1295 return PORT_NONE;
1296 }
1297
1298 return PORT_OTHER;
1299}
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310static void fw_caps_to_lmm(enum fw_port_type port_type,
1311 unsigned int fw_caps,
1312 unsigned long *link_mode_mask)
1313{
1314 #define SET_LMM(__lmm_name) \
1315 __set_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \
1316 link_mode_mask)
1317
1318 #define FW_CAPS_TO_LMM(__fw_name, __lmm_name) \
1319 do { \
1320 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1321 SET_LMM(__lmm_name); \
1322 } while (0)
1323
1324 switch (port_type) {
1325 case FW_PORT_TYPE_BT_SGMII:
1326 case FW_PORT_TYPE_BT_XFI:
1327 case FW_PORT_TYPE_BT_XAUI:
1328 SET_LMM(TP);
1329 FW_CAPS_TO_LMM(SPEED_100M, 100baseT_Full);
1330 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
1331 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
1332 break;
1333
1334 case FW_PORT_TYPE_KX4:
1335 case FW_PORT_TYPE_KX:
1336 SET_LMM(Backplane);
1337 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
1338 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
1339 break;
1340
1341 case FW_PORT_TYPE_KR:
1342 SET_LMM(Backplane);
1343 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
1344 break;
1345
1346 case FW_PORT_TYPE_BP_AP:
1347 SET_LMM(Backplane);
1348 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
1349 FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
1350 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
1351 break;
1352
1353 case FW_PORT_TYPE_BP4_AP:
1354 SET_LMM(Backplane);
1355 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
1356 FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
1357 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
1358 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
1359 break;
1360
1361 case FW_PORT_TYPE_FIBER_XFI:
1362 case FW_PORT_TYPE_FIBER_XAUI:
1363 case FW_PORT_TYPE_SFP:
1364 case FW_PORT_TYPE_QSFP_10G:
1365 case FW_PORT_TYPE_QSA:
1366 SET_LMM(FIBRE);
1367 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
1368 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
1369 break;
1370
1371 case FW_PORT_TYPE_BP40_BA:
1372 case FW_PORT_TYPE_QSFP:
1373 SET_LMM(FIBRE);
1374 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
1375 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
1376 FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
1377 break;
1378
1379 case FW_PORT_TYPE_CR_QSFP:
1380 case FW_PORT_TYPE_SFP28:
1381 SET_LMM(FIBRE);
1382 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
1383 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
1384 FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
1385 break;
1386
1387 case FW_PORT_TYPE_KR_SFP28:
1388 SET_LMM(Backplane);
1389 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
1390 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
1391 FW_CAPS_TO_LMM(SPEED_25G, 25000baseKR_Full);
1392 break;
1393
1394 case FW_PORT_TYPE_KR_XLAUI:
1395 SET_LMM(Backplane);
1396 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
1397 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
1398 FW_CAPS_TO_LMM(SPEED_40G, 40000baseKR4_Full);
1399 break;
1400
1401 case FW_PORT_TYPE_CR2_QSFP:
1402 SET_LMM(FIBRE);
1403 FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
1404 break;
1405
1406 case FW_PORT_TYPE_KR4_100G:
1407 case FW_PORT_TYPE_CR4_QSFP:
1408 SET_LMM(FIBRE);
1409 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
1410 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
1411 FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
1412 FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
1413 FW_CAPS_TO_LMM(SPEED_50G, 50000baseCR2_Full);
1414 FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR4_Full);
1415 break;
1416
1417 default:
1418 break;
1419 }
1420
1421 if (fw_caps & FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M)) {
1422 FW_CAPS_TO_LMM(FEC_RS, FEC_RS);
1423 FW_CAPS_TO_LMM(FEC_BASER_RS, FEC_BASER);
1424 } else {
1425 SET_LMM(FEC_NONE);
1426 }
1427
1428 FW_CAPS_TO_LMM(ANEG, Autoneg);
1429 FW_CAPS_TO_LMM(802_3_PAUSE, Pause);
1430 FW_CAPS_TO_LMM(802_3_ASM_DIR, Asym_Pause);
1431
1432 #undef FW_CAPS_TO_LMM
1433 #undef SET_LMM
1434}
1435
1436static int cxgb4vf_get_link_ksettings(struct net_device *dev,
1437 struct ethtool_link_ksettings *link_ksettings)
1438{
1439 struct port_info *pi = netdev_priv(dev);
1440 struct ethtool_link_settings *base = &link_ksettings->base;
1441
1442
1443
1444
1445
1446 if (!netif_running(dev))
1447 (void)t4vf_update_port_info(pi);
1448
1449 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1450 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
1451 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
1452
1453 base->port = from_fw_port_mod_type(pi->port_type, pi->mod_type);
1454
1455 if (pi->mdio_addr >= 0) {
1456 base->phy_address = pi->mdio_addr;
1457 base->mdio_support = (pi->port_type == FW_PORT_TYPE_BT_SGMII
1458 ? ETH_MDIO_SUPPORTS_C22
1459 : ETH_MDIO_SUPPORTS_C45);
1460 } else {
1461 base->phy_address = 255;
1462 base->mdio_support = 0;
1463 }
1464
1465 fw_caps_to_lmm(pi->port_type, pi->link_cfg.pcaps,
1466 link_ksettings->link_modes.supported);
1467 fw_caps_to_lmm(pi->port_type, pi->link_cfg.acaps,
1468 link_ksettings->link_modes.advertising);
1469 fw_caps_to_lmm(pi->port_type, pi->link_cfg.lpacaps,
1470 link_ksettings->link_modes.lp_advertising);
1471
1472 if (netif_carrier_ok(dev)) {
1473 base->speed = pi->link_cfg.speed;
1474 base->duplex = DUPLEX_FULL;
1475 } else {
1476 base->speed = SPEED_UNKNOWN;
1477 base->duplex = DUPLEX_UNKNOWN;
1478 }
1479
1480 base->autoneg = pi->link_cfg.autoneg;
1481 if (pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)
1482 ethtool_link_ksettings_add_link_mode(link_ksettings,
1483 supported, Autoneg);
1484 if (pi->link_cfg.autoneg)
1485 ethtool_link_ksettings_add_link_mode(link_ksettings,
1486 advertising, Autoneg);
1487
1488 return 0;
1489}
1490
1491
1492static inline unsigned int fwcap_to_eth_fec(unsigned int fw_fec)
1493{
1494 unsigned int eth_fec = 0;
1495
1496 if (fw_fec & FW_PORT_CAP32_FEC_RS)
1497 eth_fec |= ETHTOOL_FEC_RS;
1498 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
1499 eth_fec |= ETHTOOL_FEC_BASER;
1500
1501
1502 if (!eth_fec)
1503 eth_fec = ETHTOOL_FEC_OFF;
1504
1505 return eth_fec;
1506}
1507
1508
1509static inline unsigned int cc_to_eth_fec(unsigned int cc_fec)
1510{
1511 unsigned int eth_fec = 0;
1512
1513 if (cc_fec & FEC_AUTO)
1514 eth_fec |= ETHTOOL_FEC_AUTO;
1515 if (cc_fec & FEC_RS)
1516 eth_fec |= ETHTOOL_FEC_RS;
1517 if (cc_fec & FEC_BASER_RS)
1518 eth_fec |= ETHTOOL_FEC_BASER;
1519
1520
1521 if (!eth_fec)
1522 eth_fec = ETHTOOL_FEC_OFF;
1523
1524 return eth_fec;
1525}
1526
1527static int cxgb4vf_get_fecparam(struct net_device *dev,
1528 struct ethtool_fecparam *fec)
1529{
1530 const struct port_info *pi = netdev_priv(dev);
1531 const struct link_config *lc = &pi->link_cfg;
1532
1533
1534
1535
1536
1537 fec->fec = fwcap_to_eth_fec(lc->pcaps);
1538 if (fec->fec != ETHTOOL_FEC_OFF)
1539 fec->fec |= ETHTOOL_FEC_AUTO;
1540
1541
1542
1543
1544 fec->active_fec = cc_to_eth_fec(lc->fec);
1545 return 0;
1546}
1547
1548
1549
1550
1551static void cxgb4vf_get_drvinfo(struct net_device *dev,
1552 struct ethtool_drvinfo *drvinfo)
1553{
1554 struct adapter *adapter = netdev2adap(dev);
1555
1556 strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
1557 strlcpy(drvinfo->bus_info, pci_name(to_pci_dev(dev->dev.parent)),
1558 sizeof(drvinfo->bus_info));
1559 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1560 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1561 FW_HDR_FW_VER_MAJOR_G(adapter->params.dev.fwrev),
1562 FW_HDR_FW_VER_MINOR_G(adapter->params.dev.fwrev),
1563 FW_HDR_FW_VER_MICRO_G(adapter->params.dev.fwrev),
1564 FW_HDR_FW_VER_BUILD_G(adapter->params.dev.fwrev),
1565 FW_HDR_FW_VER_MAJOR_G(adapter->params.dev.tprev),
1566 FW_HDR_FW_VER_MINOR_G(adapter->params.dev.tprev),
1567 FW_HDR_FW_VER_MICRO_G(adapter->params.dev.tprev),
1568 FW_HDR_FW_VER_BUILD_G(adapter->params.dev.tprev));
1569}
1570
1571
1572
1573
1574static u32 cxgb4vf_get_msglevel(struct net_device *dev)
1575{
1576 return netdev2adap(dev)->msg_enable;
1577}
1578
1579
1580
1581
1582static void cxgb4vf_set_msglevel(struct net_device *dev, u32 msglevel)
1583{
1584 netdev2adap(dev)->msg_enable = msglevel;
1585}
1586
1587
1588
1589
1590
1591
1592
1593static void cxgb4vf_get_ringparam(struct net_device *dev,
1594 struct ethtool_ringparam *rp)
1595{
1596 const struct port_info *pi = netdev_priv(dev);
1597 const struct sge *s = &pi->adapter->sge;
1598
1599 rp->rx_max_pending = MAX_RX_BUFFERS;
1600 rp->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
1601 rp->rx_jumbo_max_pending = 0;
1602 rp->tx_max_pending = MAX_TXQ_ENTRIES;
1603
1604 rp->rx_pending = s->ethrxq[pi->first_qset].fl.size - MIN_FL_RESID;
1605 rp->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
1606 rp->rx_jumbo_pending = 0;
1607 rp->tx_pending = s->ethtxq[pi->first_qset].q.size;
1608}
1609
1610
1611
1612
1613
1614
1615
1616static int cxgb4vf_set_ringparam(struct net_device *dev,
1617 struct ethtool_ringparam *rp)
1618{
1619 const struct port_info *pi = netdev_priv(dev);
1620 struct adapter *adapter = pi->adapter;
1621 struct sge *s = &adapter->sge;
1622 int qs;
1623
1624 if (rp->rx_pending > MAX_RX_BUFFERS ||
1625 rp->rx_jumbo_pending ||
1626 rp->tx_pending > MAX_TXQ_ENTRIES ||
1627 rp->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1628 rp->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1629 rp->rx_pending < MIN_FL_ENTRIES ||
1630 rp->tx_pending < MIN_TXQ_ENTRIES)
1631 return -EINVAL;
1632
1633 if (adapter->flags & CXGB4VF_FULL_INIT_DONE)
1634 return -EBUSY;
1635
1636 for (qs = pi->first_qset; qs < pi->first_qset + pi->nqsets; qs++) {
1637 s->ethrxq[qs].fl.size = rp->rx_pending + MIN_FL_RESID;
1638 s->ethrxq[qs].rspq.size = rp->rx_mini_pending;
1639 s->ethtxq[qs].q.size = rp->tx_pending;
1640 }
1641 return 0;
1642}
1643
1644
1645
1646
1647
1648
1649static int cxgb4vf_get_coalesce(struct net_device *dev,
1650 struct ethtool_coalesce *coalesce)
1651{
1652 const struct port_info *pi = netdev_priv(dev);
1653 const struct adapter *adapter = pi->adapter;
1654 const struct sge_rspq *rspq = &adapter->sge.ethrxq[pi->first_qset].rspq;
1655
1656 coalesce->rx_coalesce_usecs = qtimer_val(adapter, rspq);
1657 coalesce->rx_max_coalesced_frames =
1658 ((rspq->intr_params & QINTR_CNT_EN_F)
1659 ? adapter->sge.counter_val[rspq->pktcnt_idx]
1660 : 0);
1661 return 0;
1662}
1663
1664
1665
1666
1667
1668
1669static int cxgb4vf_set_coalesce(struct net_device *dev,
1670 struct ethtool_coalesce *coalesce)
1671{
1672 const struct port_info *pi = netdev_priv(dev);
1673 struct adapter *adapter = pi->adapter;
1674
1675 return set_rxq_intr_params(adapter,
1676 &adapter->sge.ethrxq[pi->first_qset].rspq,
1677 coalesce->rx_coalesce_usecs,
1678 coalesce->rx_max_coalesced_frames);
1679}
1680
1681
1682
1683
1684static void cxgb4vf_get_pauseparam(struct net_device *dev,
1685 struct ethtool_pauseparam *pauseparam)
1686{
1687 struct port_info *pi = netdev_priv(dev);
1688
1689 pauseparam->autoneg = (pi->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
1690 pauseparam->rx_pause = (pi->link_cfg.advertised_fc & PAUSE_RX) != 0;
1691 pauseparam->tx_pause = (pi->link_cfg.advertised_fc & PAUSE_TX) != 0;
1692}
1693
1694
1695
1696
1697static int cxgb4vf_phys_id(struct net_device *dev,
1698 enum ethtool_phys_id_state state)
1699{
1700 unsigned int val;
1701 struct port_info *pi = netdev_priv(dev);
1702
1703 if (state == ETHTOOL_ID_ACTIVE)
1704 val = 0xffff;
1705 else if (state == ETHTOOL_ID_INACTIVE)
1706 val = 0;
1707 else
1708 return -EINVAL;
1709
1710 return t4vf_identify_port(pi->adapter, pi->viid, val);
1711}
1712
1713
1714
1715
1716struct queue_port_stats {
1717 u64 tso;
1718 u64 tx_csum;
1719 u64 rx_csum;
1720 u64 vlan_ex;
1721 u64 vlan_ins;
1722 u64 lro_pkts;
1723 u64 lro_merged;
1724};
1725
1726
1727
1728
1729
1730
1731static const char stats_strings[][ETH_GSTRING_LEN] = {
1732
1733
1734
1735 "TxBroadcastBytes ",
1736 "TxBroadcastFrames ",
1737 "TxMulticastBytes ",
1738 "TxMulticastFrames ",
1739 "TxUnicastBytes ",
1740 "TxUnicastFrames ",
1741 "TxDroppedFrames ",
1742 "TxOffloadBytes ",
1743 "TxOffloadFrames ",
1744 "RxBroadcastBytes ",
1745 "RxBroadcastFrames ",
1746 "RxMulticastBytes ",
1747 "RxMulticastFrames ",
1748 "RxUnicastBytes ",
1749 "RxUnicastFrames ",
1750 "RxErrorFrames ",
1751
1752
1753
1754
1755
1756 "TSO ",
1757 "TxCsumOffload ",
1758 "RxCsumGood ",
1759 "VLANextractions ",
1760 "VLANinsertions ",
1761 "GROPackets ",
1762 "GROMerged ",
1763};
1764
1765
1766
1767
1768static int cxgb4vf_get_sset_count(struct net_device *dev, int sset)
1769{
1770 switch (sset) {
1771 case ETH_SS_STATS:
1772 return ARRAY_SIZE(stats_strings);
1773 default:
1774 return -EOPNOTSUPP;
1775 }
1776
1777}
1778
1779
1780
1781
1782static void cxgb4vf_get_strings(struct net_device *dev,
1783 u32 sset,
1784 u8 *data)
1785{
1786 switch (sset) {
1787 case ETH_SS_STATS:
1788 memcpy(data, stats_strings, sizeof(stats_strings));
1789 break;
1790 }
1791}
1792
1793
1794
1795
1796
1797static void collect_sge_port_stats(const struct adapter *adapter,
1798 const struct port_info *pi,
1799 struct queue_port_stats *stats)
1800{
1801 const struct sge_eth_txq *txq = &adapter->sge.ethtxq[pi->first_qset];
1802 const struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[pi->first_qset];
1803 int qs;
1804
1805 memset(stats, 0, sizeof(*stats));
1806 for (qs = 0; qs < pi->nqsets; qs++, rxq++, txq++) {
1807 stats->tso += txq->tso;
1808 stats->tx_csum += txq->tx_cso;
1809 stats->rx_csum += rxq->stats.rx_cso;
1810 stats->vlan_ex += rxq->stats.vlan_ex;
1811 stats->vlan_ins += txq->vlan_ins;
1812 stats->lro_pkts += rxq->stats.lro_pkts;
1813 stats->lro_merged += rxq->stats.lro_merged;
1814 }
1815}
1816
1817
1818
1819
1820static void cxgb4vf_get_ethtool_stats(struct net_device *dev,
1821 struct ethtool_stats *stats,
1822 u64 *data)
1823{
1824 struct port_info *pi = netdev2pinfo(dev);
1825 struct adapter *adapter = pi->adapter;
1826 int err = t4vf_get_port_stats(adapter, pi->pidx,
1827 (struct t4vf_port_stats *)data);
1828 if (err)
1829 memset(data, 0, sizeof(struct t4vf_port_stats));
1830
1831 data += sizeof(struct t4vf_port_stats) / sizeof(u64);
1832 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1833}
1834
1835
1836
1837
1838static int cxgb4vf_get_regs_len(struct net_device *dev)
1839{
1840 return T4VF_REGMAP_SIZE;
1841}
1842
1843
1844
1845
1846static void reg_block_dump(struct adapter *adapter, void *regbuf,
1847 unsigned int start, unsigned int end)
1848{
1849 u32 *bp = regbuf + start - T4VF_REGMAP_START;
1850
1851 for ( ; start <= end; start += sizeof(u32)) {
1852
1853
1854
1855
1856
1857 if (start == T4VF_CIM_BASE_ADDR + CIM_VF_EXT_MAILBOX_CTRL)
1858 *bp++ = 0xffff;
1859 else
1860 *bp++ = t4_read_reg(adapter, start);
1861 }
1862}
1863
1864
1865
1866
1867static void cxgb4vf_get_regs(struct net_device *dev,
1868 struct ethtool_regs *regs,
1869 void *regbuf)
1870{
1871 struct adapter *adapter = netdev2adap(dev);
1872
1873 regs->version = mk_adap_vers(adapter);
1874
1875
1876
1877
1878 memset(regbuf, 0, T4VF_REGMAP_SIZE);
1879
1880 reg_block_dump(adapter, regbuf,
1881 T4VF_SGE_BASE_ADDR + T4VF_MOD_MAP_SGE_FIRST,
1882 T4VF_SGE_BASE_ADDR + T4VF_MOD_MAP_SGE_LAST);
1883 reg_block_dump(adapter, regbuf,
1884 T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_FIRST,
1885 T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_LAST);
1886
1887
1888
1889 reg_block_dump(adapter, regbuf,
1890 T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST,
1891 T4VF_PL_BASE_ADDR + (is_t4(adapter->params.chip)
1892 ? PL_VF_WHOAMI_A : PL_VF_REVISION_A));
1893 reg_block_dump(adapter, regbuf,
1894 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST,
1895 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST);
1896
1897 reg_block_dump(adapter, regbuf,
1898 T4VF_MBDATA_BASE_ADDR + T4VF_MBDATA_FIRST,
1899 T4VF_MBDATA_BASE_ADDR + T4VF_MBDATA_LAST);
1900}
1901
1902
1903
1904
1905static void cxgb4vf_get_wol(struct net_device *dev,
1906 struct ethtool_wolinfo *wol)
1907{
1908 wol->supported = 0;
1909 wol->wolopts = 0;
1910 memset(&wol->sopass, 0, sizeof(wol->sopass));
1911}
1912
1913
1914
1915
1916#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
1917#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
1918 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
1919
1920static const struct ethtool_ops cxgb4vf_ethtool_ops = {
1921 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1922 ETHTOOL_COALESCE_RX_MAX_FRAMES,
1923 .get_link_ksettings = cxgb4vf_get_link_ksettings,
1924 .get_fecparam = cxgb4vf_get_fecparam,
1925 .get_drvinfo = cxgb4vf_get_drvinfo,
1926 .get_msglevel = cxgb4vf_get_msglevel,
1927 .set_msglevel = cxgb4vf_set_msglevel,
1928 .get_ringparam = cxgb4vf_get_ringparam,
1929 .set_ringparam = cxgb4vf_set_ringparam,
1930 .get_coalesce = cxgb4vf_get_coalesce,
1931 .set_coalesce = cxgb4vf_set_coalesce,
1932 .get_pauseparam = cxgb4vf_get_pauseparam,
1933 .get_link = ethtool_op_get_link,
1934 .get_strings = cxgb4vf_get_strings,
1935 .set_phys_id = cxgb4vf_phys_id,
1936 .get_sset_count = cxgb4vf_get_sset_count,
1937 .get_ethtool_stats = cxgb4vf_get_ethtool_stats,
1938 .get_regs_len = cxgb4vf_get_regs_len,
1939 .get_regs = cxgb4vf_get_regs,
1940 .get_wol = cxgb4vf_get_wol,
1941};
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959static int mboxlog_show(struct seq_file *seq, void *v)
1960{
1961 struct adapter *adapter = seq->private;
1962 struct mbox_cmd_log *log = adapter->mbox_log;
1963 struct mbox_cmd *entry;
1964 int entry_idx, i;
1965
1966 if (v == SEQ_START_TOKEN) {
1967 seq_printf(seq,
1968 "%10s %15s %5s %5s %s\n",
1969 "Seq#", "Tstamp", "Atime", "Etime",
1970 "Command/Reply");
1971 return 0;
1972 }
1973
1974 entry_idx = log->cursor + ((uintptr_t)v - 2);
1975 if (entry_idx >= log->size)
1976 entry_idx -= log->size;
1977 entry = mbox_cmd_log_entry(log, entry_idx);
1978
1979
1980 if (entry->timestamp == 0)
1981 return 0;
1982
1983 seq_printf(seq, "%10u %15llu %5d %5d",
1984 entry->seqno, entry->timestamp,
1985 entry->access, entry->execute);
1986 for (i = 0; i < MBOX_LEN / 8; i++) {
1987 u64 flit = entry->cmd[i];
1988 u32 hi = (u32)(flit >> 32);
1989 u32 lo = (u32)flit;
1990
1991 seq_printf(seq, " %08x %08x", hi, lo);
1992 }
1993 seq_puts(seq, "\n");
1994 return 0;
1995}
1996
1997static inline void *mboxlog_get_idx(struct seq_file *seq, loff_t pos)
1998{
1999 struct adapter *adapter = seq->private;
2000 struct mbox_cmd_log *log = adapter->mbox_log;
2001
2002 return ((pos <= log->size) ? (void *)(uintptr_t)(pos + 1) : NULL);
2003}
2004
2005static void *mboxlog_start(struct seq_file *seq, loff_t *pos)
2006{
2007 return *pos ? mboxlog_get_idx(seq, *pos) : SEQ_START_TOKEN;
2008}
2009
2010static void *mboxlog_next(struct seq_file *seq, void *v, loff_t *pos)
2011{
2012 ++*pos;
2013 return mboxlog_get_idx(seq, *pos);
2014}
2015
2016static void mboxlog_stop(struct seq_file *seq, void *v)
2017{
2018}
2019
2020static const struct seq_operations mboxlog_sops = {
2021 .start = mboxlog_start,
2022 .next = mboxlog_next,
2023 .stop = mboxlog_stop,
2024 .show = mboxlog_show
2025};
2026
2027DEFINE_SEQ_ATTRIBUTE(mboxlog);
2028
2029
2030
2031#define QPL 4
2032
2033static int sge_qinfo_show(struct seq_file *seq, void *v)
2034{
2035 struct adapter *adapter = seq->private;
2036 int eth_entries = DIV_ROUND_UP(adapter->sge.ethqsets, QPL);
2037 int qs, r = (uintptr_t)v - 1;
2038
2039 if (r)
2040 seq_putc(seq, '\n');
2041
2042 #define S3(fmt_spec, s, v) \
2043 do {\
2044 seq_printf(seq, "%-12s", s); \
2045 for (qs = 0; qs < n; ++qs) \
2046 seq_printf(seq, " %16" fmt_spec, v); \
2047 seq_putc(seq, '\n'); \
2048 } while (0)
2049 #define S(s, v) S3("s", s, v)
2050 #define T(s, v) S3("u", s, txq[qs].v)
2051 #define R(s, v) S3("u", s, rxq[qs].v)
2052
2053 if (r < eth_entries) {
2054 const struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[r * QPL];
2055 const struct sge_eth_txq *txq = &adapter->sge.ethtxq[r * QPL];
2056 int n = min(QPL, adapter->sge.ethqsets - QPL * r);
2057
2058 S("QType:", "Ethernet");
2059 S("Interface:",
2060 (rxq[qs].rspq.netdev
2061 ? rxq[qs].rspq.netdev->name
2062 : "N/A"));
2063 S3("d", "Port:",
2064 (rxq[qs].rspq.netdev
2065 ? ((struct port_info *)
2066 netdev_priv(rxq[qs].rspq.netdev))->port_id
2067 : -1));
2068 T("TxQ ID:", q.abs_id);
2069 T("TxQ size:", q.size);
2070 T("TxQ inuse:", q.in_use);
2071 T("TxQ PIdx:", q.pidx);
2072 T("TxQ CIdx:", q.cidx);
2073 R("RspQ ID:", rspq.abs_id);
2074 R("RspQ size:", rspq.size);
2075 R("RspQE size:", rspq.iqe_len);
2076 S3("u", "Intr delay:", qtimer_val(adapter, &rxq[qs].rspq));
2077 S3("u", "Intr pktcnt:",
2078 adapter->sge.counter_val[rxq[qs].rspq.pktcnt_idx]);
2079 R("RspQ CIdx:", rspq.cidx);
2080 R("RspQ Gen:", rspq.gen);
2081 R("FL ID:", fl.abs_id);
2082 R("FL size:", fl.size - MIN_FL_RESID);
2083 R("FL avail:", fl.avail);
2084 R("FL PIdx:", fl.pidx);
2085 R("FL CIdx:", fl.cidx);
2086 return 0;
2087 }
2088
2089 r -= eth_entries;
2090 if (r == 0) {
2091 const struct sge_rspq *evtq = &adapter->sge.fw_evtq;
2092
2093 seq_printf(seq, "%-12s %16s\n", "QType:", "FW event queue");
2094 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", evtq->abs_id);
2095 seq_printf(seq, "%-12s %16u\n", "Intr delay:",
2096 qtimer_val(adapter, evtq));
2097 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:",
2098 adapter->sge.counter_val[evtq->pktcnt_idx]);
2099 seq_printf(seq, "%-12s %16u\n", "RspQ Cidx:", evtq->cidx);
2100 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", evtq->gen);
2101 } else if (r == 1) {
2102 const struct sge_rspq *intrq = &adapter->sge.intrq;
2103
2104 seq_printf(seq, "%-12s %16s\n", "QType:", "Interrupt Queue");
2105 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", intrq->abs_id);
2106 seq_printf(seq, "%-12s %16u\n", "Intr delay:",
2107 qtimer_val(adapter, intrq));
2108 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:",
2109 adapter->sge.counter_val[intrq->pktcnt_idx]);
2110 seq_printf(seq, "%-12s %16u\n", "RspQ Cidx:", intrq->cidx);
2111 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", intrq->gen);
2112 }
2113
2114 #undef R
2115 #undef T
2116 #undef S
2117 #undef S3
2118
2119 return 0;
2120}
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130static int sge_queue_entries(const struct adapter *adapter)
2131{
2132 return DIV_ROUND_UP(adapter->sge.ethqsets, QPL) + 1 +
2133 ((adapter->flags & CXGB4VF_USING_MSI) != 0);
2134}
2135
2136static void *sge_queue_start(struct seq_file *seq, loff_t *pos)
2137{
2138 int entries = sge_queue_entries(seq->private);
2139
2140 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
2141}
2142
2143static void sge_queue_stop(struct seq_file *seq, void *v)
2144{
2145}
2146
2147static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos)
2148{
2149 int entries = sge_queue_entries(seq->private);
2150
2151 ++*pos;
2152 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
2153}
2154
2155static const struct seq_operations sge_qinfo_sops = {
2156 .start = sge_queue_start,
2157 .next = sge_queue_next,
2158 .stop = sge_queue_stop,
2159 .show = sge_qinfo_show
2160};
2161
2162DEFINE_SEQ_ATTRIBUTE(sge_qinfo);
2163
2164
2165
2166
2167#define QPL 4
2168
2169static int sge_qstats_show(struct seq_file *seq, void *v)
2170{
2171 struct adapter *adapter = seq->private;
2172 int eth_entries = DIV_ROUND_UP(adapter->sge.ethqsets, QPL);
2173 int qs, r = (uintptr_t)v - 1;
2174
2175 if (r)
2176 seq_putc(seq, '\n');
2177
2178 #define S3(fmt, s, v) \
2179 do { \
2180 seq_printf(seq, "%-16s", s); \
2181 for (qs = 0; qs < n; ++qs) \
2182 seq_printf(seq, " %8" fmt, v); \
2183 seq_putc(seq, '\n'); \
2184 } while (0)
2185 #define S(s, v) S3("s", s, v)
2186
2187 #define T3(fmt, s, v) S3(fmt, s, txq[qs].v)
2188 #define T(s, v) T3("lu", s, v)
2189
2190 #define R3(fmt, s, v) S3(fmt, s, rxq[qs].v)
2191 #define R(s, v) R3("lu", s, v)
2192
2193 if (r < eth_entries) {
2194 const struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[r * QPL];
2195 const struct sge_eth_txq *txq = &adapter->sge.ethtxq[r * QPL];
2196 int n = min(QPL, adapter->sge.ethqsets - QPL * r);
2197
2198 S("QType:", "Ethernet");
2199 S("Interface:",
2200 (rxq[qs].rspq.netdev
2201 ? rxq[qs].rspq.netdev->name
2202 : "N/A"));
2203 R3("u", "RspQNullInts:", rspq.unhandled_irqs);
2204 R("RxPackets:", stats.pkts);
2205 R("RxCSO:", stats.rx_cso);
2206 R("VLANxtract:", stats.vlan_ex);
2207 R("LROmerged:", stats.lro_merged);
2208 R("LROpackets:", stats.lro_pkts);
2209 R("RxDrops:", stats.rx_drops);
2210 T("TSO:", tso);
2211 T("TxCSO:", tx_cso);
2212 T("VLANins:", vlan_ins);
2213 T("TxQFull:", q.stops);
2214 T("TxQRestarts:", q.restarts);
2215 T("TxMapErr:", mapping_err);
2216 R("FLAllocErr:", fl.alloc_failed);
2217 R("FLLrgAlcErr:", fl.large_alloc_failed);
2218 R("FLStarving:", fl.starving);
2219 return 0;
2220 }
2221
2222 r -= eth_entries;
2223 if (r == 0) {
2224 const struct sge_rspq *evtq = &adapter->sge.fw_evtq;
2225
2226 seq_printf(seq, "%-8s %16s\n", "QType:", "FW event queue");
2227 seq_printf(seq, "%-16s %8u\n", "RspQNullInts:",
2228 evtq->unhandled_irqs);
2229 seq_printf(seq, "%-16s %8u\n", "RspQ CIdx:", evtq->cidx);
2230 seq_printf(seq, "%-16s %8u\n", "RspQ Gen:", evtq->gen);
2231 } else if (r == 1) {
2232 const struct sge_rspq *intrq = &adapter->sge.intrq;
2233
2234 seq_printf(seq, "%-8s %16s\n", "QType:", "Interrupt Queue");
2235 seq_printf(seq, "%-16s %8u\n", "RspQNullInts:",
2236 intrq->unhandled_irqs);
2237 seq_printf(seq, "%-16s %8u\n", "RspQ CIdx:", intrq->cidx);
2238 seq_printf(seq, "%-16s %8u\n", "RspQ Gen:", intrq->gen);
2239 }
2240
2241 #undef R
2242 #undef T
2243 #undef S
2244 #undef R3
2245 #undef T3
2246 #undef S3
2247
2248 return 0;
2249}
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259static int sge_qstats_entries(const struct adapter *adapter)
2260{
2261 return DIV_ROUND_UP(adapter->sge.ethqsets, QPL) + 1 +
2262 ((adapter->flags & CXGB4VF_USING_MSI) != 0);
2263}
2264
2265static void *sge_qstats_start(struct seq_file *seq, loff_t *pos)
2266{
2267 int entries = sge_qstats_entries(seq->private);
2268
2269 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
2270}
2271
2272static void sge_qstats_stop(struct seq_file *seq, void *v)
2273{
2274}
2275
2276static void *sge_qstats_next(struct seq_file *seq, void *v, loff_t *pos)
2277{
2278 int entries = sge_qstats_entries(seq->private);
2279
2280 (*pos)++;
2281 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
2282}
2283
2284static const struct seq_operations sge_qstats_sops = {
2285 .start = sge_qstats_start,
2286 .next = sge_qstats_next,
2287 .stop = sge_qstats_stop,
2288 .show = sge_qstats_show
2289};
2290
2291DEFINE_SEQ_ATTRIBUTE(sge_qstats);
2292
2293
2294
2295
2296static int resources_show(struct seq_file *seq, void *v)
2297{
2298 struct adapter *adapter = seq->private;
2299 struct vf_resources *vfres = &adapter->params.vfres;
2300
2301 #define S(desc, fmt, var) \
2302 seq_printf(seq, "%-60s " fmt "\n", \
2303 desc " (" #var "):", vfres->var)
2304
2305 S("Virtual Interfaces", "%d", nvi);
2306 S("Egress Queues", "%d", neq);
2307 S("Ethernet Control", "%d", nethctrl);
2308 S("Ingress Queues/w Free Lists/Interrupts", "%d", niqflint);
2309 S("Ingress Queues", "%d", niq);
2310 S("Traffic Class", "%d", tc);
2311 S("Port Access Rights Mask", "%#x", pmask);
2312 S("MAC Address Filters", "%d", nexactf);
2313 S("Firmware Command Read Capabilities", "%#x", r_caps);
2314 S("Firmware Command Write/Execute Capabilities", "%#x", wx_caps);
2315
2316 #undef S
2317
2318 return 0;
2319}
2320DEFINE_SHOW_ATTRIBUTE(resources);
2321
2322
2323
2324
2325static int interfaces_show(struct seq_file *seq, void *v)
2326{
2327 if (v == SEQ_START_TOKEN) {
2328 seq_puts(seq, "Interface Port VIID\n");
2329 } else {
2330 struct adapter *adapter = seq->private;
2331 int pidx = (uintptr_t)v - 2;
2332 struct net_device *dev = adapter->port[pidx];
2333 struct port_info *pi = netdev_priv(dev);
2334
2335 seq_printf(seq, "%9s %4d %#5x\n",
2336 dev->name, pi->port_id, pi->viid);
2337 }
2338 return 0;
2339}
2340
2341static inline void *interfaces_get_idx(struct adapter *adapter, loff_t pos)
2342{
2343 return pos <= adapter->params.nports
2344 ? (void *)(uintptr_t)(pos + 1)
2345 : NULL;
2346}
2347
2348static void *interfaces_start(struct seq_file *seq, loff_t *pos)
2349{
2350 return *pos
2351 ? interfaces_get_idx(seq->private, *pos)
2352 : SEQ_START_TOKEN;
2353}
2354
2355static void *interfaces_next(struct seq_file *seq, void *v, loff_t *pos)
2356{
2357 (*pos)++;
2358 return interfaces_get_idx(seq->private, *pos);
2359}
2360
2361static void interfaces_stop(struct seq_file *seq, void *v)
2362{
2363}
2364
2365static const struct seq_operations interfaces_sops = {
2366 .start = interfaces_start,
2367 .next = interfaces_next,
2368 .stop = interfaces_stop,
2369 .show = interfaces_show
2370};
2371
2372DEFINE_SEQ_ATTRIBUTE(interfaces);
2373
2374
2375
2376
2377struct cxgb4vf_debugfs_entry {
2378 const char *name;
2379 umode_t mode;
2380 const struct file_operations *fops;
2381};
2382
2383static struct cxgb4vf_debugfs_entry debugfs_files[] = {
2384 { "mboxlog", 0444, &mboxlog_fops },
2385 { "sge_qinfo", 0444, &sge_qinfo_fops },
2386 { "sge_qstats", 0444, &sge_qstats_fops },
2387 { "resources", 0444, &resources_fops },
2388 { "interfaces", 0444, &interfaces_fops },
2389};
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400static int setup_debugfs(struct adapter *adapter)
2401{
2402 int i;
2403
2404 BUG_ON(IS_ERR_OR_NULL(adapter->debugfs_root));
2405
2406
2407
2408
2409 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
2410 debugfs_create_file(debugfs_files[i].name,
2411 debugfs_files[i].mode,
2412 adapter->debugfs_root, adapter,
2413 debugfs_files[i].fops);
2414
2415 return 0;
2416}
2417
2418
2419
2420
2421
2422static void cleanup_debugfs(struct adapter *adapter)
2423{
2424 BUG_ON(IS_ERR_OR_NULL(adapter->debugfs_root));
2425
2426
2427
2428
2429
2430
2431
2432
2433}
2434
2435
2436
2437
2438
2439static void size_nports_qsets(struct adapter *adapter)
2440{
2441 struct vf_resources *vfres = &adapter->params.vfres;
2442 unsigned int ethqsets, pmask_nports;
2443
2444
2445
2446
2447 adapter->params.nports = vfres->nvi;
2448 if (adapter->params.nports > MAX_NPORTS) {
2449 dev_warn(adapter->pdev_dev, "only using %d of %d maximum"
2450 " allowed virtual interfaces\n", MAX_NPORTS,
2451 adapter->params.nports);
2452 adapter->params.nports = MAX_NPORTS;
2453 }
2454
2455
2456
2457
2458
2459
2460 pmask_nports = hweight32(adapter->params.vfres.pmask);
2461 if (pmask_nports < adapter->params.nports) {
2462 dev_warn(adapter->pdev_dev, "only using %d of %d provisioned"
2463 " virtual interfaces; limited by Port Access Rights"
2464 " mask %#x\n", pmask_nports, adapter->params.nports,
2465 adapter->params.vfres.pmask);
2466 adapter->params.nports = pmask_nports;
2467 }
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485 ethqsets = vfres->niqflint - 1 - (msi == MSI_MSI);
2486 if (vfres->nethctrl != ethqsets)
2487 ethqsets = min(vfres->nethctrl, ethqsets);
2488 if (vfres->neq < ethqsets*2)
2489 ethqsets = vfres->neq/2;
2490 if (ethqsets > MAX_ETH_QSETS)
2491 ethqsets = MAX_ETH_QSETS;
2492 adapter->sge.max_ethqsets = ethqsets;
2493
2494 if (adapter->sge.max_ethqsets < adapter->params.nports) {
2495 dev_warn(adapter->pdev_dev, "only using %d of %d available"
2496 " virtual interfaces (too few Queue Sets)\n",
2497 adapter->sge.max_ethqsets, adapter->params.nports);
2498 adapter->params.nports = adapter->sge.max_ethqsets;
2499 }
2500}
2501
2502
2503
2504
2505
2506
2507static int adap_init0(struct adapter *adapter)
2508{
2509 struct sge_params *sge_params = &adapter->params.sge;
2510 struct sge *s = &adapter->sge;
2511 int err;
2512 u32 param, val = 0;
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524 err = t4vf_fw_reset(adapter);
2525 if (err < 0) {
2526 dev_err(adapter->pdev_dev, "FW reset failed: err=%d\n", err);
2527 return err;
2528 }
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538 err = t4vf_get_dev_params(adapter);
2539 if (err) {
2540 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2541 " device parameters: err=%d\n", err);
2542 return err;
2543 }
2544 err = t4vf_get_vpd_params(adapter);
2545 if (err) {
2546 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2547 " VPD parameters: err=%d\n", err);
2548 return err;
2549 }
2550 err = t4vf_get_sge_params(adapter);
2551 if (err) {
2552 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2553 " SGE parameters: err=%d\n", err);
2554 return err;
2555 }
2556 err = t4vf_get_rss_glb_config(adapter);
2557 if (err) {
2558 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2559 " RSS parameters: err=%d\n", err);
2560 return err;
2561 }
2562 if (adapter->params.rss.mode !=
2563 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
2564 dev_err(adapter->pdev_dev, "unable to operate with global RSS"
2565 " mode %d\n", adapter->params.rss.mode);
2566 return -EINVAL;
2567 }
2568 err = t4vf_sge_init(adapter);
2569 if (err) {
2570 dev_err(adapter->pdev_dev, "unable to use adapter parameters:"
2571 " err=%d\n", err);
2572 return err;
2573 }
2574
2575
2576
2577
2578
2579
2580 param = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2581 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP);
2582 val = 1;
2583 (void) t4vf_set_params(adapter, 1, ¶m, &val);
2584
2585
2586
2587
2588
2589 s->timer_val[0] = core_ticks_to_us(adapter,
2590 TIMERVALUE0_G(sge_params->sge_timer_value_0_and_1));
2591 s->timer_val[1] = core_ticks_to_us(adapter,
2592 TIMERVALUE1_G(sge_params->sge_timer_value_0_and_1));
2593 s->timer_val[2] = core_ticks_to_us(adapter,
2594 TIMERVALUE0_G(sge_params->sge_timer_value_2_and_3));
2595 s->timer_val[3] = core_ticks_to_us(adapter,
2596 TIMERVALUE1_G(sge_params->sge_timer_value_2_and_3));
2597 s->timer_val[4] = core_ticks_to_us(adapter,
2598 TIMERVALUE0_G(sge_params->sge_timer_value_4_and_5));
2599 s->timer_val[5] = core_ticks_to_us(adapter,
2600 TIMERVALUE1_G(sge_params->sge_timer_value_4_and_5));
2601
2602 s->counter_val[0] = THRESHOLD_0_G(sge_params->sge_ingress_rx_threshold);
2603 s->counter_val[1] = THRESHOLD_1_G(sge_params->sge_ingress_rx_threshold);
2604 s->counter_val[2] = THRESHOLD_2_G(sge_params->sge_ingress_rx_threshold);
2605 s->counter_val[3] = THRESHOLD_3_G(sge_params->sge_ingress_rx_threshold);
2606
2607
2608
2609
2610
2611
2612 err = t4vf_get_vfres(adapter);
2613 if (err) {
2614 dev_err(adapter->pdev_dev, "unable to get virtual interface"
2615 " resources: err=%d\n", err);
2616 return err;
2617 }
2618
2619
2620 if (adapter->params.vfres.pmask == 0) {
2621 dev_err(adapter->pdev_dev, "no port access configured\n"
2622 "usable!\n");
2623 return -EINVAL;
2624 }
2625 if (adapter->params.vfres.nvi == 0) {
2626 dev_err(adapter->pdev_dev, "no virtual interfaces configured/"
2627 "usable!\n");
2628 return -EINVAL;
2629 }
2630
2631
2632
2633
2634 size_nports_qsets(adapter);
2635
2636 adapter->flags |= CXGB4VF_FW_OK;
2637 return 0;
2638}
2639
2640static inline void init_rspq(struct sge_rspq *rspq, u8 timer_idx,
2641 u8 pkt_cnt_idx, unsigned int size,
2642 unsigned int iqe_size)
2643{
2644 rspq->intr_params = (QINTR_TIMER_IDX_V(timer_idx) |
2645 (pkt_cnt_idx < SGE_NCOUNTERS ?
2646 QINTR_CNT_EN_F : 0));
2647 rspq->pktcnt_idx = (pkt_cnt_idx < SGE_NCOUNTERS
2648 ? pkt_cnt_idx
2649 : 0);
2650 rspq->iqe_len = iqe_size;
2651 rspq->size = size;
2652}
2653
2654
2655
2656
2657
2658
2659
2660static void cfg_queues(struct adapter *adapter)
2661{
2662 struct sge *s = &adapter->sge;
2663 int q10g, n10g, qidx, pidx, qs;
2664 size_t iqe_size;
2665
2666
2667
2668
2669
2670
2671 BUG_ON((adapter->flags &
2672 (CXGB4VF_USING_MSIX | CXGB4VF_USING_MSI)) == 0);
2673
2674
2675
2676
2677 n10g = 0;
2678 for_each_port(adapter, pidx)
2679 n10g += is_x_10g_port(&adap2pinfo(adapter, pidx)->link_cfg);
2680
2681
2682
2683
2684
2685 if (n10g == 0)
2686 q10g = 0;
2687 else {
2688 int n1g = (adapter->params.nports - n10g);
2689 q10g = (adapter->sge.max_ethqsets - n1g) / n10g;
2690 if (q10g > num_online_cpus())
2691 q10g = num_online_cpus();
2692 }
2693
2694
2695
2696
2697
2698
2699 qidx = 0;
2700 for_each_port(adapter, pidx) {
2701 struct port_info *pi = adap2pinfo(adapter, pidx);
2702
2703 pi->first_qset = qidx;
2704 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
2705 qidx += pi->nqsets;
2706 }
2707 s->ethqsets = qidx;
2708
2709
2710
2711
2712
2713
2714 iqe_size = 64;
2715
2716
2717
2718
2719
2720 for (qs = 0; qs < s->max_ethqsets; qs++) {
2721 struct sge_eth_rxq *rxq = &s->ethrxq[qs];
2722 struct sge_eth_txq *txq = &s->ethtxq[qs];
2723
2724 init_rspq(&rxq->rspq, 0, 0, 1024, iqe_size);
2725 rxq->fl.size = 72;
2726 txq->q.size = 1024;
2727 }
2728
2729
2730
2731
2732
2733 init_rspq(&s->fw_evtq, SGE_TIMER_RSTRT_CNTR, 0, 512, iqe_size);
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748 init_rspq(&s->intrq, SGE_TIMER_RSTRT_CNTR, 0, MSIX_ENTRIES + 1,
2749 iqe_size);
2750}
2751
2752
2753
2754
2755
2756static void reduce_ethqs(struct adapter *adapter, int n)
2757{
2758 int i;
2759 struct port_info *pi;
2760
2761
2762
2763
2764
2765 BUG_ON(n < adapter->params.nports);
2766 while (n < adapter->sge.ethqsets)
2767 for_each_port(adapter, i) {
2768 pi = adap2pinfo(adapter, i);
2769 if (pi->nqsets > 1) {
2770 pi->nqsets--;
2771 adapter->sge.ethqsets--;
2772 if (adapter->sge.ethqsets <= n)
2773 break;
2774 }
2775 }
2776
2777
2778
2779
2780 n = 0;
2781 for_each_port(adapter, i) {
2782 pi = adap2pinfo(adapter, i);
2783 pi->first_qset = n;
2784 n += pi->nqsets;
2785 }
2786}
2787
2788
2789
2790
2791
2792
2793
2794
2795static int enable_msix(struct adapter *adapter)
2796{
2797 int i, want, need, nqsets;
2798 struct msix_entry entries[MSIX_ENTRIES];
2799 struct sge *s = &adapter->sge;
2800
2801 for (i = 0; i < MSIX_ENTRIES; ++i)
2802 entries[i].entry = i;
2803
2804
2805
2806
2807
2808
2809
2810
2811 want = s->max_ethqsets + MSIX_EXTRAS;
2812 need = adapter->params.nports + MSIX_EXTRAS;
2813
2814 want = pci_enable_msix_range(adapter->pdev, entries, need, want);
2815 if (want < 0)
2816 return want;
2817
2818 nqsets = want - MSIX_EXTRAS;
2819 if (nqsets < s->max_ethqsets) {
2820 dev_warn(adapter->pdev_dev, "only enough MSI-X vectors"
2821 " for %d Queue Sets\n", nqsets);
2822 s->max_ethqsets = nqsets;
2823 if (nqsets < s->ethqsets)
2824 reduce_ethqs(adapter, nqsets);
2825 }
2826 for (i = 0; i < want; ++i)
2827 adapter->msix_info[i].vec = entries[i].vector;
2828
2829 return 0;
2830}
2831
2832static const struct net_device_ops cxgb4vf_netdev_ops = {
2833 .ndo_open = cxgb4vf_open,
2834 .ndo_stop = cxgb4vf_stop,
2835 .ndo_start_xmit = t4vf_eth_xmit,
2836 .ndo_get_stats = cxgb4vf_get_stats,
2837 .ndo_set_rx_mode = cxgb4vf_set_rxmode,
2838 .ndo_set_mac_address = cxgb4vf_set_mac_addr,
2839 .ndo_validate_addr = eth_validate_addr,
2840 .ndo_do_ioctl = cxgb4vf_do_ioctl,
2841 .ndo_change_mtu = cxgb4vf_change_mtu,
2842 .ndo_fix_features = cxgb4vf_fix_features,
2843 .ndo_set_features = cxgb4vf_set_features,
2844#ifdef CONFIG_NET_POLL_CONTROLLER
2845 .ndo_poll_controller = cxgb4vf_poll_controller,
2846#endif
2847};
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859static unsigned int cxgb4vf_get_port_mask(struct adapter *adapter)
2860{
2861 unsigned int naddr = 1, pidx = 0;
2862 unsigned int pmask, rmask = 0;
2863 u8 mac[ETH_ALEN];
2864 int err;
2865
2866 pmask = adapter->params.vfres.pmask;
2867 while (pmask) {
2868 if (pmask & 1) {
2869 err = t4vf_get_vf_mac_acl(adapter, pidx, &naddr, mac);
2870 if (!err && !is_zero_ether_addr(mac))
2871 rmask |= (1 << pidx);
2872 }
2873 pmask >>= 1;
2874 pidx++;
2875 }
2876 if (!rmask)
2877 rmask = adapter->params.vfres.pmask;
2878
2879 return rmask;
2880}
2881
2882
2883
2884
2885
2886
2887static int cxgb4vf_pci_probe(struct pci_dev *pdev,
2888 const struct pci_device_id *ent)
2889{
2890 struct adapter *adapter;
2891 struct net_device *netdev;
2892 struct port_info *pi;
2893 unsigned int pmask;
2894 int pci_using_dac;
2895 int err, pidx;
2896
2897
2898
2899
2900 err = pci_enable_device(pdev);
2901 if (err) {
2902 dev_err(&pdev->dev, "cannot enable PCI device\n");
2903 return err;
2904 }
2905
2906
2907
2908
2909
2910 err = pci_request_regions(pdev, KBUILD_MODNAME);
2911 if (err) {
2912 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2913 goto err_disable_device;
2914 }
2915
2916
2917
2918
2919
2920 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2921 if (err == 0) {
2922 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2923 if (err) {
2924 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for"
2925 " coherent allocations\n");
2926 goto err_release_regions;
2927 }
2928 pci_using_dac = 1;
2929 } else {
2930 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2931 if (err != 0) {
2932 dev_err(&pdev->dev, "no usable DMA configuration\n");
2933 goto err_release_regions;
2934 }
2935 pci_using_dac = 0;
2936 }
2937
2938
2939
2940
2941 pci_set_master(pdev);
2942
2943
2944
2945
2946 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
2947 if (!adapter) {
2948 err = -ENOMEM;
2949 goto err_release_regions;
2950 }
2951 pci_set_drvdata(pdev, adapter);
2952 adapter->pdev = pdev;
2953 adapter->pdev_dev = &pdev->dev;
2954
2955 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
2956 (sizeof(struct mbox_cmd) *
2957 T4VF_OS_LOG_MBOX_CMDS),
2958 GFP_KERNEL);
2959 if (!adapter->mbox_log) {
2960 err = -ENOMEM;
2961 goto err_free_adapter;
2962 }
2963 adapter->mbox_log->size = T4VF_OS_LOG_MBOX_CMDS;
2964
2965
2966
2967
2968 spin_lock_init(&adapter->stats_lock);
2969 spin_lock_init(&adapter->mbox_lock);
2970 INIT_LIST_HEAD(&adapter->mlist.list);
2971
2972
2973
2974
2975 adapter->regs = pci_ioremap_bar(pdev, 0);
2976 if (!adapter->regs) {
2977 dev_err(&pdev->dev, "cannot map device registers\n");
2978 err = -ENOMEM;
2979 goto err_free_adapter;
2980 }
2981
2982
2983
2984 err = t4vf_prep_adapter(adapter);
2985 if (err) {
2986 dev_err(adapter->pdev_dev, "device didn't become ready:"
2987 " err=%d\n", err);
2988 goto err_unmap_bar0;
2989 }
2990
2991
2992
2993
2994 if (!is_t4(adapter->params.chip)) {
2995 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
2996 pci_resource_len(pdev, 2));
2997 if (!adapter->bar2) {
2998 dev_err(adapter->pdev_dev, "cannot map BAR2 doorbells\n");
2999 err = -ENOMEM;
3000 goto err_unmap_bar0;
3001 }
3002 }
3003
3004
3005
3006 adapter->name = pci_name(pdev);
3007 adapter->msg_enable = DFLT_MSG_ENABLE;
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023 if (!pcie_relaxed_ordering_enabled(pdev))
3024 adapter->flags |= CXGB4VF_ROOT_NO_RELAXED_ORDERING;
3025
3026 err = adap_init0(adapter);
3027 if (err)
3028 dev_err(&pdev->dev,
3029 "Adapter initialization failed, error %d. Continuing in debug mode\n",
3030 err);
3031
3032
3033 INIT_LIST_HEAD(&adapter->mac_hlist);
3034
3035
3036
3037
3038 pmask = cxgb4vf_get_port_mask(adapter);
3039 for_each_port(adapter, pidx) {
3040 int port_id, viid;
3041 u8 mac[ETH_ALEN];
3042 unsigned int naddr = 1;
3043
3044
3045
3046
3047
3048
3049
3050 if (pmask == 0)
3051 break;
3052 port_id = ffs(pmask) - 1;
3053 pmask &= ~(1 << port_id);
3054
3055
3056
3057
3058 netdev = alloc_etherdev_mq(sizeof(struct port_info),
3059 MAX_PORT_QSETS);
3060 if (netdev == NULL) {
3061 err = -ENOMEM;
3062 goto err_free_dev;
3063 }
3064 adapter->port[pidx] = netdev;
3065 SET_NETDEV_DEV(netdev, &pdev->dev);
3066 pi = netdev_priv(netdev);
3067 pi->adapter = adapter;
3068 pi->pidx = pidx;
3069 pi->port_id = port_id;
3070
3071
3072
3073
3074
3075 pi->xact_addr_filt = -1;
3076 netdev->irq = pdev->irq;
3077
3078 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | NETIF_F_GRO |
3079 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
3080 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3081 netdev->features = netdev->hw_features;
3082 if (pci_using_dac)
3083 netdev->features |= NETIF_F_HIGHDMA;
3084 netdev->vlan_features = netdev->features & VLAN_FEAT;
3085
3086 netdev->priv_flags |= IFF_UNICAST_FLT;
3087 netdev->min_mtu = 81;
3088 netdev->max_mtu = ETH_MAX_MTU;
3089
3090 netdev->netdev_ops = &cxgb4vf_netdev_ops;
3091 netdev->ethtool_ops = &cxgb4vf_ethtool_ops;
3092 netdev->dev_port = pi->port_id;
3093
3094
3095
3096
3097
3098 if (!(adapter->flags & CXGB4VF_FW_OK))
3099 continue;
3100
3101 viid = t4vf_alloc_vi(adapter, port_id);
3102 if (viid < 0) {
3103 dev_err(&pdev->dev,
3104 "cannot allocate VI for port %d: err=%d\n",
3105 port_id, viid);
3106 err = viid;
3107 goto err_free_dev;
3108 }
3109 pi->viid = viid;
3110
3111
3112
3113
3114 err = t4vf_port_init(adapter, pidx);
3115 if (err) {
3116 dev_err(&pdev->dev, "cannot initialize port %d\n",
3117 pidx);
3118 goto err_free_dev;
3119 }
3120
3121 err = t4vf_get_vf_mac_acl(adapter, port_id, &naddr, mac);
3122 if (err) {
3123 dev_err(&pdev->dev,
3124 "unable to determine MAC ACL address, "
3125 "continuing anyway.. (status %d)\n", err);
3126 } else if (naddr && adapter->params.vfres.nvi == 1) {
3127 struct sockaddr addr;
3128
3129 ether_addr_copy(addr.sa_data, mac);
3130 err = cxgb4vf_set_mac_addr(netdev, &addr);
3131 if (err) {
3132 dev_err(&pdev->dev,
3133 "unable to set MAC address %pM\n",
3134 mac);
3135 goto err_free_dev;
3136 }
3137 dev_info(&pdev->dev,
3138 "Using assigned MAC ACL: %pM\n", mac);
3139 }
3140 }
3141
3142
3143
3144
3145
3146
3147 if (msi == MSI_MSIX && enable_msix(adapter) == 0)
3148 adapter->flags |= CXGB4VF_USING_MSIX;
3149 else {
3150 if (msi == MSI_MSIX) {
3151 dev_info(adapter->pdev_dev,
3152 "Unable to use MSI-X Interrupts; falling "
3153 "back to MSI Interrupts\n");
3154
3155
3156
3157
3158
3159 msi = MSI_MSI;
3160 size_nports_qsets(adapter);
3161 }
3162 err = pci_enable_msi(pdev);
3163 if (err) {
3164 dev_err(&pdev->dev, "Unable to allocate MSI Interrupts;"
3165 " err=%d\n", err);
3166 goto err_free_dev;
3167 }
3168 adapter->flags |= CXGB4VF_USING_MSI;
3169 }
3170
3171
3172
3173
3174 cfg_queues(adapter);
3175
3176
3177
3178
3179
3180
3181
3182 for_each_port(adapter, pidx) {
3183 struct port_info *pi = netdev_priv(adapter->port[pidx]);
3184 netdev = adapter->port[pidx];
3185 if (netdev == NULL)
3186 continue;
3187
3188 netif_set_real_num_tx_queues(netdev, pi->nqsets);
3189 netif_set_real_num_rx_queues(netdev, pi->nqsets);
3190
3191 err = register_netdev(netdev);
3192 if (err) {
3193 dev_warn(&pdev->dev, "cannot register net device %s,"
3194 " skipping\n", netdev->name);
3195 continue;
3196 }
3197
3198 netif_carrier_off(netdev);
3199 set_bit(pidx, &adapter->registered_device_map);
3200 }
3201 if (adapter->registered_device_map == 0) {
3202 dev_err(&pdev->dev, "could not register any net devices\n");
3203 goto err_disable_interrupts;
3204 }
3205
3206
3207
3208
3209 if (!IS_ERR_OR_NULL(cxgb4vf_debugfs_root)) {
3210 adapter->debugfs_root =
3211 debugfs_create_dir(pci_name(pdev),
3212 cxgb4vf_debugfs_root);
3213 setup_debugfs(adapter);
3214 }
3215
3216
3217
3218
3219
3220 for_each_port(adapter, pidx) {
3221 dev_info(adapter->pdev_dev, "%s: Chelsio VF NIC PCIe %s\n",
3222 adapter->port[pidx]->name,
3223 (adapter->flags & CXGB4VF_USING_MSIX) ? "MSI-X" :
3224 (adapter->flags & CXGB4VF_USING_MSI) ? "MSI" : "");
3225 }
3226
3227
3228
3229
3230 return 0;
3231
3232
3233
3234
3235
3236err_disable_interrupts:
3237 if (adapter->flags & CXGB4VF_USING_MSIX) {
3238 pci_disable_msix(adapter->pdev);
3239 adapter->flags &= ~CXGB4VF_USING_MSIX;
3240 } else if (adapter->flags & CXGB4VF_USING_MSI) {
3241 pci_disable_msi(adapter->pdev);
3242 adapter->flags &= ~CXGB4VF_USING_MSI;
3243 }
3244
3245err_free_dev:
3246 for_each_port(adapter, pidx) {
3247 netdev = adapter->port[pidx];
3248 if (netdev == NULL)
3249 continue;
3250 pi = netdev_priv(netdev);
3251 if (pi->viid)
3252 t4vf_free_vi(adapter, pi->viid);
3253 if (test_bit(pidx, &adapter->registered_device_map))
3254 unregister_netdev(netdev);
3255 free_netdev(netdev);
3256 }
3257
3258 if (!is_t4(adapter->params.chip))
3259 iounmap(adapter->bar2);
3260
3261err_unmap_bar0:
3262 iounmap(adapter->regs);
3263
3264err_free_adapter:
3265 kfree(adapter->mbox_log);
3266 kfree(adapter);
3267
3268err_release_regions:
3269 pci_release_regions(pdev);
3270 pci_clear_master(pdev);
3271
3272err_disable_device:
3273 pci_disable_device(pdev);
3274
3275 return err;
3276}
3277
3278
3279
3280
3281
3282
3283static void cxgb4vf_pci_remove(struct pci_dev *pdev)
3284{
3285 struct adapter *adapter = pci_get_drvdata(pdev);
3286 struct hash_mac_addr *entry, *tmp;
3287
3288
3289
3290
3291 if (adapter) {
3292 int pidx;
3293
3294
3295
3296
3297
3298 for_each_port(adapter, pidx)
3299 if (test_bit(pidx, &adapter->registered_device_map))
3300 unregister_netdev(adapter->port[pidx]);
3301 t4vf_sge_stop(adapter);
3302 if (adapter->flags & CXGB4VF_USING_MSIX) {
3303 pci_disable_msix(adapter->pdev);
3304 adapter->flags &= ~CXGB4VF_USING_MSIX;
3305 } else if (adapter->flags & CXGB4VF_USING_MSI) {
3306 pci_disable_msi(adapter->pdev);
3307 adapter->flags &= ~CXGB4VF_USING_MSI;
3308 }
3309
3310
3311
3312
3313 if (!IS_ERR_OR_NULL(adapter->debugfs_root)) {
3314 cleanup_debugfs(adapter);
3315 debugfs_remove_recursive(adapter->debugfs_root);
3316 }
3317
3318
3319
3320
3321 t4vf_free_sge_resources(adapter);
3322 for_each_port(adapter, pidx) {
3323 struct net_device *netdev = adapter->port[pidx];
3324 struct port_info *pi;
3325
3326 if (netdev == NULL)
3327 continue;
3328
3329 pi = netdev_priv(netdev);
3330 if (pi->viid)
3331 t4vf_free_vi(adapter, pi->viid);
3332 free_netdev(netdev);
3333 }
3334 iounmap(adapter->regs);
3335 if (!is_t4(adapter->params.chip))
3336 iounmap(adapter->bar2);
3337 kfree(adapter->mbox_log);
3338 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
3339 list) {
3340 list_del(&entry->list);
3341 kfree(entry);
3342 }
3343 kfree(adapter);
3344 }
3345
3346
3347
3348
3349 pci_disable_device(pdev);
3350 pci_clear_master(pdev);
3351 pci_release_regions(pdev);
3352}
3353
3354
3355
3356
3357
3358static void cxgb4vf_pci_shutdown(struct pci_dev *pdev)
3359{
3360 struct adapter *adapter;
3361 int pidx;
3362
3363 adapter = pci_get_drvdata(pdev);
3364 if (!adapter)
3365 return;
3366
3367
3368
3369
3370
3371 for_each_port(adapter, pidx)
3372 if (test_bit(pidx, &adapter->registered_device_map))
3373 unregister_netdev(adapter->port[pidx]);
3374
3375
3376
3377
3378 t4vf_sge_stop(adapter);
3379 if (adapter->flags & CXGB4VF_USING_MSIX) {
3380 pci_disable_msix(adapter->pdev);
3381 adapter->flags &= ~CXGB4VF_USING_MSIX;
3382 } else if (adapter->flags & CXGB4VF_USING_MSI) {
3383 pci_disable_msi(adapter->pdev);
3384 adapter->flags &= ~CXGB4VF_USING_MSI;
3385 }
3386
3387
3388
3389
3390
3391 t4vf_free_sge_resources(adapter);
3392 pci_set_drvdata(pdev, NULL);
3393}
3394
3395
3396
3397#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
3398 static const struct pci_device_id cxgb4vf_pci_tbl[] = {
3399#define CH_PCI_DEVICE_ID_FUNCTION 0x8
3400
3401#define CH_PCI_ID_TABLE_ENTRY(devid) \
3402 { PCI_VDEVICE(CHELSIO, (devid)), 0 }
3403
3404#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END { 0, } }
3405
3406#include "../cxgb4/t4_pci_id_tbl.h"
3407
3408MODULE_DESCRIPTION(DRV_DESC);
3409MODULE_AUTHOR("Chelsio Communications");
3410MODULE_LICENSE("Dual BSD/GPL");
3411MODULE_DEVICE_TABLE(pci, cxgb4vf_pci_tbl);
3412
3413static struct pci_driver cxgb4vf_driver = {
3414 .name = KBUILD_MODNAME,
3415 .id_table = cxgb4vf_pci_tbl,
3416 .probe = cxgb4vf_pci_probe,
3417 .remove = cxgb4vf_pci_remove,
3418 .shutdown = cxgb4vf_pci_shutdown,
3419};
3420
3421
3422
3423
3424static int __init cxgb4vf_module_init(void)
3425{
3426 int ret;
3427
3428
3429
3430
3431 if (msi != MSI_MSIX && msi != MSI_MSI) {
3432 pr_warn("bad module parameter msi=%d; must be %d (MSI-X or MSI) or %d (MSI)\n",
3433 msi, MSI_MSIX, MSI_MSI);
3434 return -EINVAL;
3435 }
3436
3437
3438 cxgb4vf_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
3439
3440 ret = pci_register_driver(&cxgb4vf_driver);
3441 if (ret < 0)
3442 debugfs_remove(cxgb4vf_debugfs_root);
3443 return ret;
3444}
3445
3446
3447
3448
3449static void __exit cxgb4vf_module_exit(void)
3450{
3451 pci_unregister_driver(&cxgb4vf_driver);
3452 debugfs_remove(cxgb4vf_debugfs_root);
3453}
3454
3455module_init(cxgb4vf_module_init);
3456module_exit(cxgb4vf_module_exit);
3457