linux/drivers/net/ethernet/freescale/fec_ptp.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
   4 *
   5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
   6 */
   7
   8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10#include <linux/module.h>
  11#include <linux/kernel.h>
  12#include <linux/string.h>
  13#include <linux/ptrace.h>
  14#include <linux/errno.h>
  15#include <linux/ioport.h>
  16#include <linux/slab.h>
  17#include <linux/interrupt.h>
  18#include <linux/pci.h>
  19#include <linux/delay.h>
  20#include <linux/netdevice.h>
  21#include <linux/etherdevice.h>
  22#include <linux/skbuff.h>
  23#include <linux/spinlock.h>
  24#include <linux/workqueue.h>
  25#include <linux/bitops.h>
  26#include <linux/io.h>
  27#include <linux/irq.h>
  28#include <linux/clk.h>
  29#include <linux/platform_device.h>
  30#include <linux/phy.h>
  31#include <linux/fec.h>
  32#include <linux/of.h>
  33#include <linux/of_device.h>
  34#include <linux/of_gpio.h>
  35#include <linux/of_net.h>
  36
  37#include "fec.h"
  38
  39/* FEC 1588 register bits */
  40#define FEC_T_CTRL_SLAVE                0x00002000
  41#define FEC_T_CTRL_CAPTURE              0x00000800
  42#define FEC_T_CTRL_RESTART              0x00000200
  43#define FEC_T_CTRL_PERIOD_RST           0x00000030
  44#define FEC_T_CTRL_PERIOD_EN            0x00000010
  45#define FEC_T_CTRL_ENABLE               0x00000001
  46
  47#define FEC_T_INC_MASK                  0x0000007f
  48#define FEC_T_INC_OFFSET                0
  49#define FEC_T_INC_CORR_MASK             0x00007f00
  50#define FEC_T_INC_CORR_OFFSET           8
  51
  52#define FEC_T_CTRL_PINPER               0x00000080
  53#define FEC_T_TF0_MASK                  0x00000001
  54#define FEC_T_TF0_OFFSET                0
  55#define FEC_T_TF1_MASK                  0x00000002
  56#define FEC_T_TF1_OFFSET                1
  57#define FEC_T_TF2_MASK                  0x00000004
  58#define FEC_T_TF2_OFFSET                2
  59#define FEC_T_TF3_MASK                  0x00000008
  60#define FEC_T_TF3_OFFSET                3
  61#define FEC_T_TDRE_MASK                 0x00000001
  62#define FEC_T_TDRE_OFFSET               0
  63#define FEC_T_TMODE_MASK                0x0000003C
  64#define FEC_T_TMODE_OFFSET              2
  65#define FEC_T_TIE_MASK                  0x00000040
  66#define FEC_T_TIE_OFFSET                6
  67#define FEC_T_TF_MASK                   0x00000080
  68#define FEC_T_TF_OFFSET                 7
  69
  70#define FEC_ATIME_CTRL          0x400
  71#define FEC_ATIME               0x404
  72#define FEC_ATIME_EVT_OFFSET    0x408
  73#define FEC_ATIME_EVT_PERIOD    0x40c
  74#define FEC_ATIME_CORR          0x410
  75#define FEC_ATIME_INC           0x414
  76#define FEC_TS_TIMESTAMP        0x418
  77
  78#define FEC_TGSR                0x604
  79#define FEC_TCSR(n)             (0x608 + n * 0x08)
  80#define FEC_TCCR(n)             (0x60C + n * 0x08)
  81#define MAX_TIMER_CHANNEL       3
  82#define FEC_TMODE_TOGGLE        0x05
  83#define FEC_HIGH_PULSE          0x0F
  84
  85#define FEC_CC_MULT     (1 << 31)
  86#define FEC_COUNTER_PERIOD      (1 << 31)
  87#define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC
  88#define FEC_CHANNLE_0           0
  89#define DEFAULT_PPS_CHANNEL     FEC_CHANNLE_0
  90
  91/**
  92 * fec_ptp_enable_pps
  93 * @fep: the fec_enet_private structure handle
  94 * @enable: enable the channel pps output
  95 *
  96 * This function enble the PPS ouput on the timer channel.
  97 */
  98static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
  99{
 100        unsigned long flags;
 101        u32 val, tempval;
 102        struct timespec64 ts;
 103        u64 ns;
 104        val = 0;
 105
 106        if (fep->pps_enable == enable)
 107                return 0;
 108
 109        fep->pps_channel = DEFAULT_PPS_CHANNEL;
 110        fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
 111
 112        spin_lock_irqsave(&fep->tmreg_lock, flags);
 113
 114        if (enable) {
 115                /* clear capture or output compare interrupt status if have.
 116                 */
 117                writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
 118
 119                /* It is recommended to double check the TMODE field in the
 120                 * TCSR register to be cleared before the first compare counter
 121                 * is written into TCCR register. Just add a double check.
 122                 */
 123                val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
 124                do {
 125                        val &= ~(FEC_T_TMODE_MASK);
 126                        writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
 127                        val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
 128                } while (val & FEC_T_TMODE_MASK);
 129
 130                /* Dummy read counter to update the counter */
 131                timecounter_read(&fep->tc);
 132                /* We want to find the first compare event in the next
 133                 * second point. So we need to know what the ptp time
 134                 * is now and how many nanoseconds is ahead to get next second.
 135                 * The remaining nanosecond ahead before the next second would be
 136                 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
 137                 * to current timer would be next second.
 138                 */
 139                tempval = readl(fep->hwp + FEC_ATIME_CTRL);
 140                tempval |= FEC_T_CTRL_CAPTURE;
 141                writel(tempval, fep->hwp + FEC_ATIME_CTRL);
 142
 143                tempval = readl(fep->hwp + FEC_ATIME);
 144                /* Convert the ptp local counter to 1588 timestamp */
 145                ns = timecounter_cyc2time(&fep->tc, tempval);
 146                ts = ns_to_timespec64(ns);
 147
 148                /* The tempval is  less than 3 seconds, and  so val is less than
 149                 * 4 seconds. No overflow for 32bit calculation.
 150                 */
 151                val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;
 152
 153                /* Need to consider the situation that the current time is
 154                 * very close to the second point, which means NSEC_PER_SEC
 155                 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
 156                 * is still running when we calculate the first compare event, it is
 157                 * possible that the remaining nanoseonds run out before the compare
 158                 * counter is calculated and written into TCCR register. To avoid
 159                 * this possibility, we will set the compare event to be the next
 160                 * of next second. The current setting is 31-bit timer and wrap
 161                 * around over 2 seconds. So it is okay to set the next of next
 162                 * seond for the timer.
 163                 */
 164                val += NSEC_PER_SEC;
 165
 166                /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
 167                 * ptp counter, which maybe cause 32-bit wrap. Since the
 168                 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
 169                 * We can ensure the wrap will not cause issue. If the offset
 170                 * is bigger than fep->cc.mask would be a error.
 171                 */
 172                val &= fep->cc.mask;
 173                writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
 174
 175                /* Calculate the second the compare event timestamp */
 176                fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
 177
 178                /* * Enable compare event when overflow */
 179                val = readl(fep->hwp + FEC_ATIME_CTRL);
 180                val |= FEC_T_CTRL_PINPER;
 181                writel(val, fep->hwp + FEC_ATIME_CTRL);
 182
 183                /* Compare channel setting. */
 184                val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
 185                val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
 186                val &= ~(1 << FEC_T_TDRE_OFFSET);
 187                val &= ~(FEC_T_TMODE_MASK);
 188                val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET);
 189                writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
 190
 191                /* Write the second compare event timestamp and calculate
 192                 * the third timestamp. Refer the TCCR register detail in the spec.
 193                 */
 194                writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
 195                fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
 196        } else {
 197                writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
 198        }
 199
 200        fep->pps_enable = enable;
 201        spin_unlock_irqrestore(&fep->tmreg_lock, flags);
 202
 203        return 0;
 204}
 205
 206/**
 207 * fec_ptp_read - read raw cycle counter (to be used by time counter)
 208 * @cc: the cyclecounter structure
 209 *
 210 * this function reads the cyclecounter registers and is called by the
 211 * cyclecounter structure used to construct a ns counter from the
 212 * arbitrary fixed point registers
 213 */
 214static u64 fec_ptp_read(const struct cyclecounter *cc)
 215{
 216        struct fec_enet_private *fep =
 217                container_of(cc, struct fec_enet_private, cc);
 218        const struct platform_device_id *id_entry =
 219                platform_get_device_id(fep->pdev);
 220        u32 tempval;
 221
 222        tempval = readl(fep->hwp + FEC_ATIME_CTRL);
 223        tempval |= FEC_T_CTRL_CAPTURE;
 224        writel(tempval, fep->hwp + FEC_ATIME_CTRL);
 225
 226        if (id_entry->driver_data & FEC_QUIRK_BUG_CAPTURE)
 227                udelay(1);
 228
 229        return readl(fep->hwp + FEC_ATIME);
 230}
 231
 232/**
 233 * fec_ptp_start_cyclecounter - create the cycle counter from hw
 234 * @ndev: network device
 235 *
 236 * this function initializes the timecounter and cyclecounter
 237 * structures for use in generated a ns counter from the arbitrary
 238 * fixed point cycles registers in the hardware.
 239 */
 240void fec_ptp_start_cyclecounter(struct net_device *ndev)
 241{
 242        struct fec_enet_private *fep = netdev_priv(ndev);
 243        unsigned long flags;
 244        int inc;
 245
 246        inc = 1000000000 / fep->cycle_speed;
 247
 248        /* grab the ptp lock */
 249        spin_lock_irqsave(&fep->tmreg_lock, flags);
 250
 251        /* 1ns counter */
 252        writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
 253
 254        /* use 31-bit timer counter */
 255        writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
 256
 257        writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
 258                fep->hwp + FEC_ATIME_CTRL);
 259
 260        memset(&fep->cc, 0, sizeof(fep->cc));
 261        fep->cc.read = fec_ptp_read;
 262        fep->cc.mask = CLOCKSOURCE_MASK(31);
 263        fep->cc.shift = 31;
 264        fep->cc.mult = FEC_CC_MULT;
 265
 266        /* reset the ns time counter */
 267        timecounter_init(&fep->tc, &fep->cc, 0);
 268
 269        spin_unlock_irqrestore(&fep->tmreg_lock, flags);
 270}
 271
 272/**
 273 * fec_ptp_adjfreq - adjust ptp cycle frequency
 274 * @ptp: the ptp clock structure
 275 * @ppb: parts per billion adjustment from base
 276 *
 277 * Adjust the frequency of the ptp cycle counter by the
 278 * indicated ppb from the base frequency.
 279 *
 280 * Because ENET hardware frequency adjust is complex,
 281 * using software method to do that.
 282 */
 283static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 284{
 285        unsigned long flags;
 286        int neg_adj = 0;
 287        u32 i, tmp;
 288        u32 corr_inc, corr_period;
 289        u32 corr_ns;
 290        u64 lhs, rhs;
 291
 292        struct fec_enet_private *fep =
 293            container_of(ptp, struct fec_enet_private, ptp_caps);
 294
 295        if (ppb == 0)
 296                return 0;
 297
 298        if (ppb < 0) {
 299                ppb = -ppb;
 300                neg_adj = 1;
 301        }
 302
 303        /* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC;
 304         * Try to find the corr_inc  between 1 to fep->ptp_inc to
 305         * meet adjustment requirement.
 306         */
 307        lhs = NSEC_PER_SEC;
 308        rhs = (u64)ppb * (u64)fep->ptp_inc;
 309        for (i = 1; i <= fep->ptp_inc; i++) {
 310                if (lhs >= rhs) {
 311                        corr_inc = i;
 312                        corr_period = div_u64(lhs, rhs);
 313                        break;
 314                }
 315                lhs += NSEC_PER_SEC;
 316        }
 317        /* Not found? Set it to high value - double speed
 318         * correct in every clock step.
 319         */
 320        if (i > fep->ptp_inc) {
 321                corr_inc = fep->ptp_inc;
 322                corr_period = 1;
 323        }
 324
 325        if (neg_adj)
 326                corr_ns = fep->ptp_inc - corr_inc;
 327        else
 328                corr_ns = fep->ptp_inc + corr_inc;
 329
 330        spin_lock_irqsave(&fep->tmreg_lock, flags);
 331
 332        tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
 333        tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
 334        writel(tmp, fep->hwp + FEC_ATIME_INC);
 335        corr_period = corr_period > 1 ? corr_period - 1 : corr_period;
 336        writel(corr_period, fep->hwp + FEC_ATIME_CORR);
 337        /* dummy read to update the timer. */
 338        timecounter_read(&fep->tc);
 339
 340        spin_unlock_irqrestore(&fep->tmreg_lock, flags);
 341
 342        return 0;
 343}
 344
 345/**
 346 * fec_ptp_adjtime
 347 * @ptp: the ptp clock structure
 348 * @delta: offset to adjust the cycle counter by
 349 *
 350 * adjust the timer by resetting the timecounter structure.
 351 */
 352static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 353{
 354        struct fec_enet_private *fep =
 355            container_of(ptp, struct fec_enet_private, ptp_caps);
 356        unsigned long flags;
 357
 358        spin_lock_irqsave(&fep->tmreg_lock, flags);
 359        timecounter_adjtime(&fep->tc, delta);
 360        spin_unlock_irqrestore(&fep->tmreg_lock, flags);
 361
 362        return 0;
 363}
 364
 365/**
 366 * fec_ptp_gettime
 367 * @ptp: the ptp clock structure
 368 * @ts: timespec structure to hold the current time value
 369 *
 370 * read the timecounter and return the correct value on ns,
 371 * after converting it into a struct timespec.
 372 */
 373static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
 374{
 375        struct fec_enet_private *adapter =
 376            container_of(ptp, struct fec_enet_private, ptp_caps);
 377        u64 ns;
 378        unsigned long flags;
 379
 380        spin_lock_irqsave(&adapter->tmreg_lock, flags);
 381        ns = timecounter_read(&adapter->tc);
 382        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 383
 384        *ts = ns_to_timespec64(ns);
 385
 386        return 0;
 387}
 388
 389/**
 390 * fec_ptp_settime
 391 * @ptp: the ptp clock structure
 392 * @ts: the timespec containing the new time for the cycle counter
 393 *
 394 * reset the timecounter to use a new base value instead of the kernel
 395 * wall timer value.
 396 */
 397static int fec_ptp_settime(struct ptp_clock_info *ptp,
 398                           const struct timespec64 *ts)
 399{
 400        struct fec_enet_private *fep =
 401            container_of(ptp, struct fec_enet_private, ptp_caps);
 402
 403        u64 ns;
 404        unsigned long flags;
 405        u32 counter;
 406
 407        mutex_lock(&fep->ptp_clk_mutex);
 408        /* Check the ptp clock */
 409        if (!fep->ptp_clk_on) {
 410                mutex_unlock(&fep->ptp_clk_mutex);
 411                return -EINVAL;
 412        }
 413
 414        ns = timespec64_to_ns(ts);
 415        /* Get the timer value based on timestamp.
 416         * Update the counter with the masked value.
 417         */
 418        counter = ns & fep->cc.mask;
 419
 420        spin_lock_irqsave(&fep->tmreg_lock, flags);
 421        writel(counter, fep->hwp + FEC_ATIME);
 422        timecounter_init(&fep->tc, &fep->cc, ns);
 423        spin_unlock_irqrestore(&fep->tmreg_lock, flags);
 424        mutex_unlock(&fep->ptp_clk_mutex);
 425        return 0;
 426}
 427
 428/**
 429 * fec_ptp_enable
 430 * @ptp: the ptp clock structure
 431 * @rq: the requested feature to change
 432 * @on: whether to enable or disable the feature
 433 *
 434 */
 435static int fec_ptp_enable(struct ptp_clock_info *ptp,
 436                          struct ptp_clock_request *rq, int on)
 437{
 438        struct fec_enet_private *fep =
 439            container_of(ptp, struct fec_enet_private, ptp_caps);
 440        int ret = 0;
 441
 442        if (rq->type == PTP_CLK_REQ_PPS) {
 443                ret = fec_ptp_enable_pps(fep, on);
 444
 445                return ret;
 446        }
 447        return -EOPNOTSUPP;
 448}
 449
 450/**
 451 * fec_ptp_disable_hwts - disable hardware time stamping
 452 * @ndev: pointer to net_device
 453 */
 454void fec_ptp_disable_hwts(struct net_device *ndev)
 455{
 456        struct fec_enet_private *fep = netdev_priv(ndev);
 457
 458        fep->hwts_tx_en = 0;
 459        fep->hwts_rx_en = 0;
 460}
 461
 462int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr)
 463{
 464        struct fec_enet_private *fep = netdev_priv(ndev);
 465
 466        struct hwtstamp_config config;
 467
 468        if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 469                return -EFAULT;
 470
 471        /* reserved for future extensions */
 472        if (config.flags)
 473                return -EINVAL;
 474
 475        switch (config.tx_type) {
 476        case HWTSTAMP_TX_OFF:
 477                fep->hwts_tx_en = 0;
 478                break;
 479        case HWTSTAMP_TX_ON:
 480                fep->hwts_tx_en = 1;
 481                break;
 482        default:
 483                return -ERANGE;
 484        }
 485
 486        switch (config.rx_filter) {
 487        case HWTSTAMP_FILTER_NONE:
 488                fep->hwts_rx_en = 0;
 489                break;
 490
 491        default:
 492                fep->hwts_rx_en = 1;
 493                config.rx_filter = HWTSTAMP_FILTER_ALL;
 494                break;
 495        }
 496
 497        return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 498            -EFAULT : 0;
 499}
 500
 501int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr)
 502{
 503        struct fec_enet_private *fep = netdev_priv(ndev);
 504        struct hwtstamp_config config;
 505
 506        config.flags = 0;
 507        config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 508        config.rx_filter = (fep->hwts_rx_en ?
 509                            HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 510
 511        return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 512                -EFAULT : 0;
 513}
 514
 515/*
 516 * fec_time_keep - call timecounter_read every second to avoid timer overrun
 517 *                 because ENET just support 32bit counter, will timeout in 4s
 518 */
 519static void fec_time_keep(struct work_struct *work)
 520{
 521        struct delayed_work *dwork = to_delayed_work(work);
 522        struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
 523        unsigned long flags;
 524
 525        mutex_lock(&fep->ptp_clk_mutex);
 526        if (fep->ptp_clk_on) {
 527                spin_lock_irqsave(&fep->tmreg_lock, flags);
 528                timecounter_read(&fep->tc);
 529                spin_unlock_irqrestore(&fep->tmreg_lock, flags);
 530        }
 531        mutex_unlock(&fep->ptp_clk_mutex);
 532
 533        schedule_delayed_work(&fep->time_keep, HZ);
 534}
 535
 536/* This function checks the pps event and reloads the timer compare counter. */
 537static irqreturn_t fec_pps_interrupt(int irq, void *dev_id)
 538{
 539        struct net_device *ndev = dev_id;
 540        struct fec_enet_private *fep = netdev_priv(ndev);
 541        u32 val;
 542        u8 channel = fep->pps_channel;
 543        struct ptp_clock_event event;
 544
 545        val = readl(fep->hwp + FEC_TCSR(channel));
 546        if (val & FEC_T_TF_MASK) {
 547                /* Write the next next compare(not the next according the spec)
 548                 * value to the register
 549                 */
 550                writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
 551                do {
 552                        writel(val, fep->hwp + FEC_TCSR(channel));
 553                } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
 554
 555                /* Update the counter; */
 556                fep->next_counter = (fep->next_counter + fep->reload_period) &
 557                                fep->cc.mask;
 558
 559                event.type = PTP_CLOCK_PPS;
 560                ptp_clock_event(fep->ptp_clock, &event);
 561                return IRQ_HANDLED;
 562        }
 563
 564        return IRQ_NONE;
 565}
 566
 567/**
 568 * fec_ptp_init
 569 * @pdev: The FEC network adapter
 570 * @irq_idx: the interrupt index
 571 *
 572 * This function performs the required steps for enabling ptp
 573 * support. If ptp support has already been loaded it simply calls the
 574 * cyclecounter init routine and exits.
 575 */
 576
 577void fec_ptp_init(struct platform_device *pdev, int irq_idx)
 578{
 579        struct net_device *ndev = platform_get_drvdata(pdev);
 580        struct fec_enet_private *fep = netdev_priv(ndev);
 581        int irq;
 582        int ret;
 583
 584        fep->ptp_caps.owner = THIS_MODULE;
 585        strlcpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name));
 586
 587        fep->ptp_caps.max_adj = 250000000;
 588        fep->ptp_caps.n_alarm = 0;
 589        fep->ptp_caps.n_ext_ts = 0;
 590        fep->ptp_caps.n_per_out = 0;
 591        fep->ptp_caps.n_pins = 0;
 592        fep->ptp_caps.pps = 1;
 593        fep->ptp_caps.adjfreq = fec_ptp_adjfreq;
 594        fep->ptp_caps.adjtime = fec_ptp_adjtime;
 595        fep->ptp_caps.gettime64 = fec_ptp_gettime;
 596        fep->ptp_caps.settime64 = fec_ptp_settime;
 597        fep->ptp_caps.enable = fec_ptp_enable;
 598
 599        fep->cycle_speed = clk_get_rate(fep->clk_ptp);
 600        fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
 601
 602        spin_lock_init(&fep->tmreg_lock);
 603
 604        fec_ptp_start_cyclecounter(ndev);
 605
 606        INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
 607
 608        irq = platform_get_irq_byname_optional(pdev, "pps");
 609        if (irq < 0)
 610                irq = platform_get_irq_optional(pdev, irq_idx);
 611        /* Failure to get an irq is not fatal,
 612         * only the PTP_CLOCK_PPS clock events should stop
 613         */
 614        if (irq >= 0) {
 615                ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt,
 616                                       0, pdev->name, ndev);
 617                if (ret < 0)
 618                        dev_warn(&pdev->dev, "request for pps irq failed(%d)\n",
 619                                 ret);
 620        }
 621
 622        fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
 623        if (IS_ERR(fep->ptp_clock)) {
 624                fep->ptp_clock = NULL;
 625                dev_err(&pdev->dev, "ptp_clock_register failed\n");
 626        }
 627
 628        schedule_delayed_work(&fep->time_keep, HZ);
 629}
 630
 631void fec_ptp_stop(struct platform_device *pdev)
 632{
 633        struct net_device *ndev = platform_get_drvdata(pdev);
 634        struct fec_enet_private *fep = netdev_priv(ndev);
 635
 636        cancel_delayed_work_sync(&fep->time_keep);
 637        if (fep->ptp_clock)
 638                ptp_clock_unregister(fep->ptp_clock);
 639}
 640