1
2
3
4#include "i40e_status.h"
5#include "i40e_type.h"
6#include "i40e_register.h"
7#include "i40e_adminq.h"
8#include "i40e_prototype.h"
9
10static void i40e_resume_aq(struct i40e_hw *hw);
11
12
13
14
15
16
17
18static void i40e_adminq_init_regs(struct i40e_hw *hw)
19{
20
21 if (i40e_is_vf(hw)) {
22 hw->aq.asq.tail = I40E_VF_ATQT1;
23 hw->aq.asq.head = I40E_VF_ATQH1;
24 hw->aq.asq.len = I40E_VF_ATQLEN1;
25 hw->aq.asq.bal = I40E_VF_ATQBAL1;
26 hw->aq.asq.bah = I40E_VF_ATQBAH1;
27 hw->aq.arq.tail = I40E_VF_ARQT1;
28 hw->aq.arq.head = I40E_VF_ARQH1;
29 hw->aq.arq.len = I40E_VF_ARQLEN1;
30 hw->aq.arq.bal = I40E_VF_ARQBAL1;
31 hw->aq.arq.bah = I40E_VF_ARQBAH1;
32 } else {
33 hw->aq.asq.tail = I40E_PF_ATQT;
34 hw->aq.asq.head = I40E_PF_ATQH;
35 hw->aq.asq.len = I40E_PF_ATQLEN;
36 hw->aq.asq.bal = I40E_PF_ATQBAL;
37 hw->aq.asq.bah = I40E_PF_ATQBAH;
38 hw->aq.arq.tail = I40E_PF_ARQT;
39 hw->aq.arq.head = I40E_PF_ARQH;
40 hw->aq.arq.len = I40E_PF_ARQLEN;
41 hw->aq.arq.bal = I40E_PF_ARQBAL;
42 hw->aq.arq.bah = I40E_PF_ARQBAH;
43 }
44}
45
46
47
48
49
50static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
51{
52 i40e_status ret_code;
53
54 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
55 i40e_mem_atq_ring,
56 (hw->aq.num_asq_entries *
57 sizeof(struct i40e_aq_desc)),
58 I40E_ADMINQ_DESC_ALIGNMENT);
59 if (ret_code)
60 return ret_code;
61
62 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
63 (hw->aq.num_asq_entries *
64 sizeof(struct i40e_asq_cmd_details)));
65 if (ret_code) {
66 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
67 return ret_code;
68 }
69
70 return ret_code;
71}
72
73
74
75
76
77static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
78{
79 i40e_status ret_code;
80
81 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
82 i40e_mem_arq_ring,
83 (hw->aq.num_arq_entries *
84 sizeof(struct i40e_aq_desc)),
85 I40E_ADMINQ_DESC_ALIGNMENT);
86
87 return ret_code;
88}
89
90
91
92
93
94
95
96
97static void i40e_free_adminq_asq(struct i40e_hw *hw)
98{
99 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
100}
101
102
103
104
105
106
107
108
109static void i40e_free_adminq_arq(struct i40e_hw *hw)
110{
111 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
112}
113
114
115
116
117
118static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
119{
120 i40e_status ret_code;
121 struct i40e_aq_desc *desc;
122 struct i40e_dma_mem *bi;
123 int i;
124
125
126
127
128
129
130 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
131 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
132 if (ret_code)
133 goto alloc_arq_bufs;
134 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
135
136
137 for (i = 0; i < hw->aq.num_arq_entries; i++) {
138 bi = &hw->aq.arq.r.arq_bi[i];
139 ret_code = i40e_allocate_dma_mem(hw, bi,
140 i40e_mem_arq_buf,
141 hw->aq.arq_buf_size,
142 I40E_ADMINQ_DESC_ALIGNMENT);
143 if (ret_code)
144 goto unwind_alloc_arq_bufs;
145
146
147 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
148
149 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
150 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
151 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
152 desc->opcode = 0;
153
154
155
156 desc->datalen = cpu_to_le16((u16)bi->size);
157 desc->retval = 0;
158 desc->cookie_high = 0;
159 desc->cookie_low = 0;
160 desc->params.external.addr_high =
161 cpu_to_le32(upper_32_bits(bi->pa));
162 desc->params.external.addr_low =
163 cpu_to_le32(lower_32_bits(bi->pa));
164 desc->params.external.param0 = 0;
165 desc->params.external.param1 = 0;
166 }
167
168alloc_arq_bufs:
169 return ret_code;
170
171unwind_alloc_arq_bufs:
172
173 i--;
174 for (; i >= 0; i--)
175 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
176 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
177
178 return ret_code;
179}
180
181
182
183
184
185static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
186{
187 i40e_status ret_code;
188 struct i40e_dma_mem *bi;
189 int i;
190
191
192 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
193 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
194 if (ret_code)
195 goto alloc_asq_bufs;
196 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
197
198
199 for (i = 0; i < hw->aq.num_asq_entries; i++) {
200 bi = &hw->aq.asq.r.asq_bi[i];
201 ret_code = i40e_allocate_dma_mem(hw, bi,
202 i40e_mem_asq_buf,
203 hw->aq.asq_buf_size,
204 I40E_ADMINQ_DESC_ALIGNMENT);
205 if (ret_code)
206 goto unwind_alloc_asq_bufs;
207 }
208alloc_asq_bufs:
209 return ret_code;
210
211unwind_alloc_asq_bufs:
212
213 i--;
214 for (; i >= 0; i--)
215 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
216 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
217
218 return ret_code;
219}
220
221
222
223
224
225static void i40e_free_arq_bufs(struct i40e_hw *hw)
226{
227 int i;
228
229
230 for (i = 0; i < hw->aq.num_arq_entries; i++)
231 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
232
233
234 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
235
236
237 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
238}
239
240
241
242
243
244static void i40e_free_asq_bufs(struct i40e_hw *hw)
245{
246 int i;
247
248
249 for (i = 0; i < hw->aq.num_asq_entries; i++)
250 if (hw->aq.asq.r.asq_bi[i].pa)
251 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
252
253
254 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
255
256
257 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
258
259
260 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
261}
262
263
264
265
266
267
268
269static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
270{
271 i40e_status ret_code = 0;
272 u32 reg = 0;
273
274
275 wr32(hw, hw->aq.asq.head, 0);
276 wr32(hw, hw->aq.asq.tail, 0);
277
278
279 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
280 I40E_PF_ATQLEN_ATQENABLE_MASK));
281 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
282 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
283
284
285 reg = rd32(hw, hw->aq.asq.bal);
286 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
287 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
288
289 return ret_code;
290}
291
292
293
294
295
296
297
298static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
299{
300 i40e_status ret_code = 0;
301 u32 reg = 0;
302
303
304 wr32(hw, hw->aq.arq.head, 0);
305 wr32(hw, hw->aq.arq.tail, 0);
306
307
308 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
309 I40E_PF_ARQLEN_ARQENABLE_MASK));
310 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
311 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
312
313
314 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
315
316
317 reg = rd32(hw, hw->aq.arq.bal);
318 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
319 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
320
321 return ret_code;
322}
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337static i40e_status i40e_init_asq(struct i40e_hw *hw)
338{
339 i40e_status ret_code = 0;
340
341 if (hw->aq.asq.count > 0) {
342
343 ret_code = I40E_ERR_NOT_READY;
344 goto init_adminq_exit;
345 }
346
347
348 if ((hw->aq.num_asq_entries == 0) ||
349 (hw->aq.asq_buf_size == 0)) {
350 ret_code = I40E_ERR_CONFIG;
351 goto init_adminq_exit;
352 }
353
354 hw->aq.asq.next_to_use = 0;
355 hw->aq.asq.next_to_clean = 0;
356
357
358 ret_code = i40e_alloc_adminq_asq_ring(hw);
359 if (ret_code)
360 goto init_adminq_exit;
361
362
363 ret_code = i40e_alloc_asq_bufs(hw);
364 if (ret_code)
365 goto init_adminq_free_rings;
366
367
368 ret_code = i40e_config_asq_regs(hw);
369 if (ret_code)
370 goto init_adminq_free_rings;
371
372
373 hw->aq.asq.count = hw->aq.num_asq_entries;
374 goto init_adminq_exit;
375
376init_adminq_free_rings:
377 i40e_free_adminq_asq(hw);
378
379init_adminq_exit:
380 return ret_code;
381}
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396static i40e_status i40e_init_arq(struct i40e_hw *hw)
397{
398 i40e_status ret_code = 0;
399
400 if (hw->aq.arq.count > 0) {
401
402 ret_code = I40E_ERR_NOT_READY;
403 goto init_adminq_exit;
404 }
405
406
407 if ((hw->aq.num_arq_entries == 0) ||
408 (hw->aq.arq_buf_size == 0)) {
409 ret_code = I40E_ERR_CONFIG;
410 goto init_adminq_exit;
411 }
412
413 hw->aq.arq.next_to_use = 0;
414 hw->aq.arq.next_to_clean = 0;
415
416
417 ret_code = i40e_alloc_adminq_arq_ring(hw);
418 if (ret_code)
419 goto init_adminq_exit;
420
421
422 ret_code = i40e_alloc_arq_bufs(hw);
423 if (ret_code)
424 goto init_adminq_free_rings;
425
426
427 ret_code = i40e_config_arq_regs(hw);
428 if (ret_code)
429 goto init_adminq_free_rings;
430
431
432 hw->aq.arq.count = hw->aq.num_arq_entries;
433 goto init_adminq_exit;
434
435init_adminq_free_rings:
436 i40e_free_adminq_arq(hw);
437
438init_adminq_exit:
439 return ret_code;
440}
441
442
443
444
445
446
447
448static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
449{
450 i40e_status ret_code = 0;
451
452 mutex_lock(&hw->aq.asq_mutex);
453
454 if (hw->aq.asq.count == 0) {
455 ret_code = I40E_ERR_NOT_READY;
456 goto shutdown_asq_out;
457 }
458
459
460 wr32(hw, hw->aq.asq.head, 0);
461 wr32(hw, hw->aq.asq.tail, 0);
462 wr32(hw, hw->aq.asq.len, 0);
463 wr32(hw, hw->aq.asq.bal, 0);
464 wr32(hw, hw->aq.asq.bah, 0);
465
466 hw->aq.asq.count = 0;
467
468
469 i40e_free_asq_bufs(hw);
470
471shutdown_asq_out:
472 mutex_unlock(&hw->aq.asq_mutex);
473 return ret_code;
474}
475
476
477
478
479
480
481
482static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
483{
484 i40e_status ret_code = 0;
485
486 mutex_lock(&hw->aq.arq_mutex);
487
488 if (hw->aq.arq.count == 0) {
489 ret_code = I40E_ERR_NOT_READY;
490 goto shutdown_arq_out;
491 }
492
493
494 wr32(hw, hw->aq.arq.head, 0);
495 wr32(hw, hw->aq.arq.tail, 0);
496 wr32(hw, hw->aq.arq.len, 0);
497 wr32(hw, hw->aq.arq.bal, 0);
498 wr32(hw, hw->aq.arq.bah, 0);
499
500 hw->aq.arq.count = 0;
501
502
503 i40e_free_arq_bufs(hw);
504
505shutdown_arq_out:
506 mutex_unlock(&hw->aq.arq_mutex);
507 return ret_code;
508}
509
510
511
512
513
514static void i40e_set_hw_flags(struct i40e_hw *hw)
515{
516 struct i40e_adminq_info *aq = &hw->aq;
517
518 hw->flags = 0;
519
520 switch (hw->mac.type) {
521 case I40E_MAC_XL710:
522 if (aq->api_maj_ver > 1 ||
523 (aq->api_maj_ver == 1 &&
524 aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710)) {
525 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;
526 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
527
528 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE;
529 }
530 break;
531 case I40E_MAC_X722:
532 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
533 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
534
535 if (aq->api_maj_ver > 1 ||
536 (aq->api_maj_ver == 1 &&
537 aq->api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722))
538 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
539
540 if (aq->api_maj_ver > 1 ||
541 (aq->api_maj_ver == 1 &&
542 aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_X722))
543 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;
544
545 if (aq->api_maj_ver > 1 ||
546 (aq->api_maj_ver == 1 &&
547 aq->api_min_ver >= I40E_MINOR_VER_FW_REQUEST_FEC_X722))
548 hw->flags |= I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE;
549
550 fallthrough;
551 default:
552 break;
553 }
554
555
556 if (aq->api_maj_ver > 1 ||
557 (aq->api_maj_ver == 1 &&
558 aq->api_min_ver >= 5))
559 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
560
561 if (aq->api_maj_ver > 1 ||
562 (aq->api_maj_ver == 1 &&
563 aq->api_min_ver >= 8)) {
564 hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT;
565 hw->flags |= I40E_HW_FLAG_DROP_MODE;
566 }
567
568 if (aq->api_maj_ver > 1 ||
569 (aq->api_maj_ver == 1 &&
570 aq->api_min_ver >= 9))
571 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED;
572}
573
574
575
576
577
578
579
580
581
582
583
584
585i40e_status i40e_init_adminq(struct i40e_hw *hw)
586{
587 u16 cfg_ptr, oem_hi, oem_lo;
588 u16 eetrack_lo, eetrack_hi;
589 i40e_status ret_code;
590 int retry = 0;
591
592
593 if ((hw->aq.num_arq_entries == 0) ||
594 (hw->aq.num_asq_entries == 0) ||
595 (hw->aq.arq_buf_size == 0) ||
596 (hw->aq.asq_buf_size == 0)) {
597 ret_code = I40E_ERR_CONFIG;
598 goto init_adminq_exit;
599 }
600
601
602 i40e_adminq_init_regs(hw);
603
604
605 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;
606
607
608 ret_code = i40e_init_asq(hw);
609 if (ret_code)
610 goto init_adminq_destroy_locks;
611
612
613 ret_code = i40e_init_arq(hw);
614 if (ret_code)
615 goto init_adminq_free_asq;
616
617
618
619
620
621 do {
622 ret_code = i40e_aq_get_firmware_version(hw,
623 &hw->aq.fw_maj_ver,
624 &hw->aq.fw_min_ver,
625 &hw->aq.fw_build,
626 &hw->aq.api_maj_ver,
627 &hw->aq.api_min_ver,
628 NULL);
629 if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)
630 break;
631 retry++;
632 msleep(100);
633 i40e_resume_aq(hw);
634 } while (retry < 10);
635 if (ret_code != I40E_SUCCESS)
636 goto init_adminq_free_arq;
637
638
639
640
641 i40e_set_hw_flags(hw);
642
643
644 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,
645 &hw->nvm.version);
646 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
647 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
648 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
649 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr);
650 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF),
651 &oem_hi);
652 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)),
653 &oem_lo);
654 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
655
656 if (hw->mac.type == I40E_MAC_XL710 &&
657 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
658 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
659 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE;
660 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
661 }
662 if (hw->mac.type == I40E_MAC_X722 &&
663 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
664 hw->aq.api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722) {
665 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE;
666 }
667
668
669 if (hw->aq.api_maj_ver > 1 ||
670 (hw->aq.api_maj_ver == 1 &&
671 hw->aq.api_min_ver >= 7))
672 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE;
673
674 if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {
675 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
676 goto init_adminq_free_arq;
677 }
678
679
680 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
681 hw->nvm_release_on_done = false;
682 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
683
684 ret_code = 0;
685
686
687 goto init_adminq_exit;
688
689init_adminq_free_arq:
690 i40e_shutdown_arq(hw);
691init_adminq_free_asq:
692 i40e_shutdown_asq(hw);
693init_adminq_destroy_locks:
694
695init_adminq_exit:
696 return ret_code;
697}
698
699
700
701
702
703void i40e_shutdown_adminq(struct i40e_hw *hw)
704{
705 if (i40e_check_asq_alive(hw))
706 i40e_aq_queue_shutdown(hw, true);
707
708 i40e_shutdown_asq(hw);
709 i40e_shutdown_arq(hw);
710
711 if (hw->nvm_buff.va)
712 i40e_free_virt_mem(hw, &hw->nvm_buff);
713}
714
715
716
717
718
719
720
721static u16 i40e_clean_asq(struct i40e_hw *hw)
722{
723 struct i40e_adminq_ring *asq = &(hw->aq.asq);
724 struct i40e_asq_cmd_details *details;
725 u16 ntc = asq->next_to_clean;
726 struct i40e_aq_desc desc_cb;
727 struct i40e_aq_desc *desc;
728
729 desc = I40E_ADMINQ_DESC(*asq, ntc);
730 details = I40E_ADMINQ_DETAILS(*asq, ntc);
731 while (rd32(hw, hw->aq.asq.head) != ntc) {
732 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,
733 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
734
735 if (details->callback) {
736 I40E_ADMINQ_CALLBACK cb_func =
737 (I40E_ADMINQ_CALLBACK)details->callback;
738 desc_cb = *desc;
739 cb_func(hw, &desc_cb);
740 }
741 memset(desc, 0, sizeof(*desc));
742 memset(details, 0, sizeof(*details));
743 ntc++;
744 if (ntc == asq->count)
745 ntc = 0;
746 desc = I40E_ADMINQ_DESC(*asq, ntc);
747 details = I40E_ADMINQ_DETAILS(*asq, ntc);
748 }
749
750 asq->next_to_clean = ntc;
751
752 return I40E_DESC_UNUSED(asq);
753}
754
755
756
757
758
759
760
761
762static bool i40e_asq_done(struct i40e_hw *hw)
763{
764
765
766
767 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
768
769}
770
771
772
773
774
775
776
777
778
779
780
781
782i40e_status i40e_asq_send_command(struct i40e_hw *hw,
783 struct i40e_aq_desc *desc,
784 void *buff,
785 u16 buff_size,
786 struct i40e_asq_cmd_details *cmd_details)
787{
788 i40e_status status = 0;
789 struct i40e_dma_mem *dma_buff = NULL;
790 struct i40e_asq_cmd_details *details;
791 struct i40e_aq_desc *desc_on_ring;
792 bool cmd_completed = false;
793 u16 retval = 0;
794 u32 val = 0;
795
796 mutex_lock(&hw->aq.asq_mutex);
797
798 if (hw->aq.asq.count == 0) {
799 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
800 "AQTX: Admin queue not initialized.\n");
801 status = I40E_ERR_QUEUE_EMPTY;
802 goto asq_send_command_error;
803 }
804
805 hw->aq.asq_last_status = I40E_AQ_RC_OK;
806
807 val = rd32(hw, hw->aq.asq.head);
808 if (val >= hw->aq.num_asq_entries) {
809 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
810 "AQTX: head overrun at %d\n", val);
811 status = I40E_ERR_ADMIN_QUEUE_FULL;
812 goto asq_send_command_error;
813 }
814
815 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
816 if (cmd_details) {
817 *details = *cmd_details;
818
819
820
821
822
823 if (details->cookie) {
824 desc->cookie_high =
825 cpu_to_le32(upper_32_bits(details->cookie));
826 desc->cookie_low =
827 cpu_to_le32(lower_32_bits(details->cookie));
828 }
829 } else {
830 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
831 }
832
833
834 desc->flags &= ~cpu_to_le16(details->flags_dis);
835 desc->flags |= cpu_to_le16(details->flags_ena);
836
837 if (buff_size > hw->aq.asq_buf_size) {
838 i40e_debug(hw,
839 I40E_DEBUG_AQ_MESSAGE,
840 "AQTX: Invalid buffer size: %d.\n",
841 buff_size);
842 status = I40E_ERR_INVALID_SIZE;
843 goto asq_send_command_error;
844 }
845
846 if (details->postpone && !details->async) {
847 i40e_debug(hw,
848 I40E_DEBUG_AQ_MESSAGE,
849 "AQTX: Async flag not set along with postpone flag");
850 status = I40E_ERR_PARAM;
851 goto asq_send_command_error;
852 }
853
854
855
856
857
858
859
860
861 if (i40e_clean_asq(hw) == 0) {
862 i40e_debug(hw,
863 I40E_DEBUG_AQ_MESSAGE,
864 "AQTX: Error queue is full.\n");
865 status = I40E_ERR_ADMIN_QUEUE_FULL;
866 goto asq_send_command_error;
867 }
868
869
870 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
871
872
873 *desc_on_ring = *desc;
874
875
876 if (buff != NULL) {
877 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
878
879 memcpy(dma_buff->va, buff, buff_size);
880 desc_on_ring->datalen = cpu_to_le16(buff_size);
881
882
883
884
885 desc_on_ring->params.external.addr_high =
886 cpu_to_le32(upper_32_bits(dma_buff->pa));
887 desc_on_ring->params.external.addr_low =
888 cpu_to_le32(lower_32_bits(dma_buff->pa));
889 }
890
891
892 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n");
893 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
894 buff, buff_size);
895 (hw->aq.asq.next_to_use)++;
896 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
897 hw->aq.asq.next_to_use = 0;
898 if (!details->postpone)
899 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
900
901
902
903
904 if (!details->async && !details->postpone) {
905 u32 total_delay = 0;
906
907 do {
908
909
910
911 if (i40e_asq_done(hw))
912 break;
913 udelay(50);
914 total_delay += 50;
915 } while (total_delay < hw->aq.asq_cmd_timeout);
916 }
917
918
919 if (i40e_asq_done(hw)) {
920 *desc = *desc_on_ring;
921 if (buff != NULL)
922 memcpy(buff, dma_buff->va, buff_size);
923 retval = le16_to_cpu(desc->retval);
924 if (retval != 0) {
925 i40e_debug(hw,
926 I40E_DEBUG_AQ_MESSAGE,
927 "AQTX: Command completed with error 0x%X.\n",
928 retval);
929
930
931 retval &= 0xff;
932 }
933 cmd_completed = true;
934 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
935 status = 0;
936 else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY)
937 status = I40E_ERR_NOT_READY;
938 else
939 status = I40E_ERR_ADMIN_QUEUE_ERROR;
940 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
941 }
942
943 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,
944 "AQTX: desc and buffer writeback:\n");
945 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
946
947
948 if (details->wb_desc)
949 *details->wb_desc = *desc_on_ring;
950
951
952 if ((!cmd_completed) &&
953 (!details->async && !details->postpone)) {
954 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
955 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
956 "AQTX: AQ Critical error.\n");
957 status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
958 } else {
959 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
960 "AQTX: Writeback timeout.\n");
961 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
962 }
963 }
964
965asq_send_command_error:
966 mutex_unlock(&hw->aq.asq_mutex);
967 return status;
968}
969
970
971
972
973
974
975
976
977void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
978 u16 opcode)
979{
980
981 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
982 desc->opcode = cpu_to_le16(opcode);
983 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
984}
985
986
987
988
989
990
991
992
993
994
995
996i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
997 struct i40e_arq_event_info *e,
998 u16 *pending)
999{
1000 i40e_status ret_code = 0;
1001 u16 ntc = hw->aq.arq.next_to_clean;
1002 struct i40e_aq_desc *desc;
1003 struct i40e_dma_mem *bi;
1004 u16 desc_idx;
1005 u16 datalen;
1006 u16 flags;
1007 u16 ntu;
1008
1009
1010 memset(&e->desc, 0, sizeof(e->desc));
1011
1012
1013 mutex_lock(&hw->aq.arq_mutex);
1014
1015 if (hw->aq.arq.count == 0) {
1016 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
1017 "AQRX: Admin queue not initialized.\n");
1018 ret_code = I40E_ERR_QUEUE_EMPTY;
1019 goto clean_arq_element_err;
1020 }
1021
1022
1023 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1024 if (ntu == ntc) {
1025
1026 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
1027 goto clean_arq_element_out;
1028 }
1029
1030
1031 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
1032 desc_idx = ntc;
1033
1034 hw->aq.arq_last_status =
1035 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
1036 flags = le16_to_cpu(desc->flags);
1037 if (flags & I40E_AQ_FLAG_ERR) {
1038 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
1039 i40e_debug(hw,
1040 I40E_DEBUG_AQ_MESSAGE,
1041 "AQRX: Event received with error 0x%X.\n",
1042 hw->aq.arq_last_status);
1043 }
1044
1045 e->desc = *desc;
1046 datalen = le16_to_cpu(desc->datalen);
1047 e->msg_len = min(datalen, e->buf_len);
1048 if (e->msg_buf != NULL && (e->msg_len != 0))
1049 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
1050 e->msg_len);
1051
1052 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n");
1053 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
1054 hw->aq.arq_buf_size);
1055
1056
1057
1058
1059
1060 bi = &hw->aq.arq.r.arq_bi[ntc];
1061 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
1062
1063 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
1064 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
1065 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
1066 desc->datalen = cpu_to_le16((u16)bi->size);
1067 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
1068 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
1069
1070
1071 wr32(hw, hw->aq.arq.tail, ntc);
1072
1073 ntc++;
1074 if (ntc == hw->aq.num_arq_entries)
1075 ntc = 0;
1076 hw->aq.arq.next_to_clean = ntc;
1077 hw->aq.arq.next_to_use = ntu;
1078
1079 i40e_nvmupd_check_wait_event(hw, le16_to_cpu(e->desc.opcode), &e->desc);
1080clean_arq_element_out:
1081
1082 if (pending)
1083 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
1084clean_arq_element_err:
1085 mutex_unlock(&hw->aq.arq_mutex);
1086
1087 return ret_code;
1088}
1089
1090static void i40e_resume_aq(struct i40e_hw *hw)
1091{
1092
1093 hw->aq.asq.next_to_use = 0;
1094 hw->aq.asq.next_to_clean = 0;
1095
1096 i40e_config_asq_regs(hw);
1097
1098 hw->aq.arq.next_to_use = 0;
1099 hw->aq.arq.next_to_clean = 0;
1100
1101 i40e_config_arq_regs(hw);
1102}
1103