1
2
3
4#ifndef _I40E_ADMINQ_CMD_H_
5#define _I40E_ADMINQ_CMD_H_
6
7
8
9
10
11
12
13#define I40E_FW_API_VERSION_MAJOR 0x0001
14#define I40E_FW_API_VERSION_MINOR_X722 0x0009
15#define I40E_FW_API_VERSION_MINOR_X710 0x0009
16
17#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
18 I40E_FW_API_VERSION_MINOR_X710 : \
19 I40E_FW_API_VERSION_MINOR_X722)
20
21
22#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
23
24#define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
25
26#define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
27
28#define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
29
30struct i40e_aq_desc {
31 __le16 flags;
32 __le16 opcode;
33 __le16 datalen;
34 __le16 retval;
35 __le32 cookie_high;
36 __le32 cookie_low;
37 union {
38 struct {
39 __le32 param0;
40 __le32 param1;
41 __le32 param2;
42 __le32 param3;
43 } internal;
44 struct {
45 __le32 param0;
46 __le32 param1;
47 __le32 addr_high;
48 __le32 addr_low;
49 } external;
50 u8 raw[16];
51 } params;
52};
53
54
55
56
57
58
59
60#define I40E_AQ_FLAG_ERR_SHIFT 2
61#define I40E_AQ_FLAG_LB_SHIFT 9
62#define I40E_AQ_FLAG_RD_SHIFT 10
63#define I40E_AQ_FLAG_BUF_SHIFT 12
64#define I40E_AQ_FLAG_SI_SHIFT 13
65
66#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT)
67#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT)
68#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT)
69#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT)
70#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT)
71
72
73enum i40e_admin_queue_err {
74 I40E_AQ_RC_OK = 0,
75 I40E_AQ_RC_EPERM = 1,
76 I40E_AQ_RC_ENOENT = 2,
77 I40E_AQ_RC_ESRCH = 3,
78 I40E_AQ_RC_EINTR = 4,
79 I40E_AQ_RC_EIO = 5,
80 I40E_AQ_RC_ENXIO = 6,
81 I40E_AQ_RC_E2BIG = 7,
82 I40E_AQ_RC_EAGAIN = 8,
83 I40E_AQ_RC_ENOMEM = 9,
84 I40E_AQ_RC_EACCES = 10,
85 I40E_AQ_RC_EFAULT = 11,
86 I40E_AQ_RC_EBUSY = 12,
87 I40E_AQ_RC_EEXIST = 13,
88 I40E_AQ_RC_EINVAL = 14,
89 I40E_AQ_RC_ENOTTY = 15,
90 I40E_AQ_RC_ENOSPC = 16,
91 I40E_AQ_RC_ENOSYS = 17,
92 I40E_AQ_RC_ERANGE = 18,
93 I40E_AQ_RC_EFLUSHED = 19,
94 I40E_AQ_RC_BAD_ADDR = 20,
95 I40E_AQ_RC_EMODE = 21,
96 I40E_AQ_RC_EFBIG = 22,
97};
98
99
100enum i40e_admin_queue_opc {
101
102 i40e_aqc_opc_get_version = 0x0001,
103 i40e_aqc_opc_driver_version = 0x0002,
104 i40e_aqc_opc_queue_shutdown = 0x0003,
105 i40e_aqc_opc_set_pf_context = 0x0004,
106
107
108 i40e_aqc_opc_request_resource = 0x0008,
109 i40e_aqc_opc_release_resource = 0x0009,
110
111 i40e_aqc_opc_list_func_capabilities = 0x000A,
112 i40e_aqc_opc_list_dev_capabilities = 0x000B,
113
114
115 i40e_aqc_opc_set_proxy_config = 0x0104,
116 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
117
118
119 i40e_aqc_opc_mac_address_read = 0x0107,
120 i40e_aqc_opc_mac_address_write = 0x0108,
121
122
123 i40e_aqc_opc_clear_pxe_mode = 0x0110,
124
125
126 i40e_aqc_opc_set_wol_filter = 0x0120,
127 i40e_aqc_opc_get_wake_reason = 0x0121,
128
129
130 i40e_aqc_opc_get_switch_config = 0x0200,
131 i40e_aqc_opc_add_statistics = 0x0201,
132 i40e_aqc_opc_remove_statistics = 0x0202,
133 i40e_aqc_opc_set_port_parameters = 0x0203,
134 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
135 i40e_aqc_opc_set_switch_config = 0x0205,
136 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
137 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
138
139 i40e_aqc_opc_add_vsi = 0x0210,
140 i40e_aqc_opc_update_vsi_parameters = 0x0211,
141 i40e_aqc_opc_get_vsi_parameters = 0x0212,
142
143 i40e_aqc_opc_add_pv = 0x0220,
144 i40e_aqc_opc_update_pv_parameters = 0x0221,
145 i40e_aqc_opc_get_pv_parameters = 0x0222,
146
147 i40e_aqc_opc_add_veb = 0x0230,
148 i40e_aqc_opc_update_veb_parameters = 0x0231,
149 i40e_aqc_opc_get_veb_parameters = 0x0232,
150
151 i40e_aqc_opc_delete_element = 0x0243,
152
153 i40e_aqc_opc_add_macvlan = 0x0250,
154 i40e_aqc_opc_remove_macvlan = 0x0251,
155 i40e_aqc_opc_add_vlan = 0x0252,
156 i40e_aqc_opc_remove_vlan = 0x0253,
157 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
158 i40e_aqc_opc_add_tag = 0x0255,
159 i40e_aqc_opc_remove_tag = 0x0256,
160 i40e_aqc_opc_add_multicast_etag = 0x0257,
161 i40e_aqc_opc_remove_multicast_etag = 0x0258,
162 i40e_aqc_opc_update_tag = 0x0259,
163 i40e_aqc_opc_add_control_packet_filter = 0x025A,
164 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
165 i40e_aqc_opc_add_cloud_filters = 0x025C,
166 i40e_aqc_opc_remove_cloud_filters = 0x025D,
167 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
168
169 i40e_aqc_opc_add_mirror_rule = 0x0260,
170 i40e_aqc_opc_delete_mirror_rule = 0x0261,
171
172
173 i40e_aqc_opc_write_personalization_profile = 0x0270,
174 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
175
176
177 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
178 i40e_aqc_opc_dcb_updated = 0x0302,
179 i40e_aqc_opc_set_dcb_parameters = 0x0303,
180
181
182 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
183 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
184 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
185 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
186 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
187 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
188
189 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
190 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
191 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
192 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
193 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
194 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
195 i40e_aqc_opc_query_port_ets_config = 0x0419,
196 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
197 i40e_aqc_opc_suspend_port_tx = 0x041B,
198 i40e_aqc_opc_resume_port_tx = 0x041C,
199 i40e_aqc_opc_configure_partition_bw = 0x041D,
200
201 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
202 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
203
204
205 i40e_aqc_opc_get_phy_abilities = 0x0600,
206 i40e_aqc_opc_set_phy_config = 0x0601,
207 i40e_aqc_opc_set_mac_config = 0x0603,
208 i40e_aqc_opc_set_link_restart_an = 0x0605,
209 i40e_aqc_opc_get_link_status = 0x0607,
210 i40e_aqc_opc_set_phy_int_mask = 0x0613,
211 i40e_aqc_opc_get_local_advt_reg = 0x0614,
212 i40e_aqc_opc_set_local_advt_reg = 0x0615,
213 i40e_aqc_opc_get_partner_advt = 0x0616,
214 i40e_aqc_opc_set_lb_modes = 0x0618,
215 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
216 i40e_aqc_opc_set_phy_debug = 0x0622,
217 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
218 i40e_aqc_opc_run_phy_activity = 0x0626,
219 i40e_aqc_opc_set_phy_register = 0x0628,
220 i40e_aqc_opc_get_phy_register = 0x0629,
221
222
223 i40e_aqc_opc_nvm_read = 0x0701,
224 i40e_aqc_opc_nvm_erase = 0x0702,
225 i40e_aqc_opc_nvm_update = 0x0703,
226 i40e_aqc_opc_nvm_config_read = 0x0704,
227 i40e_aqc_opc_nvm_config_write = 0x0705,
228 i40e_aqc_opc_oem_post_update = 0x0720,
229 i40e_aqc_opc_thermal_sensor = 0x0721,
230
231
232 i40e_aqc_opc_send_msg_to_pf = 0x0801,
233 i40e_aqc_opc_send_msg_to_vf = 0x0802,
234 i40e_aqc_opc_send_msg_to_peer = 0x0803,
235
236
237 i40e_aqc_opc_alternate_write = 0x0900,
238 i40e_aqc_opc_alternate_write_indirect = 0x0901,
239 i40e_aqc_opc_alternate_read = 0x0902,
240 i40e_aqc_opc_alternate_read_indirect = 0x0903,
241 i40e_aqc_opc_alternate_write_done = 0x0904,
242 i40e_aqc_opc_alternate_set_mode = 0x0905,
243 i40e_aqc_opc_alternate_clear_port = 0x0906,
244
245
246 i40e_aqc_opc_lldp_get_mib = 0x0A00,
247 i40e_aqc_opc_lldp_update_mib = 0x0A01,
248 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
249 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
250 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
251 i40e_aqc_opc_lldp_stop = 0x0A05,
252 i40e_aqc_opc_lldp_start = 0x0A06,
253 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
254 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
255 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
256 i40e_aqc_opc_lldp_restore = 0x0A0A,
257
258
259 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
260 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
261 i40e_aqc_opc_set_rss_key = 0x0B02,
262 i40e_aqc_opc_set_rss_lut = 0x0B03,
263 i40e_aqc_opc_get_rss_key = 0x0B04,
264 i40e_aqc_opc_get_rss_lut = 0x0B05,
265
266
267 i40e_aqc_opc_event_lan_overflow = 0x1001,
268
269
270 i40e_aqc_opc_oem_parameter_change = 0xFE00,
271 i40e_aqc_opc_oem_device_status_change = 0xFE01,
272 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
273 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
274
275
276 i40e_aqc_opc_debug_read_reg = 0xFF03,
277 i40e_aqc_opc_debug_write_reg = 0xFF04,
278 i40e_aqc_opc_debug_modify_reg = 0xFF07,
279 i40e_aqc_opc_debug_dump_internals = 0xFF08,
280};
281
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297
298
299
300#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
301 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
302
303
304
305
306#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
307
308
309
310
311struct i40e_aqc_get_version {
312 __le32 rom_ver;
313 __le32 fw_build;
314 __le16 fw_major;
315 __le16 fw_minor;
316 __le16 api_major;
317 __le16 api_minor;
318};
319
320I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
321
322
323struct i40e_aqc_driver_version {
324 u8 driver_major_ver;
325 u8 driver_minor_ver;
326 u8 driver_build_ver;
327 u8 driver_subbuild_ver;
328 u8 reserved[4];
329 __le32 address_high;
330 __le32 address_low;
331};
332
333I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
334
335
336struct i40e_aqc_queue_shutdown {
337 __le32 driver_unloading;
338#define I40E_AQ_DRIVER_UNLOADING 0x1
339 u8 reserved[12];
340};
341
342I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
343
344
345struct i40e_aqc_set_pf_context {
346 u8 pf_id;
347 u8 reserved[15];
348};
349
350I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
351
352
353
354
355struct i40e_aqc_request_resource {
356 __le16 resource_id;
357 __le16 access_type;
358 __le32 timeout;
359 __le32 resource_number;
360 u8 reserved[4];
361};
362
363I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
364
365
366
367
368struct i40e_aqc_list_capabilites {
369 u8 command_flags;
370 u8 pf_index;
371 u8 reserved[2];
372 __le32 count;
373 __le32 addr_high;
374 __le32 addr_low;
375};
376
377I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
378
379struct i40e_aqc_list_capabilities_element_resp {
380 __le16 id;
381 u8 major_rev;
382 u8 minor_rev;
383 __le32 number;
384 __le32 logical_id;
385 __le32 phys_id;
386 u8 reserved[16];
387};
388
389
390
391#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
392#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
393#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
394#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
395#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
396#define I40E_AQ_CAP_ID_SRIOV 0x0012
397#define I40E_AQ_CAP_ID_VF 0x0013
398#define I40E_AQ_CAP_ID_VMDQ 0x0014
399#define I40E_AQ_CAP_ID_8021QBG 0x0015
400#define I40E_AQ_CAP_ID_8021QBR 0x0016
401#define I40E_AQ_CAP_ID_VSI 0x0017
402#define I40E_AQ_CAP_ID_DCB 0x0018
403#define I40E_AQ_CAP_ID_FCOE 0x0021
404#define I40E_AQ_CAP_ID_ISCSI 0x0022
405#define I40E_AQ_CAP_ID_RSS 0x0040
406#define I40E_AQ_CAP_ID_RXQ 0x0041
407#define I40E_AQ_CAP_ID_TXQ 0x0042
408#define I40E_AQ_CAP_ID_MSIX 0x0043
409#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
410#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
411#define I40E_AQ_CAP_ID_1588 0x0046
412#define I40E_AQ_CAP_ID_IWARP 0x0051
413#define I40E_AQ_CAP_ID_LED 0x0061
414#define I40E_AQ_CAP_ID_SDP 0x0062
415#define I40E_AQ_CAP_ID_MDIO 0x0063
416#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
417#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
418#define I40E_AQ_CAP_ID_FLEX10 0x00F1
419#define I40E_AQ_CAP_ID_CEM 0x00F2
420
421
422struct i40e_aqc_cppm_configuration {
423 __le16 command_flags;
424 __le16 ttlx;
425 __le32 dmacr;
426 __le16 dmcth;
427 u8 hptc;
428 u8 reserved;
429 __le32 pfltrc;
430};
431
432I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
433
434
435struct i40e_aqc_arp_proxy_data {
436 __le16 command_flags;
437 __le16 table_id;
438 __le32 enabled_offloads;
439 __le32 ip_addr;
440 u8 mac_addr[6];
441 u8 reserved[2];
442};
443
444I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
445
446
447struct i40e_aqc_ns_proxy_data {
448 __le16 table_idx_mac_addr_0;
449 __le16 table_idx_mac_addr_1;
450 __le16 table_idx_ipv6_0;
451 __le16 table_idx_ipv6_1;
452 __le16 control;
453 u8 mac_addr_0[6];
454 u8 mac_addr_1[6];
455 u8 local_mac_addr[6];
456 u8 ipv6_addr_0[16];
457 u8 ipv6_addr_1[16];
458};
459
460I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
461
462
463struct i40e_aqc_mng_laa {
464 __le16 command_flags;
465 u8 reserved[2];
466 __le32 sal;
467 __le16 sah;
468 u8 reserved2[6];
469};
470
471I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
472
473
474struct i40e_aqc_mac_address_read {
475 __le16 command_flags;
476#define I40E_AQC_LAN_ADDR_VALID 0x10
477#define I40E_AQC_PORT_ADDR_VALID 0x40
478 u8 reserved[6];
479 __le32 addr_high;
480 __le32 addr_low;
481};
482
483I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
484
485struct i40e_aqc_mac_address_read_data {
486 u8 pf_lan_mac[6];
487 u8 pf_san_mac[6];
488 u8 port_mac[6];
489 u8 pf_wol_mac[6];
490};
491
492I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
493
494
495struct i40e_aqc_mac_address_write {
496 __le16 command_flags;
497#define I40E_AQC_MC_MAG_EN 0x0100
498#define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
499#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
500#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
501#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
502
503 __le16 mac_sah;
504 __le32 mac_sal;
505 u8 reserved[8];
506};
507
508I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
509
510
511
512
513struct i40e_aqc_clear_pxe {
514 u8 rx_cnt;
515 u8 reserved[15];
516};
517
518I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
519
520
521
522struct i40e_aqc_set_wol_filter {
523 __le16 filter_index;
524
525 __le16 cmd_flags;
526 __le16 valid_flags;
527 u8 reserved[2];
528 __le32 address_high;
529 __le32 address_low;
530};
531
532I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
533
534struct i40e_aqc_set_wol_filter_data {
535 u8 filter[128];
536 u8 mask[16];
537};
538
539I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
540
541
542
543struct i40e_aqc_get_wake_reason_completion {
544 u8 reserved_1[2];
545 __le16 wake_reason;
546 u8 reserved_2[12];
547};
548
549I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
550
551
552
553
554
555
556struct i40e_aqc_switch_seid {
557 __le16 seid;
558 u8 reserved[6];
559 __le32 addr_high;
560 __le32 addr_low;
561};
562
563I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
564
565
566
567
568struct i40e_aqc_get_switch_config_header_resp {
569 __le16 num_reported;
570 __le16 num_total;
571 u8 reserved[12];
572};
573
574I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
575
576struct i40e_aqc_switch_config_element_resp {
577 u8 element_type;
578 u8 revision;
579 __le16 seid;
580 __le16 uplink_seid;
581 __le16 downlink_seid;
582 u8 reserved[3];
583 u8 connection_type;
584 __le16 scheduler_id;
585 __le16 element_info;
586};
587
588I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
589
590
591
592
593
594struct i40e_aqc_get_switch_config_resp {
595 struct i40e_aqc_get_switch_config_header_resp header;
596 struct i40e_aqc_switch_config_element_resp element[1];
597};
598
599I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
600
601
602
603
604struct i40e_aqc_add_remove_statistics {
605 __le16 seid;
606 __le16 vlan;
607 __le16 stat_index;
608 u8 reserved[10];
609};
610
611I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
612
613
614struct i40e_aqc_set_port_parameters {
615 __le16 command_flags;
616 __le16 bad_frame_vsi;
617 __le16 default_seid;
618 u8 reserved[10];
619};
620
621I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
622
623
624struct i40e_aqc_get_switch_resource_alloc {
625 u8 num_entries;
626 u8 reserved[7];
627 __le32 addr_high;
628 __le32 addr_low;
629};
630
631I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
632
633
634struct i40e_aqc_switch_resource_alloc_element_resp {
635 u8 resource_type;
636 u8 reserved1;
637 __le16 guaranteed;
638 __le16 total;
639 __le16 used;
640 __le16 total_unalloced;
641 u8 reserved2[6];
642};
643
644I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
645
646
647struct i40e_aqc_set_switch_config {
648 __le16 flags;
649
650#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
651 __le16 valid_flags;
652
653
654
655
656
657 __le16 switch_tag;
658
659
660
661
662
663
664
665 __le16 first_tag;
666 __le16 second_tag;
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681#define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
682
683
684#define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
685
686#define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
687 u8 mode;
688 u8 rsvd5[5];
689};
690
691I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
692
693
694
695
696
697
698struct i40e_aqc_rx_ctl_reg_read_write {
699 __le32 reserved1;
700 __le32 address;
701 __le32 reserved2;
702 __le32 value;
703};
704
705I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
706
707
708
709
710
711
712
713
714
715
716
717struct i40e_aqc_add_get_update_vsi {
718 __le16 uplink_seid;
719 u8 connection_type;
720#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
721 u8 reserved1;
722 u8 vf_id;
723 u8 reserved2;
724 __le16 vsi_flags;
725#define I40E_AQ_VSI_TYPE_VF 0x0
726#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
727#define I40E_AQ_VSI_TYPE_PF 0x2
728 __le32 addr_high;
729 __le32 addr_low;
730};
731
732I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
733
734struct i40e_aqc_add_get_update_vsi_completion {
735 __le16 seid;
736 __le16 vsi_number;
737 __le16 vsi_used;
738 __le16 vsi_free;
739 __le32 addr_high;
740 __le32 addr_low;
741};
742
743I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
744
745struct i40e_aqc_vsi_properties_data {
746
747 __le16 valid_sections;
748#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
749#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
750#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
751#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
752#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
753#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
754
755 __le16 switch_id;
756#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
757#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
758#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
759#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
760 u8 sw_reserved[2];
761
762 u8 sec_flags;
763#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
764#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
765 u8 sec_reserved;
766
767 __le16 pvid;
768 __le16 fcoe_pvid;
769 u8 port_vlan_flags;
770#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
771#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
772 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
773#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
774#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
775#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
776#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
777#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
778 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
779#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
780#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
781#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
782 u8 pvlan_reserved[3];
783
784 __le32 ingress_table;
785 __le32 egress_table;
786
787 __le16 cas_pv_tag;
788 u8 cas_pv_flags;
789 u8 cas_pv_reserved;
790
791 __le16 mapping_flags;
792#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
793#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
794 __le16 queue_mapping[16];
795 __le16 tc_mapping[8];
796#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
797#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
798
799 u8 queueing_opt_flags;
800#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
801#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
802 u8 queueing_opt_reserved[3];
803
804 u8 up_enable_bits;
805 u8 sched_reserved;
806
807 __le32 outer_up_table;
808 u8 cmd_reserved[8];
809
810 __le16 qs_handle[8];
811#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
812 __le16 stat_counter_idx;
813 __le16 sched_id;
814 u8 resp_reserved[12];
815};
816
817I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
818
819
820
821
822
823struct i40e_aqc_add_update_pv {
824 __le16 command_flags;
825 __le16 uplink_seid;
826 __le16 connected_seid;
827 u8 reserved[10];
828};
829
830I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
831
832struct i40e_aqc_add_update_pv_completion {
833
834 __le16 pv_seid;
835 u8 reserved[14];
836};
837
838I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
839
840
841
842
843
844struct i40e_aqc_get_pv_params_completion {
845 __le16 seid;
846 __le16 default_stag;
847 __le16 pv_flags;
848 u8 reserved[8];
849 __le16 default_port_seid;
850};
851
852I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
853
854
855struct i40e_aqc_add_veb {
856 __le16 uplink_seid;
857 __le16 downlink_seid;
858 __le16 veb_flags;
859#define I40E_AQC_ADD_VEB_FLOATING 0x1
860#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
861#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
862#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
863 u8 enable_tcs;
864 u8 reserved[9];
865};
866
867I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
868
869struct i40e_aqc_add_veb_completion {
870 u8 reserved[6];
871 __le16 switch_seid;
872
873 __le16 veb_seid;
874 __le16 statistic_index;
875 __le16 vebs_used;
876 __le16 vebs_free;
877};
878
879I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
880
881
882
883
884struct i40e_aqc_get_veb_parameters_completion {
885 __le16 seid;
886 __le16 switch_id;
887 __le16 veb_flags;
888 __le16 statistic_index;
889 __le16 vebs_used;
890 __le16 vebs_free;
891 u8 reserved[4];
892};
893
894I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
895
896
897
898
899
900
901
902
903struct i40e_aqc_macvlan {
904 __le16 num_addresses;
905 __le16 seid[3];
906#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
907 __le32 addr_high;
908 __le32 addr_low;
909};
910
911I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
912
913
914struct i40e_aqc_add_macvlan_element_data {
915 u8 mac_addr[6];
916 __le16 vlan_tag;
917 __le16 flags;
918#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
919#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
920#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
921 __le16 queue_number;
922
923 u8 match_method;
924#define I40E_AQC_MM_ERR_NO_RES 0xFF
925 u8 reserved1[3];
926};
927
928struct i40e_aqc_add_remove_macvlan_completion {
929 __le16 perfect_mac_used;
930 __le16 perfect_mac_free;
931 __le16 unicast_hash_free;
932 __le16 multicast_hash_free;
933 __le32 addr_high;
934 __le32 addr_low;
935};
936
937I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
938
939
940
941
942
943
944struct i40e_aqc_remove_macvlan_element_data {
945 u8 mac_addr[6];
946 __le16 vlan_tag;
947 u8 flags;
948#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
949#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
950 u8 reserved[3];
951
952 u8 error_code;
953 u8 reply_reserved[3];
954};
955
956
957
958
959
960struct i40e_aqc_add_remove_vlan_element_data {
961 __le16 vlan_tag;
962 u8 vlan_flags;
963 u8 reserved;
964 u8 result;
965 u8 reserved1[3];
966};
967
968struct i40e_aqc_add_remove_vlan_completion {
969 u8 reserved[4];
970 __le16 vlans_used;
971 __le16 vlans_free;
972 __le32 addr_high;
973 __le32 addr_low;
974};
975
976
977struct i40e_aqc_set_vsi_promiscuous_modes {
978 __le16 promiscuous_flags;
979 __le16 valid_flags;
980
981#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
982#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
983#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
984#define I40E_AQC_SET_VSI_DEFAULT 0x08
985#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
986#define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
987 __le16 seid;
988 __le16 vlan_tag;
989#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
990 u8 reserved[8];
991};
992
993I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
994
995
996
997
998struct i40e_aqc_add_tag {
999 __le16 flags;
1000 __le16 seid;
1001 __le16 tag;
1002 __le16 queue_number;
1003 u8 reserved[8];
1004};
1005
1006I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1007
1008struct i40e_aqc_add_remove_tag_completion {
1009 u8 reserved[12];
1010 __le16 tags_used;
1011 __le16 tags_free;
1012};
1013
1014I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1015
1016
1017
1018
1019struct i40e_aqc_remove_tag {
1020 __le16 seid;
1021 __le16 tag;
1022 u8 reserved[12];
1023};
1024
1025I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1026
1027
1028
1029
1030
1031struct i40e_aqc_add_remove_mcast_etag {
1032 __le16 pv_seid;
1033 __le16 etag;
1034 u8 num_unicast_etags;
1035 u8 reserved[3];
1036 __le32 addr_high;
1037 __le32 addr_low;
1038};
1039
1040I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1041
1042struct i40e_aqc_add_remove_mcast_etag_completion {
1043 u8 reserved[4];
1044 __le16 mcast_etags_used;
1045 __le16 mcast_etags_free;
1046 __le32 addr_high;
1047 __le32 addr_low;
1048
1049};
1050
1051I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1052
1053
1054struct i40e_aqc_update_tag {
1055 __le16 seid;
1056 __le16 old_tag;
1057 __le16 new_tag;
1058 u8 reserved[10];
1059};
1060
1061I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1062
1063struct i40e_aqc_update_tag_completion {
1064 u8 reserved[12];
1065 __le16 tags_used;
1066 __le16 tags_free;
1067};
1068
1069I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1070
1071
1072
1073
1074
1075
1076struct i40e_aqc_add_remove_control_packet_filter {
1077 u8 mac[6];
1078 __le16 etype;
1079 __le16 flags;
1080#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1081#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1082#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1083 __le16 seid;
1084 __le16 queue;
1085 u8 reserved[2];
1086};
1087
1088I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1089
1090struct i40e_aqc_add_remove_control_packet_filter_completion {
1091 __le16 mac_etype_used;
1092 __le16 etype_used;
1093 __le16 mac_etype_free;
1094 __le16 etype_free;
1095 u8 reserved[8];
1096};
1097
1098I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1099
1100
1101
1102
1103
1104
1105struct i40e_aqc_add_remove_cloud_filters {
1106 u8 num_filters;
1107 u8 reserved;
1108 __le16 seid;
1109 u8 big_buffer_flag;
1110#define I40E_AQC_ADD_CLOUD_CMD_BB 1
1111 u8 reserved2[3];
1112 __le32 addr_high;
1113 __le32 addr_low;
1114};
1115
1116I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1117
1118struct i40e_aqc_cloud_filters_element_data {
1119 u8 outer_mac[6];
1120 u8 inner_mac[6];
1121 __le16 inner_vlan;
1122 union {
1123 struct {
1124 u8 reserved[12];
1125 u8 data[4];
1126 } v4;
1127 struct {
1128 u8 data[16];
1129 } v6;
1130 struct {
1131 __le16 data[8];
1132 } raw_v6;
1133 } ipaddr;
1134 __le16 flags;
1135
1136
1137
1138#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1139#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1140
1141#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1142
1143
1144#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1145#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1146#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1147#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1148
1149
1150
1151
1152#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010
1153#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011
1154#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012
1155
1156#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1157#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1158
1159#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1160#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1161#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1162
1163
1164 __le32 tenant_id;
1165 u8 reserved[4];
1166 __le16 queue_number;
1167 u8 reserved2[14];
1168
1169 u8 allocation_result;
1170 u8 response_reserved[7];
1171};
1172
1173I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1174
1175
1176
1177
1178struct i40e_aqc_cloud_filters_element_bb {
1179 struct i40e_aqc_cloud_filters_element_data element;
1180 u16 general_fields[32];
1181#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1182};
1183
1184I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1185
1186struct i40e_aqc_remove_cloud_filters_completion {
1187 __le16 perfect_ovlan_used;
1188 __le16 perfect_ovlan_free;
1189 __le16 vlan_used;
1190 __le16 vlan_free;
1191 __le32 addr_high;
1192 __le32 addr_low;
1193};
1194
1195I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1196
1197
1198
1199
1200
1201struct i40e_filter_data {
1202 u8 filter_type;
1203 u8 input[3];
1204};
1205
1206I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1207
1208struct i40e_aqc_replace_cloud_filters_cmd {
1209 u8 valid_flags;
1210 u8 old_filter_type;
1211 u8 new_filter_type;
1212 u8 tr_bit;
1213 u8 reserved[4];
1214 __le32 addr_high;
1215 __le32 addr_low;
1216};
1217
1218I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1219
1220struct i40e_aqc_replace_cloud_filters_cmd_buf {
1221 u8 data[32];
1222 struct i40e_filter_data filters[8];
1223};
1224
1225I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1226
1227
1228
1229
1230
1231
1232struct i40e_aqc_add_delete_mirror_rule {
1233 __le16 seid;
1234 __le16 rule_type;
1235#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1236#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1237 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1238#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1239#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1240#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1241 __le16 num_entries;
1242 __le16 destination;
1243 __le32 addr_high;
1244 __le32 addr_low;
1245};
1246
1247I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1248
1249struct i40e_aqc_add_delete_mirror_rule_completion {
1250 u8 reserved[2];
1251 __le16 rule_id;
1252 __le16 mirror_rules_used;
1253 __le16 mirror_rules_free;
1254 __le32 addr_high;
1255 __le32 addr_low;
1256};
1257
1258I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1259
1260
1261struct i40e_aqc_write_personalization_profile {
1262 u8 flags;
1263 u8 reserved[3];
1264 __le32 profile_track_id;
1265 __le32 addr_high;
1266 __le32 addr_low;
1267};
1268
1269I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1270
1271struct i40e_aqc_write_ddp_resp {
1272 __le32 error_offset;
1273 __le32 error_info;
1274 __le32 addr_high;
1275 __le32 addr_low;
1276};
1277
1278struct i40e_aqc_get_applied_profiles {
1279 u8 flags;
1280 u8 rsv[3];
1281 __le32 reserved;
1282 __le32 addr_high;
1283 __le32 addr_low;
1284};
1285
1286I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1287
1288
1289
1290
1291
1292
1293struct i40e_aqc_pfc_ignore {
1294 u8 tc_bitmap;
1295 u8 command_flags;
1296 u8 reserved[14];
1297};
1298
1299I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310struct i40e_aqc_tx_sched_ind {
1311 __le16 vsi_seid;
1312 u8 reserved[6];
1313 __le32 addr_high;
1314 __le32 addr_low;
1315};
1316
1317I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1318
1319
1320struct i40e_aqc_qs_handles_resp {
1321 __le16 qs_handles[8];
1322};
1323
1324
1325struct i40e_aqc_configure_vsi_bw_limit {
1326 __le16 vsi_seid;
1327 u8 reserved[2];
1328 __le16 credit;
1329 u8 reserved1[2];
1330 u8 max_credit;
1331 u8 reserved2[7];
1332};
1333
1334I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1335
1336
1337
1338
1339struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1340 u8 tc_valid_bits;
1341 u8 reserved[15];
1342 __le16 tc_bw_credits[8];
1343
1344
1345 __le16 tc_bw_max[2];
1346 u8 reserved1[28];
1347};
1348
1349I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1350
1351
1352
1353
1354struct i40e_aqc_configure_vsi_tc_bw_data {
1355 u8 tc_valid_bits;
1356 u8 reserved[3];
1357 u8 tc_bw_credits[8];
1358 u8 reserved1[4];
1359 __le16 qs_handles[8];
1360};
1361
1362I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1363
1364
1365struct i40e_aqc_query_vsi_bw_config_resp {
1366 u8 tc_valid_bits;
1367 u8 tc_suspended_bits;
1368 u8 reserved[14];
1369 __le16 qs_handles[8];
1370 u8 reserved1[4];
1371 __le16 port_bw_limit;
1372 u8 reserved2[2];
1373 u8 max_bw;
1374 u8 reserved3[23];
1375};
1376
1377I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1378
1379
1380struct i40e_aqc_query_vsi_ets_sla_config_resp {
1381 u8 tc_valid_bits;
1382 u8 reserved[3];
1383 u8 share_credits[8];
1384 __le16 credits[8];
1385
1386
1387 __le16 tc_bw_max[2];
1388};
1389
1390I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1391
1392
1393struct i40e_aqc_configure_switching_comp_bw_limit {
1394 __le16 seid;
1395 u8 reserved[2];
1396 __le16 credit;
1397 u8 reserved1[2];
1398 u8 max_bw;
1399 u8 reserved2[7];
1400};
1401
1402I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1403
1404
1405
1406
1407
1408struct i40e_aqc_configure_switching_comp_ets_data {
1409 u8 reserved[4];
1410 u8 tc_valid_bits;
1411 u8 seepage;
1412 u8 tc_strict_priority_flags;
1413 u8 reserved1[17];
1414 u8 tc_bw_share_credits[8];
1415 u8 reserved2[96];
1416};
1417
1418I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1419
1420
1421struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1422 u8 tc_valid_bits;
1423 u8 reserved[15];
1424 __le16 tc_bw_credit[8];
1425
1426
1427 __le16 tc_bw_max[2];
1428 u8 reserved1[28];
1429};
1430
1431I40E_CHECK_STRUCT_LEN(0x40,
1432 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1433
1434
1435
1436
1437struct i40e_aqc_configure_switching_comp_bw_config_data {
1438 u8 tc_valid_bits;
1439 u8 reserved[2];
1440 u8 absolute_credits;
1441 u8 tc_bw_share_credits[8];
1442 u8 reserved1[20];
1443};
1444
1445I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1446
1447
1448struct i40e_aqc_query_switching_comp_ets_config_resp {
1449 u8 tc_valid_bits;
1450 u8 reserved[35];
1451 __le16 port_bw_limit;
1452 u8 reserved1[2];
1453 u8 tc_bw_max;
1454 u8 reserved2[23];
1455};
1456
1457I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1458
1459
1460struct i40e_aqc_query_port_ets_config_resp {
1461 u8 reserved[4];
1462 u8 tc_valid_bits;
1463 u8 reserved1;
1464 u8 tc_strict_priority_bits;
1465 u8 reserved2;
1466 u8 tc_bw_share_credits[8];
1467 __le16 tc_bw_limits[8];
1468
1469
1470 __le16 tc_bw_max[2];
1471 u8 reserved3[32];
1472};
1473
1474I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1475
1476
1477
1478
1479struct i40e_aqc_query_switching_comp_bw_config_resp {
1480 u8 tc_valid_bits;
1481 u8 reserved[2];
1482 u8 absolute_credits_enable;
1483 u8 tc_bw_share_credits[8];
1484 __le16 tc_bw_limits[8];
1485
1486
1487 __le16 tc_bw_max[2];
1488};
1489
1490I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1491
1492
1493
1494
1495
1496
1497
1498
1499struct i40e_aqc_configure_partition_bw_data {
1500 __le16 pf_valid_bits;
1501 u8 min_bw[16];
1502 u8 max_bw[16];
1503};
1504
1505I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1506
1507
1508
1509
1510struct i40e_aq_get_set_hmc_resource_profile {
1511 u8 pm_profile;
1512 u8 pe_vf_enabled;
1513 u8 reserved[14];
1514};
1515
1516I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1517
1518enum i40e_aq_hmc_profile {
1519
1520 I40E_HMC_PROFILE_DEFAULT = 1,
1521 I40E_HMC_PROFILE_FAVOR_VF = 2,
1522 I40E_HMC_PROFILE_EQUAL = 3,
1523};
1524
1525
1526
1527
1528#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1529#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1530
1531enum i40e_aq_phy_type {
1532 I40E_PHY_TYPE_SGMII = 0x0,
1533 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1534 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1535 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1536 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1537 I40E_PHY_TYPE_XAUI = 0x5,
1538 I40E_PHY_TYPE_XFI = 0x6,
1539 I40E_PHY_TYPE_SFI = 0x7,
1540 I40E_PHY_TYPE_XLAUI = 0x8,
1541 I40E_PHY_TYPE_XLPPI = 0x9,
1542 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1543 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1544 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1545 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1546 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1547 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1548 I40E_PHY_TYPE_100BASE_TX = 0x11,
1549 I40E_PHY_TYPE_1000BASE_T = 0x12,
1550 I40E_PHY_TYPE_10GBASE_T = 0x13,
1551 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1552 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1553 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1554 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1555 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1556 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1557 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1558 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1559 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1560 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1561 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1562 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1563 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1564 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1565 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1566 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1567 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1568 I40E_PHY_TYPE_2_5GBASE_T = 0x30,
1569 I40E_PHY_TYPE_5GBASE_T = 0x31,
1570 I40E_PHY_TYPE_MAX,
1571 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1572 I40E_PHY_TYPE_EMPTY = 0xFE,
1573 I40E_PHY_TYPE_DEFAULT = 0xFF,
1574};
1575
1576#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1577 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1578 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1579 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1580 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1581 BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1582 BIT_ULL(I40E_PHY_TYPE_XFI) | \
1583 BIT_ULL(I40E_PHY_TYPE_SFI) | \
1584 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1585 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1586 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1587 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1588 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1589 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1590 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1591 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1592 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1593 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1594 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1595 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1596 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1597 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1598 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1599 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1600 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1601 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1602 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1603 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1604 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1605 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1606 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1607 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1608 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1609 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1610 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1611 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1612 BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1613 BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1614
1615#define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
1616#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1617#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1618#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1619#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1620#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1621#define I40E_LINK_SPEED_25GB_SHIFT 0x6
1622#define I40E_LINK_SPEED_5GB_SHIFT 0x7
1623
1624enum i40e_aq_link_speed {
1625 I40E_LINK_SPEED_UNKNOWN = 0,
1626 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1627 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1628 I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1629 I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT),
1630 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1631 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1632 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1633 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1634};
1635
1636struct i40e_aqc_module_desc {
1637 u8 oui[3];
1638 u8 reserved1;
1639 u8 part_number[16];
1640 u8 revision[4];
1641 u8 reserved2[8];
1642};
1643
1644I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1645
1646struct i40e_aq_get_phy_abilities_resp {
1647 __le32 phy_type;
1648 u8 link_speed;
1649 u8 abilities;
1650#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1651#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1652 __le16 eee_capability;
1653 __le32 eeer_val;
1654 u8 d3_lpan;
1655 u8 phy_type_ext;
1656#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1657#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1658#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1659#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1660 u8 fec_cfg_curr_mod_ext_info;
1661#define I40E_AQ_REQUEST_FEC_KR 0x04
1662#define I40E_AQ_REQUEST_FEC_RS 0x08
1663#define I40E_AQ_ENABLE_FEC_AUTO 0x10
1664
1665 u8 ext_comp_code;
1666 u8 phy_id[4];
1667 u8 module_type[3];
1668 u8 qualified_module_count;
1669#define I40E_AQ_PHY_MAX_QMS 16
1670 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1671};
1672
1673I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1674
1675
1676struct i40e_aq_set_phy_config {
1677 __le32 phy_type;
1678 u8 link_speed;
1679 u8 abilities;
1680
1681#define I40E_AQ_PHY_ENABLE_LINK 0x08
1682#define I40E_AQ_PHY_ENABLE_AN 0x10
1683#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1684 __le16 eee_capability;
1685 __le32 eeer;
1686 u8 low_power_ctrl;
1687 u8 phy_type_ext;
1688#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1689#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1690#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1691#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1692 u8 fec_config;
1693#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1694#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1695#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1696#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1697#define I40E_AQ_SET_FEC_AUTO BIT(4)
1698#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1699#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1700 u8 reserved;
1701};
1702
1703I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1704
1705
1706struct i40e_aq_set_mac_config {
1707 __le16 max_frame_size;
1708 u8 params;
1709 u8 tx_timer_priority;
1710 __le16 tx_timer_value;
1711 __le16 fc_refresh_threshold;
1712 u8 reserved[8];
1713};
1714
1715I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1716
1717
1718struct i40e_aqc_set_link_restart_an {
1719 u8 command;
1720#define I40E_AQ_PHY_RESTART_AN 0x02
1721#define I40E_AQ_PHY_LINK_ENABLE 0x04
1722 u8 reserved[15];
1723};
1724
1725I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1726
1727
1728struct i40e_aqc_get_link_status {
1729 __le16 command_flags;
1730#define I40E_AQ_LSE_DISABLE 0x2
1731#define I40E_AQ_LSE_ENABLE 0x3
1732
1733#define I40E_AQ_LSE_IS_ENABLED 0x1
1734 u8 phy_type;
1735 u8 link_speed;
1736 u8 link_info;
1737#define I40E_AQ_LINK_UP 0x01
1738#define I40E_AQ_MEDIA_AVAILABLE 0x40
1739 u8 an_info;
1740#define I40E_AQ_AN_COMPLETED 0x01
1741#define I40E_AQ_LINK_PAUSE_TX 0x20
1742#define I40E_AQ_LINK_PAUSE_RX 0x40
1743#define I40E_AQ_QUALIFIED_MODULE 0x80
1744 u8 ext_info;
1745 u8 loopback;
1746
1747#define I40E_AQ_LOOPBACK_MASK 0x07
1748 __le16 max_frame_size;
1749 u8 config;
1750#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1751#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1752#define I40E_AQ_CONFIG_CRC_ENA 0x04
1753#define I40E_AQ_CONFIG_PACING_MASK 0x78
1754 union {
1755 struct {
1756 u8 power_desc;
1757 u8 reserved[4];
1758 };
1759 struct {
1760 u8 link_type[4];
1761 u8 link_type_ext;
1762 };
1763 };
1764};
1765
1766I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1767
1768
1769struct i40e_aqc_set_phy_int_mask {
1770 u8 reserved[8];
1771 __le16 event_mask;
1772#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1773#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1774#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1775 u8 reserved1[6];
1776};
1777
1778I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1779
1780
1781
1782
1783
1784struct i40e_aqc_an_advt_reg {
1785 __le32 local_an_reg0;
1786 __le16 local_an_reg1;
1787 u8 reserved[10];
1788};
1789
1790I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1791
1792
1793struct i40e_aqc_set_lb_mode {
1794 __le16 lb_mode;
1795#define I40E_AQ_LB_PHY_LOCAL 0x01
1796#define I40E_AQ_LB_PHY_REMOTE 0x02
1797#define I40E_AQ_LB_MAC_LOCAL 0x04
1798 u8 reserved[14];
1799};
1800
1801I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1802
1803
1804struct i40e_aqc_set_phy_debug {
1805 u8 command_flags;
1806
1807#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1808
1809#define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1810 u8 reserved[15];
1811};
1812
1813I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1814
1815enum i40e_aq_phy_reg_type {
1816 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1817 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1818 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1819};
1820
1821
1822struct i40e_aqc_run_phy_activity {
1823 __le16 activity_id;
1824 u8 flags;
1825 u8 reserved1;
1826 __le32 control;
1827 __le32 data;
1828 u8 reserved2[4];
1829};
1830
1831I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1832
1833
1834
1835struct i40e_aqc_phy_register_access {
1836 u8 phy_interface;
1837#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
1838#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
1839 u8 dev_address;
1840 u8 cmd_flags;
1841#define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
1842#define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
1843#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT 2
1844#define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
1845 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
1846 u8 reserved1;
1847 __le32 reg_address;
1848 __le32 reg_value;
1849 u8 reserved2[4];
1850};
1851
1852I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
1853
1854
1855
1856
1857
1858struct i40e_aqc_nvm_update {
1859 u8 command_flags;
1860#define I40E_AQ_NVM_LAST_CMD 0x01
1861#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
1862#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
1863#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
1864#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
1865#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
1866 u8 module_pointer;
1867 __le16 length;
1868 __le32 offset;
1869 __le32 addr_high;
1870 __le32 addr_low;
1871};
1872
1873I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1874
1875
1876struct i40e_aqc_nvm_config_read {
1877 __le16 cmd_flags;
1878 __le16 element_count;
1879 __le16 element_id;
1880 __le16 element_id_msw;
1881 __le32 address_high;
1882 __le32 address_low;
1883};
1884
1885I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1886
1887
1888struct i40e_aqc_nvm_config_write {
1889 __le16 cmd_flags;
1890 __le16 element_count;
1891 u8 reserved[4];
1892 __le32 address_high;
1893 __le32 address_low;
1894};
1895
1896I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1897
1898
1899struct i40e_aqc_nvm_config_data_feature {
1900 __le16 feature_id;
1901 __le16 feature_options;
1902 __le16 feature_selection;
1903};
1904
1905I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1906
1907struct i40e_aqc_nvm_config_data_immediate_field {
1908 __le32 field_id;
1909 __le32 field_value;
1910 __le16 field_options;
1911 __le16 reserved;
1912};
1913
1914I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1915
1916
1917
1918
1919struct i40e_aqc_nvm_oem_post_update {
1920 u8 sel_data;
1921 u8 reserved[7];
1922};
1923
1924I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1925
1926struct i40e_aqc_nvm_oem_post_update_buffer {
1927 u8 str_len;
1928 u8 dev_addr;
1929 __le16 eeprom_addr;
1930 u8 data[36];
1931};
1932
1933I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1934
1935
1936
1937
1938
1939struct i40e_aqc_thermal_sensor {
1940 u8 sensor_action;
1941 u8 reserved[7];
1942 __le32 addr_high;
1943 __le32 addr_low;
1944};
1945
1946I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1947
1948
1949
1950
1951
1952struct i40e_aqc_pf_vf_message {
1953 __le32 id;
1954 u8 reserved[4];
1955 __le32 addr_high;
1956 __le32 addr_low;
1957};
1958
1959I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1960
1961
1962
1963
1964
1965
1966struct i40e_aqc_alternate_write {
1967 __le32 address0;
1968 __le32 data0;
1969 __le32 address1;
1970 __le32 data1;
1971};
1972
1973I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1974
1975
1976
1977
1978
1979struct i40e_aqc_alternate_ind_write {
1980 __le32 address;
1981 __le32 length;
1982 __le32 addr_high;
1983 __le32 addr_low;
1984};
1985
1986I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1987
1988
1989
1990
1991struct i40e_aqc_alternate_write_done {
1992 __le16 cmd_flags;
1993 u8 reserved[14];
1994};
1995
1996I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1997
1998
1999struct i40e_aqc_alternate_set_mode {
2000 __le32 mode;
2001 u8 reserved[12];
2002};
2003
2004I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2005
2006
2007
2008
2009
2010
2011struct i40e_aqc_lan_overflow {
2012 __le32 prtdcb_rupto;
2013 __le32 otx_ctl;
2014 u8 reserved[8];
2015};
2016
2017I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2018
2019
2020struct i40e_aqc_lldp_get_mib {
2021 u8 type;
2022 u8 reserved1;
2023#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2024#define I40E_AQ_LLDP_MIB_LOCAL 0x0
2025#define I40E_AQ_LLDP_MIB_REMOTE 0x1
2026#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2027#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2028#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2029
2030 __le16 local_len;
2031 __le16 remote_len;
2032 u8 reserved2[2];
2033 __le32 addr_high;
2034 __le32 addr_low;
2035};
2036
2037I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2038
2039
2040
2041
2042struct i40e_aqc_lldp_update_mib {
2043 u8 command;
2044#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2045 u8 reserved[7];
2046 __le32 addr_high;
2047 __le32 addr_low;
2048};
2049
2050I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2051
2052
2053
2054
2055struct i40e_aqc_lldp_add_tlv {
2056 u8 type;
2057 u8 reserved1[1];
2058 __le16 len;
2059 u8 reserved2[4];
2060 __le32 addr_high;
2061 __le32 addr_low;
2062};
2063
2064I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2065
2066
2067struct i40e_aqc_lldp_update_tlv {
2068 u8 type;
2069 u8 reserved;
2070 __le16 old_len;
2071 __le16 new_offset;
2072 __le16 new_len;
2073 __le32 addr_high;
2074 __le32 addr_low;
2075};
2076
2077I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2078
2079
2080struct i40e_aqc_lldp_stop {
2081 u8 command;
2082#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2083#define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
2084 u8 reserved[15];
2085};
2086
2087I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2088
2089
2090struct i40e_aqc_lldp_start {
2091 u8 command;
2092#define I40E_AQ_LLDP_AGENT_START 0x1
2093#define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
2094 u8 reserved[15];
2095};
2096
2097I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2098
2099
2100struct i40e_aqc_set_dcb_parameters {
2101 u8 command;
2102#define I40E_AQ_DCB_SET_AGENT 0x1
2103#define I40E_DCB_VALID 0x1
2104 u8 valid_flags;
2105 u8 reserved[14];
2106};
2107
2108I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2109
2110
2111
2112
2113
2114
2115#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2116#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2117#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2118#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2119#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2120#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2121
2122#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2123#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2124#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2125#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2126#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2127#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2128#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2129#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2130#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2131#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2132#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2133#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2144 u8 reserved1;
2145 u8 oper_num_tc;
2146 u8 oper_prio_tc[4];
2147 u8 reserved2;
2148 u8 oper_tc_bw[8];
2149 u8 oper_pfc_en;
2150 u8 reserved3[2];
2151 __le16 oper_app_prio;
2152 u8 reserved4[2];
2153 __le16 tlv_status;
2154};
2155
2156I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2157
2158struct i40e_aqc_get_cee_dcb_cfg_resp {
2159 u8 oper_num_tc;
2160 u8 oper_prio_tc[4];
2161 u8 oper_tc_bw[8];
2162 u8 oper_pfc_en;
2163 __le16 oper_app_prio;
2164#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2165#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2166#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2167#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2168#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2169#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2170#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2171 __le32 tlv_status;
2172#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2173#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2174#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2175#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2176#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2177#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2178 u8 reserved[12];
2179};
2180
2181I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2182
2183
2184
2185
2186struct i40e_aqc_lldp_set_local_mib {
2187 u8 type;
2188 u8 reserved0;
2189 __le16 length;
2190 u8 reserved1[4];
2191 __le32 address_high;
2192 __le32 address_low;
2193};
2194
2195I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2196
2197
2198
2199
2200struct i40e_aqc_lldp_stop_start_specific_agent {
2201 u8 command;
2202 u8 reserved[15];
2203};
2204
2205I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2206
2207
2208struct i40e_aqc_lldp_restore {
2209 u8 command;
2210#define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2211 u8 reserved[15];
2212};
2213
2214I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2215
2216
2217struct i40e_aqc_add_udp_tunnel {
2218 __le16 udp_port;
2219 u8 reserved0[3];
2220 u8 protocol_type;
2221#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2222#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2223 u8 reserved1[10];
2224};
2225
2226I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2227
2228struct i40e_aqc_add_udp_tunnel_completion {
2229 __le16 udp_port;
2230 u8 filter_entry_index;
2231 u8 multiple_pfs;
2232 u8 total_filters;
2233 u8 reserved[11];
2234};
2235
2236I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2237
2238
2239struct i40e_aqc_remove_udp_tunnel {
2240 u8 reserved[2];
2241 u8 index;
2242 u8 reserved2[13];
2243};
2244
2245I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2246
2247struct i40e_aqc_del_udp_tunnel_completion {
2248 __le16 udp_port;
2249 u8 index;
2250 u8 multiple_pfs;
2251 u8 total_filters_used;
2252 u8 reserved1[11];
2253};
2254
2255I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2256
2257struct i40e_aqc_get_set_rss_key {
2258#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2259#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2260#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2261 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2262 __le16 vsi_id;
2263 u8 reserved[6];
2264 __le32 addr_high;
2265 __le32 addr_low;
2266};
2267
2268I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2269
2270struct i40e_aqc_get_set_rss_key_data {
2271 u8 standard_rss_key[0x28];
2272 u8 extended_hash_key[0xc];
2273};
2274
2275I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2276
2277struct i40e_aqc_get_set_rss_lut {
2278#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2279#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2280#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2281 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2282 __le16 vsi_id;
2283#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2284#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2285
2286#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2287#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2288 __le16 flags;
2289 u8 reserved[4];
2290 __le32 addr_high;
2291 __le32 addr_low;
2292};
2293
2294I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2295
2296
2297
2298struct i40e_aqc_tunnel_key_structure {
2299 u8 key1_off;
2300 u8 key2_off;
2301 u8 key1_len;
2302 u8 key2_len;
2303 u8 flags;
2304 u8 network_key_index;
2305 u8 reserved[10];
2306};
2307
2308I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2309
2310
2311struct i40e_aqc_oem_param_change {
2312 __le32 param_type;
2313 __le32 param_value1;
2314 __le16 param_value2;
2315 u8 reserved[6];
2316};
2317
2318I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2319
2320struct i40e_aqc_oem_state_change {
2321 __le32 state;
2322 u8 reserved[12];
2323};
2324
2325I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2326
2327
2328struct i40e_aqc_opc_oem_ocsd_initialize {
2329 u8 type_status;
2330 u8 reserved1[3];
2331 __le32 ocsd_memory_block_addr_high;
2332 __le32 ocsd_memory_block_addr_low;
2333 __le32 requested_update_interval;
2334};
2335
2336I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2337
2338
2339struct i40e_aqc_opc_oem_ocbb_initialize {
2340 u8 type_status;
2341 u8 reserved1[3];
2342 __le32 ocbb_memory_block_addr_high;
2343 __le32 ocbb_memory_block_addr_low;
2344 u8 reserved2[4];
2345};
2346
2347I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2348
2349
2350
2351
2352
2353
2354
2355struct i40e_acq_set_test_mode {
2356 u8 mode;
2357 u8 reserved[3];
2358 u8 command;
2359 u8 reserved2[3];
2360 __le32 address_high;
2361 __le32 address_low;
2362};
2363
2364I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2365
2366
2367
2368
2369struct i40e_aqc_debug_reg_read_write {
2370 __le32 reserved;
2371 __le32 address;
2372 __le32 value_high;
2373 __le32 value_low;
2374};
2375
2376I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2377
2378
2379
2380
2381
2382
2383struct i40e_aqc_debug_reg_sg_element_data {
2384 __le32 address;
2385 __le32 value;
2386};
2387
2388
2389struct i40e_aqc_debug_modify_reg {
2390 __le32 address;
2391 __le32 value;
2392 __le32 clear_mask;
2393 __le32 set_mask;
2394};
2395
2396I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2397
2398
2399struct i40e_aqc_debug_dump_internals {
2400 u8 cluster_id;
2401 u8 table_id;
2402 __le16 data_size;
2403 __le32 idx;
2404 __le32 address_high;
2405 __le32 address_low;
2406};
2407
2408I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2409
2410struct i40e_aqc_debug_modify_internals {
2411 u8 cluster_id;
2412 u8 cluster_specific_params[7];
2413 __le32 address_high;
2414 __le32 address_low;
2415};
2416
2417I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2418
2419#endif
2420