linux/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4#include "ixgbe.h"
   5#include <linux/ptp_classify.h>
   6#include <linux/clocksource.h>
   7
   8/*
   9 * The 82599 and the X540 do not have true 64bit nanosecond scale
  10 * counter registers. Instead, SYSTIME is defined by a fixed point
  11 * system which allows the user to define the scale counter increment
  12 * value at every level change of the oscillator driving the SYSTIME
  13 * value. For both devices the TIMINCA:IV field defines this
  14 * increment. On the X540 device, 31 bits are provided. However on the
  15 * 82599 only provides 24 bits. The time unit is determined by the
  16 * clock frequency of the oscillator in combination with the TIMINCA
  17 * register. When these devices link at 10Gb the oscillator has a
  18 * period of 6.4ns. In order to convert the scale counter into
  19 * nanoseconds the cyclecounter and timecounter structures are
  20 * used. The SYSTIME registers need to be converted to ns values by use
  21 * of only a right shift (division by power of 2). The following math
  22 * determines the largest incvalue that will fit into the available
  23 * bits in the TIMINCA register.
  24 *
  25 * PeriodWidth: Number of bits to store the clock period
  26 * MaxWidth: The maximum width value of the TIMINCA register
  27 * Period: The clock period for the oscillator
  28 * round(): discard the fractional portion of the calculation
  29 *
  30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
  31 *
  32 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
  33 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
  34 *
  35 * The period also changes based on the link speed:
  36 * At 10Gb link or no link, the period remains the same.
  37 * At 1Gb link, the period is multiplied by 10. (64ns)
  38 * At 100Mb link, the period is multiplied by 100. (640ns)
  39 *
  40 * The calculated value allows us to right shift the SYSTIME register
  41 * value in order to quickly convert it into a nanosecond clock,
  42 * while allowing for the maximum possible adjustment value.
  43 *
  44 * These diagrams are only for the 10Gb link period
  45 *
  46 *           SYSTIMEH            SYSTIMEL
  47 *       +--------------+  +--------------+
  48 * X540  |      32      |  | 1 | 3 |  28  |
  49 *       *--------------+  +--------------+
  50 *        \________ 36 bits ______/  fract
  51 *
  52 *       +--------------+  +--------------+
  53 * 82599 |      32      |  | 8 | 3 |  21  |
  54 *       *--------------+  +--------------+
  55 *        \________ 43 bits ______/  fract
  56 *
  57 * The 36 bit X540 SYSTIME overflows every
  58 *   2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
  59 *
  60 * The 43 bit 82599 SYSTIME overflows every
  61 *   2^43 * 10^-9 / 3600 = 2.4 hours
  62 */
  63#define IXGBE_INCVAL_10GB 0x66666666
  64#define IXGBE_INCVAL_1GB  0x40000000
  65#define IXGBE_INCVAL_100  0x50000000
  66
  67#define IXGBE_INCVAL_SHIFT_10GB  28
  68#define IXGBE_INCVAL_SHIFT_1GB   24
  69#define IXGBE_INCVAL_SHIFT_100   21
  70
  71#define IXGBE_INCVAL_SHIFT_82599 7
  72#define IXGBE_INCPER_SHIFT_82599 24
  73
  74#define IXGBE_OVERFLOW_PERIOD    (HZ * 30)
  75#define IXGBE_PTP_TX_TIMEOUT     (HZ)
  76
  77/* We use our own definitions instead of NSEC_PER_SEC because we want to mark
  78 * the value as a ULL to force precision when bit shifting.
  79 */
  80#define NS_PER_SEC      1000000000ULL
  81#define NS_PER_HALF_SEC  500000000ULL
  82
  83/* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL
  84 * which contain measurements of seconds and nanoseconds respectively. This
  85 * matches the standard linux representation of time in the kernel. In addition,
  86 * the X550 also has a SYSTIMER register which represents residue, or
  87 * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA
  88 * register is used, but it is unlike the X540 and 82599 devices. TIMINCA
  89 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
  90 * high bit representing whether the adjustent is positive or negative. Every
  91 * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range
  92 * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the
  93 * X550's clock for purposes of SYSTIME generation is constant and not dependent
  94 * on the link speed.
  95 *
  96 *           SYSTIMEH           SYSTIMEL        SYSTIMER
  97 *       +--------------+  +--------------+  +-------------+
  98 * X550  |      32      |  |      32      |  |     32      |
  99 *       *--------------+  +--------------+  +-------------+
 100 *       \____seconds___/   \_nanoseconds_/  \__2^-32 ns__/
 101 *
 102 * This results in a full 96 bits to represent the clock, with 32 bits for
 103 * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under
 104 * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for
 105 * underflow of adjustments.
 106 *
 107 * The 32 bits of seconds for the X550 overflows every
 108 *   2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years.
 109 *
 110 * In order to adjust the clock frequency for the X550, the TIMINCA register is
 111 * provided. This register represents a + or minus nearly 0.5 ns adjustment to
 112 * the base frequency. It is measured in 2^-32 ns units, with the high bit being
 113 * the sign bit. This register enables software to calculate frequency
 114 * adjustments and apply them directly to the clock rate.
 115 *
 116 * The math for converting ppb into TIMINCA values is fairly straightforward.
 117 *   TIMINCA value = ( Base_Frequency * ppb ) / 1000000000ULL
 118 *
 119 * This assumes that ppb is never high enough to create a value bigger than
 120 * TIMINCA's 31 bits can store. This is ensured by the stack. Calculating this
 121 * value is also simple.
 122 *   Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL
 123 *
 124 * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is
 125 * 12.5 nanoseconds. This means that the Max ppb is 39999999
 126 *   Note: We subtract one in order to ensure no overflow, because the TIMINCA
 127 *         register can only hold slightly under 0.5 nanoseconds.
 128 *
 129 * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns
 130 * into 2^-32 units, which is
 131 *
 132 *  12.5 * 2^32 = C80000000
 133 *
 134 * Some revisions of hardware have a faster base frequency than the registers
 135 * were defined for. To fix this, we use a timecounter structure with the
 136 * proper mult and shift to convert the cycles into nanoseconds of time.
 137 */
 138#define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
 139#define INCVALUE_MASK   0x7FFFFFFF
 140#define ISGN            0x80000000
 141#define MAX_TIMADJ      0x7FFFFFFF
 142
 143/**
 144 * ixgbe_ptp_setup_sdp_X540
 145 * @adapter: private adapter structure
 146 *
 147 * this function enables or disables the clock out feature on SDP0 for
 148 * the X540 device. It will create a 1 second periodic output that can
 149 * be used as the PPS (via an interrupt).
 150 *
 151 * It calculates when the system time will be on an exact second, and then
 152 * aligns the start of the PPS signal to that value.
 153 *
 154 * This works by using the cycle counter shift and mult values in reverse, and
 155 * assumes that the values we're shifting will not overflow.
 156 */
 157static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)
 158{
 159        struct cyclecounter *cc = &adapter->hw_cc;
 160        struct ixgbe_hw *hw = &adapter->hw;
 161        u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
 162        u64 ns = 0, clock_edge = 0, clock_period;
 163        unsigned long flags;
 164
 165        /* disable the pin first */
 166        IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 167        IXGBE_WRITE_FLUSH(hw);
 168
 169        if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
 170                return;
 171
 172        esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 173
 174        /* enable the SDP0 pin as output, and connected to the
 175         * native function for Timesync (ClockOut)
 176         */
 177        esdp |= IXGBE_ESDP_SDP0_DIR |
 178                IXGBE_ESDP_SDP0_NATIVE;
 179
 180        /* enable the Clock Out feature on SDP0, and allow
 181         * interrupts to occur when the pin changes
 182         */
 183        tsauxc = (IXGBE_TSAUXC_EN_CLK |
 184                  IXGBE_TSAUXC_SYNCLK |
 185                  IXGBE_TSAUXC_SDP0_INT);
 186
 187        /* Determine the clock time period to use. This assumes that the
 188         * cycle counter shift is small enough to avoid overflow.
 189         */
 190        clock_period = div_u64((NS_PER_HALF_SEC << cc->shift), cc->mult);
 191        clktiml = (u32)(clock_period);
 192        clktimh = (u32)(clock_period >> 32);
 193
 194        /* Read the current clock time, and save the cycle counter value */
 195        spin_lock_irqsave(&adapter->tmreg_lock, flags);
 196        ns = timecounter_read(&adapter->hw_tc);
 197        clock_edge = adapter->hw_tc.cycle_last;
 198        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 199
 200        /* Figure out how many seconds to add in order to round up */
 201        div_u64_rem(ns, NS_PER_SEC, &rem);
 202
 203        /* Figure out how many nanoseconds to add to round the clock edge up
 204         * to the next full second
 205         */
 206        rem = (NS_PER_SEC - rem);
 207
 208        /* Adjust the clock edge to align with the next full second. */
 209        clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
 210        trgttiml = (u32)clock_edge;
 211        trgttimh = (u32)(clock_edge >> 32);
 212
 213        IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
 214        IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
 215        IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 216        IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 217
 218        IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 219        IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 220
 221        IXGBE_WRITE_FLUSH(hw);
 222}
 223
 224/**
 225 * ixgbe_ptp_setup_sdp_X550
 226 * @adapter: private adapter structure
 227 *
 228 * Enable or disable a clock output signal on SDP 0 for X550 hardware.
 229 *
 230 * Use the target time feature to align the output signal on the next full
 231 * second.
 232 *
 233 * This works by using the cycle counter shift and mult values in reverse, and
 234 * assumes that the values we're shifting will not overflow.
 235 */
 236static void ixgbe_ptp_setup_sdp_X550(struct ixgbe_adapter *adapter)
 237{
 238        u32 esdp, tsauxc, freqout, trgttiml, trgttimh, rem, tssdp;
 239        struct cyclecounter *cc = &adapter->hw_cc;
 240        struct ixgbe_hw *hw = &adapter->hw;
 241        u64 ns = 0, clock_edge = 0;
 242        struct timespec64 ts;
 243        unsigned long flags;
 244
 245        /* disable the pin first */
 246        IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 247        IXGBE_WRITE_FLUSH(hw);
 248
 249        if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
 250                return;
 251
 252        esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 253
 254        /* enable the SDP0 pin as output, and connected to the
 255         * native function for Timesync (ClockOut)
 256         */
 257        esdp |= IXGBE_ESDP_SDP0_DIR |
 258                IXGBE_ESDP_SDP0_NATIVE;
 259
 260        /* enable the Clock Out feature on SDP0, and use Target Time 0 to
 261         * enable generation of interrupts on the clock change.
 262         */
 263#define IXGBE_TSAUXC_DIS_TS_CLEAR 0x40000000
 264        tsauxc = (IXGBE_TSAUXC_EN_CLK | IXGBE_TSAUXC_ST0 |
 265                  IXGBE_TSAUXC_EN_TT0 | IXGBE_TSAUXC_SDP0_INT |
 266                  IXGBE_TSAUXC_DIS_TS_CLEAR);
 267
 268        tssdp = (IXGBE_TSSDP_TS_SDP0_EN |
 269                 IXGBE_TSSDP_TS_SDP0_CLK0);
 270
 271        /* Determine the clock time period to use. This assumes that the
 272         * cycle counter shift is small enough to avoid overflowing a 32bit
 273         * value.
 274         */
 275        freqout = div_u64(NS_PER_HALF_SEC << cc->shift,  cc->mult);
 276
 277        /* Read the current clock time, and save the cycle counter value */
 278        spin_lock_irqsave(&adapter->tmreg_lock, flags);
 279        ns = timecounter_read(&adapter->hw_tc);
 280        clock_edge = adapter->hw_tc.cycle_last;
 281        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 282
 283        /* Figure out how far past the next second we are */
 284        div_u64_rem(ns, NS_PER_SEC, &rem);
 285
 286        /* Figure out how many nanoseconds to add to round the clock edge up
 287         * to the next full second
 288         */
 289        rem = (NS_PER_SEC - rem);
 290
 291        /* Adjust the clock edge to align with the next full second. */
 292        clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
 293
 294        /* X550 hardware stores the time in 32bits of 'billions of cycles' and
 295         * 32bits of 'cycles'. There's no guarantee that cycles represents
 296         * nanoseconds. However, we can use the math from a timespec64 to
 297         * convert into the hardware representation.
 298         *
 299         * See ixgbe_ptp_read_X550() for more details.
 300         */
 301        ts = ns_to_timespec64(clock_edge);
 302        trgttiml = (u32)ts.tv_nsec;
 303        trgttimh = (u32)ts.tv_sec;
 304
 305        IXGBE_WRITE_REG(hw, IXGBE_FREQOUT0, freqout);
 306        IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 307        IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 308
 309        IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 310        IXGBE_WRITE_REG(hw, IXGBE_TSSDP, tssdp);
 311        IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 312
 313        IXGBE_WRITE_FLUSH(hw);
 314}
 315
 316/**
 317 * ixgbe_ptp_read_X550 - read cycle counter value
 318 * @cc: cyclecounter structure
 319 *
 320 * This function reads SYSTIME registers. It is called by the cyclecounter
 321 * structure to convert from internal representation into nanoseconds. We need
 322 * this for X550 since some skews do not have expected clock frequency and
 323 * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of
 324 * "cycles", rather than seconds and nanoseconds.
 325 */
 326static u64 ixgbe_ptp_read_X550(const struct cyclecounter *cc)
 327{
 328        struct ixgbe_adapter *adapter =
 329                container_of(cc, struct ixgbe_adapter, hw_cc);
 330        struct ixgbe_hw *hw = &adapter->hw;
 331        struct timespec64 ts;
 332
 333        /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'.
 334         * Some revisions of hardware run at a higher frequency and so the
 335         * cycles are not guaranteed to be nanoseconds. The timespec64 created
 336         * here is used for its math/conversions but does not necessarily
 337         * represent nominal time.
 338         *
 339         * It should be noted that this cyclecounter will overflow at a
 340         * non-bitmask field since we have to convert our billions of cycles
 341         * into an actual cycles count. This results in some possible weird
 342         * situations at high cycle counter stamps. However given that 32 bits
 343         * of "seconds" is ~138 years this isn't a problem. Even at the
 344         * increased frequency of some revisions, this is still ~103 years.
 345         * Since the SYSTIME values start at 0 and we never write them, it is
 346         * highly unlikely for the cyclecounter to overflow in practice.
 347         */
 348        IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
 349        ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 350        ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
 351
 352        return (u64)timespec64_to_ns(&ts);
 353}
 354
 355/**
 356 * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter)
 357 * @cc: the cyclecounter structure
 358 *
 359 * this function reads the cyclecounter registers and is called by the
 360 * cyclecounter structure used to construct a ns counter from the
 361 * arbitrary fixed point registers
 362 */
 363static u64 ixgbe_ptp_read_82599(const struct cyclecounter *cc)
 364{
 365        struct ixgbe_adapter *adapter =
 366                container_of(cc, struct ixgbe_adapter, hw_cc);
 367        struct ixgbe_hw *hw = &adapter->hw;
 368        u64 stamp = 0;
 369
 370        stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 371        stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 372
 373        return stamp;
 374}
 375
 376/**
 377 * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp
 378 * @adapter: private adapter structure
 379 * @hwtstamp: stack timestamp structure
 380 * @timestamp: unsigned 64bit system time value
 381 *
 382 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
 383 * which can be used by the stack's ptp functions.
 384 *
 385 * The lock is used to protect consistency of the cyclecounter and the SYSTIME
 386 * registers. However, it does not need to protect against the Rx or Tx
 387 * timestamp registers, as there can't be a new timestamp until the old one is
 388 * unlatched by reading.
 389 *
 390 * In addition to the timestamp in hardware, some controllers need a software
 391 * overflow cyclecounter, and this function takes this into account as well.
 392 **/
 393static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
 394                                          struct skb_shared_hwtstamps *hwtstamp,
 395                                          u64 timestamp)
 396{
 397        unsigned long flags;
 398        struct timespec64 systime;
 399        u64 ns;
 400
 401        memset(hwtstamp, 0, sizeof(*hwtstamp));
 402
 403        switch (adapter->hw.mac.type) {
 404        /* X550 and later hardware supposedly represent time using a seconds
 405         * and nanoseconds counter, instead of raw 64bits nanoseconds. We need
 406         * to convert the timestamp into cycles before it can be fed to the
 407         * cyclecounter. We need an actual cyclecounter because some revisions
 408         * of hardware run at a higher frequency and thus the counter does
 409         * not represent seconds/nanoseconds. Instead it can be thought of as
 410         * cycles and billions of cycles.
 411         */
 412        case ixgbe_mac_X550:
 413        case ixgbe_mac_X550EM_x:
 414        case ixgbe_mac_x550em_a:
 415                /* Upper 32 bits represent billions of cycles, lower 32 bits
 416                 * represent cycles. However, we use timespec64_to_ns for the
 417                 * correct math even though the units haven't been corrected
 418                 * yet.
 419                 */
 420                systime.tv_sec = timestamp >> 32;
 421                systime.tv_nsec = timestamp & 0xFFFFFFFF;
 422
 423                timestamp = timespec64_to_ns(&systime);
 424                break;
 425        default:
 426                break;
 427        }
 428
 429        spin_lock_irqsave(&adapter->tmreg_lock, flags);
 430        ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
 431        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 432
 433        hwtstamp->hwtstamp = ns_to_ktime(ns);
 434}
 435
 436/**
 437 * ixgbe_ptp_adjfreq_82599
 438 * @ptp: the ptp clock structure
 439 * @ppb: parts per billion adjustment from base
 440 *
 441 * adjust the frequency of the ptp cycle counter by the
 442 * indicated ppb from the base frequency.
 443 */
 444static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb)
 445{
 446        struct ixgbe_adapter *adapter =
 447                container_of(ptp, struct ixgbe_adapter, ptp_caps);
 448        struct ixgbe_hw *hw = &adapter->hw;
 449        u64 freq, incval;
 450        u32 diff;
 451        int neg_adj = 0;
 452
 453        if (ppb < 0) {
 454                neg_adj = 1;
 455                ppb = -ppb;
 456        }
 457
 458        smp_mb();
 459        incval = READ_ONCE(adapter->base_incval);
 460
 461        freq = incval;
 462        freq *= ppb;
 463        diff = div_u64(freq, 1000000000ULL);
 464
 465        incval = neg_adj ? (incval - diff) : (incval + diff);
 466
 467        switch (hw->mac.type) {
 468        case ixgbe_mac_X540:
 469                if (incval > 0xFFFFFFFFULL)
 470                        e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
 471                IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
 472                break;
 473        case ixgbe_mac_82599EB:
 474                if (incval > 0x00FFFFFFULL)
 475                        e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
 476                IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 477                                BIT(IXGBE_INCPER_SHIFT_82599) |
 478                                ((u32)incval & 0x00FFFFFFUL));
 479                break;
 480        default:
 481                break;
 482        }
 483
 484        return 0;
 485}
 486
 487/**
 488 * ixgbe_ptp_adjfreq_X550
 489 * @ptp: the ptp clock structure
 490 * @ppb: parts per billion adjustment from base
 491 *
 492 * adjust the frequency of the SYSTIME registers by the indicated ppb from base
 493 * frequency
 494 */
 495static int ixgbe_ptp_adjfreq_X550(struct ptp_clock_info *ptp, s32 ppb)
 496{
 497        struct ixgbe_adapter *adapter =
 498                        container_of(ptp, struct ixgbe_adapter, ptp_caps);
 499        struct ixgbe_hw *hw = &adapter->hw;
 500        int neg_adj = 0;
 501        u64 rate = IXGBE_X550_BASE_PERIOD;
 502        u32 inca;
 503
 504        if (ppb < 0) {
 505                neg_adj = 1;
 506                ppb = -ppb;
 507        }
 508        rate *= ppb;
 509        rate = div_u64(rate, 1000000000ULL);
 510
 511        /* warn if rate is too large */
 512        if (rate >= INCVALUE_MASK)
 513                e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n");
 514
 515        inca = rate & INCVALUE_MASK;
 516        if (neg_adj)
 517                inca |= ISGN;
 518
 519        IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
 520
 521        return 0;
 522}
 523
 524/**
 525 * ixgbe_ptp_adjtime
 526 * @ptp: the ptp clock structure
 527 * @delta: offset to adjust the cycle counter by
 528 *
 529 * adjust the timer by resetting the timecounter structure.
 530 */
 531static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 532{
 533        struct ixgbe_adapter *adapter =
 534                container_of(ptp, struct ixgbe_adapter, ptp_caps);
 535        unsigned long flags;
 536
 537        spin_lock_irqsave(&adapter->tmreg_lock, flags);
 538        timecounter_adjtime(&adapter->hw_tc, delta);
 539        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 540
 541        if (adapter->ptp_setup_sdp)
 542                adapter->ptp_setup_sdp(adapter);
 543
 544        return 0;
 545}
 546
 547/**
 548 * ixgbe_ptp_gettimex
 549 * @ptp: the ptp clock structure
 550 * @ts: timespec to hold the PHC timestamp
 551 * @sts: structure to hold the system time before and after reading the PHC
 552 *
 553 * read the timecounter and return the correct value on ns,
 554 * after converting it into a struct timespec.
 555 */
 556static int ixgbe_ptp_gettimex(struct ptp_clock_info *ptp,
 557                              struct timespec64 *ts,
 558                              struct ptp_system_timestamp *sts)
 559{
 560        struct ixgbe_adapter *adapter =
 561                container_of(ptp, struct ixgbe_adapter, ptp_caps);
 562        struct ixgbe_hw *hw = &adapter->hw;
 563        unsigned long flags;
 564        u64 ns, stamp;
 565
 566        spin_lock_irqsave(&adapter->tmreg_lock, flags);
 567
 568        switch (adapter->hw.mac.type) {
 569        case ixgbe_mac_X550:
 570        case ixgbe_mac_X550EM_x:
 571        case ixgbe_mac_x550em_a:
 572                /* Upper 32 bits represent billions of cycles, lower 32 bits
 573                 * represent cycles. However, we use timespec64_to_ns for the
 574                 * correct math even though the units haven't been corrected
 575                 * yet.
 576                 */
 577                ptp_read_system_prets(sts);
 578                IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
 579                ptp_read_system_postts(sts);
 580                ts->tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 581                ts->tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
 582                stamp = timespec64_to_ns(ts);
 583                break;
 584        default:
 585                ptp_read_system_prets(sts);
 586                stamp = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 587                ptp_read_system_postts(sts);
 588                stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 589                break;
 590        }
 591
 592        ns = timecounter_cyc2time(&adapter->hw_tc, stamp);
 593
 594        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 595
 596        *ts = ns_to_timespec64(ns);
 597
 598        return 0;
 599}
 600
 601/**
 602 * ixgbe_ptp_settime
 603 * @ptp: the ptp clock structure
 604 * @ts: the timespec containing the new time for the cycle counter
 605 *
 606 * reset the timecounter to use a new base value instead of the kernel
 607 * wall timer value.
 608 */
 609static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
 610                             const struct timespec64 *ts)
 611{
 612        struct ixgbe_adapter *adapter =
 613                container_of(ptp, struct ixgbe_adapter, ptp_caps);
 614        unsigned long flags;
 615        u64 ns = timespec64_to_ns(ts);
 616
 617        /* reset the timecounter */
 618        spin_lock_irqsave(&adapter->tmreg_lock, flags);
 619        timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
 620        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 621
 622        if (adapter->ptp_setup_sdp)
 623                adapter->ptp_setup_sdp(adapter);
 624        return 0;
 625}
 626
 627/**
 628 * ixgbe_ptp_feature_enable
 629 * @ptp: the ptp clock structure
 630 * @rq: the requested feature to change
 631 * @on: whether to enable or disable the feature
 632 *
 633 * enable (or disable) ancillary features of the phc subsystem.
 634 * our driver only supports the PPS feature on the X540
 635 */
 636static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
 637                                    struct ptp_clock_request *rq, int on)
 638{
 639        struct ixgbe_adapter *adapter =
 640                container_of(ptp, struct ixgbe_adapter, ptp_caps);
 641
 642        /**
 643         * When PPS is enabled, unmask the interrupt for the ClockOut
 644         * feature, so that the interrupt handler can send the PPS
 645         * event when the clock SDP triggers. Clear mask when PPS is
 646         * disabled
 647         */
 648        if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
 649                return -ENOTSUPP;
 650
 651        if (on)
 652                adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
 653        else
 654                adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
 655
 656        adapter->ptp_setup_sdp(adapter);
 657        return 0;
 658}
 659
 660/**
 661 * ixgbe_ptp_check_pps_event
 662 * @adapter: the private adapter structure
 663 *
 664 * This function is called by the interrupt routine when checking for
 665 * interrupts. It will check and handle a pps event.
 666 */
 667void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
 668{
 669        struct ixgbe_hw *hw = &adapter->hw;
 670        struct ptp_clock_event event;
 671
 672        event.type = PTP_CLOCK_PPS;
 673
 674        /* this check is necessary in case the interrupt was enabled via some
 675         * alternative means (ex. debug_fs). Better to check here than
 676         * everywhere that calls this function.
 677         */
 678        if (!adapter->ptp_clock)
 679                return;
 680
 681        switch (hw->mac.type) {
 682        case ixgbe_mac_X540:
 683                ptp_clock_event(adapter->ptp_clock, &event);
 684                break;
 685        default:
 686                break;
 687        }
 688}
 689
 690/**
 691 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
 692 * @adapter: private adapter struct
 693 *
 694 * this watchdog task periodically reads the timecounter
 695 * in order to prevent missing when the system time registers wrap
 696 * around. This needs to be run approximately twice a minute.
 697 */
 698void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
 699{
 700        bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
 701                                             IXGBE_OVERFLOW_PERIOD);
 702        unsigned long flags;
 703
 704        if (timeout) {
 705                /* Update the timecounter */
 706                spin_lock_irqsave(&adapter->tmreg_lock, flags);
 707                timecounter_read(&adapter->hw_tc);
 708                spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 709
 710                adapter->last_overflow_check = jiffies;
 711        }
 712}
 713
 714/**
 715 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
 716 * @adapter: private network adapter structure
 717 *
 718 * this watchdog task is scheduled to detect error case where hardware has
 719 * dropped an Rx packet that was timestamped when the ring is full. The
 720 * particular error is rare but leaves the device in a state unable to timestamp
 721 * any future packets.
 722 */
 723void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
 724{
 725        struct ixgbe_hw *hw = &adapter->hw;
 726        u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 727        struct ixgbe_ring *rx_ring;
 728        unsigned long rx_event;
 729        int n;
 730
 731        /* if we don't have a valid timestamp in the registers, just update the
 732         * timeout counter and exit
 733         */
 734        if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
 735                adapter->last_rx_ptp_check = jiffies;
 736                return;
 737        }
 738
 739        /* determine the most recent watchdog or rx_timestamp event */
 740        rx_event = adapter->last_rx_ptp_check;
 741        for (n = 0; n < adapter->num_rx_queues; n++) {
 742                rx_ring = adapter->rx_ring[n];
 743                if (time_after(rx_ring->last_rx_timestamp, rx_event))
 744                        rx_event = rx_ring->last_rx_timestamp;
 745        }
 746
 747        /* only need to read the high RXSTMP register to clear the lock */
 748        if (time_is_before_jiffies(rx_event + 5 * HZ)) {
 749                IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 750                adapter->last_rx_ptp_check = jiffies;
 751
 752                adapter->rx_hwtstamp_cleared++;
 753                e_warn(drv, "clearing RX Timestamp hang\n");
 754        }
 755}
 756
 757/**
 758 * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
 759 * @adapter: the private adapter structure
 760 *
 761 * This function should be called whenever the state related to a Tx timestamp
 762 * needs to be cleared. This helps ensure that all related bits are reset for
 763 * the next Tx timestamp event.
 764 */
 765static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
 766{
 767        struct ixgbe_hw *hw = &adapter->hw;
 768
 769        IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
 770        if (adapter->ptp_tx_skb) {
 771                dev_kfree_skb_any(adapter->ptp_tx_skb);
 772                adapter->ptp_tx_skb = NULL;
 773        }
 774        clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
 775}
 776
 777/**
 778 * ixgbe_ptp_tx_hang - detect error case where Tx timestamp never finishes
 779 * @adapter: private network adapter structure
 780 */
 781void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
 782{
 783        bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
 784                                              IXGBE_PTP_TX_TIMEOUT);
 785
 786        if (!adapter->ptp_tx_skb)
 787                return;
 788
 789        if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
 790                return;
 791
 792        /* If we haven't received a timestamp within the timeout, it is
 793         * reasonable to assume that it will never occur, so we can unlock the
 794         * timestamp bit when this occurs.
 795         */
 796        if (timeout) {
 797                cancel_work_sync(&adapter->ptp_tx_work);
 798                ixgbe_ptp_clear_tx_timestamp(adapter);
 799                adapter->tx_hwtstamp_timeouts++;
 800                e_warn(drv, "clearing Tx timestamp hang\n");
 801        }
 802}
 803
 804/**
 805 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 806 * @adapter: the private adapter struct
 807 *
 808 * if the timestamp is valid, we convert it into the timecounter ns
 809 * value, then store that result into the shhwtstamps structure which
 810 * is passed up the network stack
 811 */
 812static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
 813{
 814        struct sk_buff *skb = adapter->ptp_tx_skb;
 815        struct ixgbe_hw *hw = &adapter->hw;
 816        struct skb_shared_hwtstamps shhwtstamps;
 817        u64 regval = 0;
 818
 819        regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
 820        regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
 821        ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
 822
 823        /* Handle cleanup of the ptp_tx_skb ourselves, and unlock the state
 824         * bit prior to notifying the stack via skb_tstamp_tx(). This prevents
 825         * well behaved applications from attempting to timestamp again prior
 826         * to the lock bit being clear.
 827         */
 828        adapter->ptp_tx_skb = NULL;
 829        clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
 830
 831        /* Notify the stack and then free the skb after we've unlocked */
 832        skb_tstamp_tx(skb, &shhwtstamps);
 833        dev_kfree_skb_any(skb);
 834}
 835
 836/**
 837 * ixgbe_ptp_tx_hwtstamp_work
 838 * @work: pointer to the work struct
 839 *
 840 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
 841 * timestamp has been taken for the current skb. It is necessary, because the
 842 * descriptor's "done" bit does not correlate with the timestamp event.
 843 */
 844static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
 845{
 846        struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
 847                                                     ptp_tx_work);
 848        struct ixgbe_hw *hw = &adapter->hw;
 849        bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
 850                                              IXGBE_PTP_TX_TIMEOUT);
 851        u32 tsynctxctl;
 852
 853        /* we have to have a valid skb to poll for a timestamp */
 854        if (!adapter->ptp_tx_skb) {
 855                ixgbe_ptp_clear_tx_timestamp(adapter);
 856                return;
 857        }
 858
 859        /* stop polling once we have a valid timestamp */
 860        tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 861        if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
 862                ixgbe_ptp_tx_hwtstamp(adapter);
 863                return;
 864        }
 865
 866        if (timeout) {
 867                ixgbe_ptp_clear_tx_timestamp(adapter);
 868                adapter->tx_hwtstamp_timeouts++;
 869                e_warn(drv, "clearing Tx Timestamp hang\n");
 870        } else {
 871                /* reschedule to keep checking if it's not available yet */
 872                schedule_work(&adapter->ptp_tx_work);
 873        }
 874}
 875
 876/**
 877 * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer
 878 * @q_vector: structure containing interrupt and ring information
 879 * @skb: the packet
 880 *
 881 * This function will be called by the Rx routine of the timestamp for this
 882 * packet is stored in the buffer. The value is stored in little endian format
 883 * starting at the end of the packet data.
 884 */
 885void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
 886                           struct sk_buff *skb)
 887{
 888        __le64 regval;
 889
 890        /* copy the bits out of the skb, and then trim the skb length */
 891        skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, &regval,
 892                      IXGBE_TS_HDR_LEN);
 893        __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
 894
 895        /* The timestamp is recorded in little endian format, and is stored at
 896         * the end of the packet.
 897         *
 898         * DWORD: N              N + 1      N + 2
 899         * Field: End of Packet  SYSTIMH    SYSTIML
 900         */
 901        ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
 902                                      le64_to_cpu(regval));
 903}
 904
 905/**
 906 * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp
 907 * @q_vector: structure containing interrupt and ring information
 908 * @skb: particular skb to send timestamp with
 909 *
 910 * if the timestamp is valid, we convert it into the timecounter ns
 911 * value, then store that result into the shhwtstamps structure which
 912 * is passed up the network stack
 913 */
 914void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
 915                           struct sk_buff *skb)
 916{
 917        struct ixgbe_adapter *adapter;
 918        struct ixgbe_hw *hw;
 919        u64 regval = 0;
 920        u32 tsyncrxctl;
 921
 922        /* we cannot process timestamps on a ring without a q_vector */
 923        if (!q_vector || !q_vector->adapter)
 924                return;
 925
 926        adapter = q_vector->adapter;
 927        hw = &adapter->hw;
 928
 929        /* Read the tsyncrxctl register afterwards in order to prevent taking an
 930         * I/O hit on every packet.
 931         */
 932
 933        tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 934        if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
 935                return;
 936
 937        regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
 938        regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
 939
 940        ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 941}
 942
 943/**
 944 * ixgbe_ptp_get_ts_config - get current hardware timestamping configuration
 945 * @adapter: pointer to adapter structure
 946 * @ifr: ioctl data
 947 *
 948 * This function returns the current timestamping settings. Rather than
 949 * attempt to deconstruct registers to fill in the values, simply keep a copy
 950 * of the old settings around, and return a copy when requested.
 951 */
 952int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
 953{
 954        struct hwtstamp_config *config = &adapter->tstamp_config;
 955
 956        return copy_to_user(ifr->ifr_data, config,
 957                            sizeof(*config)) ? -EFAULT : 0;
 958}
 959
 960/**
 961 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
 962 * @adapter: the private ixgbe adapter structure
 963 * @config: the hwtstamp configuration requested
 964 *
 965 * Outgoing time stamping can be enabled and disabled. Play nice and
 966 * disable it when requested, although it shouldn't cause any overhead
 967 * when no packet needs it. At most one packet in the queue may be
 968 * marked for time stamping, otherwise it would be impossible to tell
 969 * for sure to which packet the hardware time stamp belongs.
 970 *
 971 * Incoming time stamping has to be configured via the hardware
 972 * filters. Not all combinations are supported, in particular event
 973 * type has to be specified. Matching the kind of event packet is
 974 * not supported, with the exception of "all V2 events regardless of
 975 * level 2 or 4".
 976 *
 977 * Since hardware always timestamps Path delay packets when timestamping V2
 978 * packets, regardless of the type specified in the register, only use V2
 979 * Event mode. This more accurately tells the user what the hardware is going
 980 * to do anyways.
 981 *
 982 * Note: this may modify the hwtstamp configuration towards a more general
 983 * mode, if required to support the specifically requested mode.
 984 */
 985static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
 986                                 struct hwtstamp_config *config)
 987{
 988        struct ixgbe_hw *hw = &adapter->hw;
 989        u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
 990        u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
 991        u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
 992        bool is_l2 = false;
 993        u32 regval;
 994
 995        /* reserved for future extensions */
 996        if (config->flags)
 997                return -EINVAL;
 998
 999        switch (config->tx_type) {
1000        case HWTSTAMP_TX_OFF:
1001                tsync_tx_ctl = 0;
1002        case HWTSTAMP_TX_ON:
1003                break;
1004        default:
1005                return -ERANGE;
1006        }
1007
1008        switch (config->rx_filter) {
1009        case HWTSTAMP_FILTER_NONE:
1010                tsync_rx_ctl = 0;
1011                tsync_rx_mtrl = 0;
1012                adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1013                                    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1014                break;
1015        case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1016                tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1017                tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
1018                adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1019                                   IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1020                break;
1021        case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1022                tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1023                tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
1024                adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1025                                   IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1026                break;
1027        case HWTSTAMP_FILTER_PTP_V2_EVENT:
1028        case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1029        case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1030        case HWTSTAMP_FILTER_PTP_V2_SYNC:
1031        case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1032        case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1033        case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1034        case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1035        case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1036                tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
1037                is_l2 = true;
1038                config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1039                adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1040                                   IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1041                break;
1042        case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1043        case HWTSTAMP_FILTER_NTP_ALL:
1044        case HWTSTAMP_FILTER_ALL:
1045                /* The X550 controller is capable of timestamping all packets,
1046                 * which allows it to accept any filter.
1047                 */
1048                if (hw->mac.type >= ixgbe_mac_X550) {
1049                        tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
1050                        config->rx_filter = HWTSTAMP_FILTER_ALL;
1051                        adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1052                        break;
1053                }
1054                fallthrough;
1055        default:
1056                /*
1057                 * register RXMTRL must be set in order to do V1 packets,
1058                 * therefore it is not possible to time stamp both V1 Sync and
1059                 * Delay_Req messages and hardware does not support
1060                 * timestamping all packets => return error
1061                 */
1062                adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1063                                    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1064                config->rx_filter = HWTSTAMP_FILTER_NONE;
1065                return -ERANGE;
1066        }
1067
1068        if (hw->mac.type == ixgbe_mac_82598EB) {
1069                adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1070                                    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1071                if (tsync_rx_ctl | tsync_tx_ctl)
1072                        return -ERANGE;
1073                return 0;
1074        }
1075
1076        /* Per-packet timestamping only works if the filter is set to all
1077         * packets. Since this is desired, always timestamp all packets as long
1078         * as any Rx filter was configured.
1079         */
1080        switch (hw->mac.type) {
1081        case ixgbe_mac_X550:
1082        case ixgbe_mac_X550EM_x:
1083        case ixgbe_mac_x550em_a:
1084                /* enable timestamping all packets only if at least some
1085                 * packets were requested. Otherwise, play nice and disable
1086                 * timestamping
1087                 */
1088                if (config->rx_filter == HWTSTAMP_FILTER_NONE)
1089                        break;
1090
1091                tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
1092                               IXGBE_TSYNCRXCTL_TYPE_ALL |
1093                               IXGBE_TSYNCRXCTL_TSIP_UT_EN;
1094                config->rx_filter = HWTSTAMP_FILTER_ALL;
1095                adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1096                adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
1097                is_l2 = true;
1098                break;
1099        default:
1100                break;
1101        }
1102
1103        /* define ethertype filter for timestamping L2 packets */
1104        if (is_l2)
1105                IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
1106                                (IXGBE_ETQF_FILTER_EN | /* enable filter */
1107                                 IXGBE_ETQF_1588 | /* enable timestamping */
1108                                 ETH_P_1588));     /* 1588 eth protocol type */
1109        else
1110                IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
1111
1112        /* enable/disable TX */
1113        regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
1114        regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
1115        regval |= tsync_tx_ctl;
1116        IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
1117
1118        /* enable/disable RX */
1119        regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
1120        regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
1121        regval |= tsync_rx_ctl;
1122        IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
1123
1124        /* define which PTP packets are time stamped */
1125        IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
1126
1127        IXGBE_WRITE_FLUSH(hw);
1128
1129        /* clear TX/RX time stamp registers, just to be sure */
1130        ixgbe_ptp_clear_tx_timestamp(adapter);
1131        IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
1132
1133        return 0;
1134}
1135
1136/**
1137 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
1138 * @adapter: pointer to adapter struct
1139 * @ifr: ioctl data
1140 *
1141 * Set hardware to requested mode. If unsupported, return an error with no
1142 * changes. Otherwise, store the mode for future reference.
1143 */
1144int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
1145{
1146        struct hwtstamp_config config;
1147        int err;
1148
1149        if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1150                return -EFAULT;
1151
1152        err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
1153        if (err)
1154                return err;
1155
1156        /* save these settings for future reference */
1157        memcpy(&adapter->tstamp_config, &config,
1158               sizeof(adapter->tstamp_config));
1159
1160        return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1161                -EFAULT : 0;
1162}
1163
1164static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1165                                        u32 *shift, u32 *incval)
1166{
1167        /**
1168         * Scale the NIC cycle counter by a large factor so that
1169         * relatively small corrections to the frequency can be added
1170         * or subtracted. The drawbacks of a large factor include
1171         * (a) the clock register overflows more quickly, (b) the cycle
1172         * counter structure must be able to convert the systime value
1173         * to nanoseconds using only a multiplier and a right-shift,
1174         * and (c) the value must fit within the timinca register space
1175         * => math based on internal DMA clock rate and available bits
1176         *
1177         * Note that when there is no link, internal DMA clock is same as when
1178         * link speed is 10Gb. Set the registers correctly even when link is
1179         * down to preserve the clock setting
1180         */
1181        switch (adapter->link_speed) {
1182        case IXGBE_LINK_SPEED_100_FULL:
1183                *shift = IXGBE_INCVAL_SHIFT_100;
1184                *incval = IXGBE_INCVAL_100;
1185                break;
1186        case IXGBE_LINK_SPEED_1GB_FULL:
1187                *shift = IXGBE_INCVAL_SHIFT_1GB;
1188                *incval = IXGBE_INCVAL_1GB;
1189                break;
1190        case IXGBE_LINK_SPEED_10GB_FULL:
1191        default:
1192                *shift = IXGBE_INCVAL_SHIFT_10GB;
1193                *incval = IXGBE_INCVAL_10GB;
1194                break;
1195        }
1196}
1197
1198/**
1199 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
1200 * @adapter: pointer to the adapter structure
1201 *
1202 * This function should be called to set the proper values for the TIMINCA
1203 * register and tell the cyclecounter structure what the tick rate of SYSTIME
1204 * is. It does not directly modify SYSTIME registers or the timecounter
1205 * structure. It should be called whenever a new TIMINCA value is necessary,
1206 * such as during initialization or when the link speed changes.
1207 */
1208void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1209{
1210        struct ixgbe_hw *hw = &adapter->hw;
1211        struct cyclecounter cc;
1212        unsigned long flags;
1213        u32 incval = 0;
1214        u32 tsauxc = 0;
1215        u32 fuse0 = 0;
1216
1217        /* For some of the boards below this mask is technically incorrect.
1218         * The timestamp mask overflows at approximately 61bits. However the
1219         * particular hardware does not overflow on an even bitmask value.
1220         * Instead, it overflows due to conversion of upper 32bits billions of
1221         * cycles. Timecounters are not really intended for this purpose so
1222         * they do not properly function if the overflow point isn't 2^N-1.
1223         * However, the actual SYSTIME values in question take ~138 years to
1224         * overflow. In practice this means they won't actually overflow. A
1225         * proper fix to this problem would require modification of the
1226         * timecounter delta calculations.
1227         */
1228        cc.mask = CLOCKSOURCE_MASK(64);
1229        cc.mult = 1;
1230        cc.shift = 0;
1231
1232        switch (hw->mac.type) {
1233        case ixgbe_mac_X550EM_x:
1234                /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is
1235                 * designed to represent seconds and nanoseconds when this is
1236                 * the case. However, some revisions of hardware have a 400Mhz
1237                 * clock and we have to compensate for this frequency
1238                 * variation using corrected mult and shift values.
1239                 */
1240                fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1241                if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1242                        cc.mult = 3;
1243                        cc.shift = 2;
1244                }
1245                fallthrough;
1246        case ixgbe_mac_x550em_a:
1247        case ixgbe_mac_X550:
1248                cc.read = ixgbe_ptp_read_X550;
1249
1250                /* enable SYSTIME counter */
1251                IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1252                IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1253                IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1254                tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1255                IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1256                                tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1257                IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1258                IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1259
1260                IXGBE_WRITE_FLUSH(hw);
1261                break;
1262        case ixgbe_mac_X540:
1263                cc.read = ixgbe_ptp_read_82599;
1264
1265                ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1266                IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1267                break;
1268        case ixgbe_mac_82599EB:
1269                cc.read = ixgbe_ptp_read_82599;
1270
1271                ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1272                incval >>= IXGBE_INCVAL_SHIFT_82599;
1273                cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1274                IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1275                                BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1276                break;
1277        default:
1278                /* other devices aren't supported */
1279                return;
1280        }
1281
1282        /* update the base incval used to calculate frequency adjustment */
1283        WRITE_ONCE(adapter->base_incval, incval);
1284        smp_mb();
1285
1286        /* need lock to prevent incorrect read while modifying cyclecounter */
1287        spin_lock_irqsave(&adapter->tmreg_lock, flags);
1288        memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
1289        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1290}
1291
1292/**
1293 * ixgbe_ptp_reset
1294 * @adapter: the ixgbe private board structure
1295 *
1296 * When the MAC resets, all the hardware bits for timesync are reset. This
1297 * function is used to re-enable the device for PTP based on current settings.
1298 * We do lose the current clock time, so just reset the cyclecounter to the
1299 * system real clock time.
1300 *
1301 * This function will maintain hwtstamp_config settings, and resets the SDP
1302 * output if it was enabled.
1303 */
1304void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1305{
1306        struct ixgbe_hw *hw = &adapter->hw;
1307        unsigned long flags;
1308
1309        /* reset the hardware timestamping mode */
1310        ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1311
1312        /* 82598 does not support PTP */
1313        if (hw->mac.type == ixgbe_mac_82598EB)
1314                return;
1315
1316        ixgbe_ptp_start_cyclecounter(adapter);
1317
1318        spin_lock_irqsave(&adapter->tmreg_lock, flags);
1319        timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
1320                         ktime_to_ns(ktime_get_real()));
1321        spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1322
1323        adapter->last_overflow_check = jiffies;
1324
1325        /* Now that the shift has been calculated and the systime
1326         * registers reset, (re-)enable the Clock out feature
1327         */
1328        if (adapter->ptp_setup_sdp)
1329                adapter->ptp_setup_sdp(adapter);
1330}
1331
1332/**
1333 * ixgbe_ptp_create_clock
1334 * @adapter: the ixgbe private adapter structure
1335 *
1336 * This function performs setup of the user entry point function table and
1337 * initializes the PTP clock device, which is used to access the clock-like
1338 * features of the PTP core. It will be called by ixgbe_ptp_init, and may
1339 * reuse a previously initialized clock (such as during a suspend/resume
1340 * cycle).
1341 */
1342static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
1343{
1344        struct net_device *netdev = adapter->netdev;
1345        long err;
1346
1347        /* do nothing if we already have a clock device */
1348        if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1349                return 0;
1350
1351        switch (adapter->hw.mac.type) {
1352        case ixgbe_mac_X540:
1353                snprintf(adapter->ptp_caps.name,
1354                         sizeof(adapter->ptp_caps.name),
1355                         "%s", netdev->name);
1356                adapter->ptp_caps.owner = THIS_MODULE;
1357                adapter->ptp_caps.max_adj = 250000000;
1358                adapter->ptp_caps.n_alarm = 0;
1359                adapter->ptp_caps.n_ext_ts = 0;
1360                adapter->ptp_caps.n_per_out = 0;
1361                adapter->ptp_caps.pps = 1;
1362                adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1363                adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1364                adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1365                adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1366                adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1367                adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X540;
1368                break;
1369        case ixgbe_mac_82599EB:
1370                snprintf(adapter->ptp_caps.name,
1371                         sizeof(adapter->ptp_caps.name),
1372                         "%s", netdev->name);
1373                adapter->ptp_caps.owner = THIS_MODULE;
1374                adapter->ptp_caps.max_adj = 250000000;
1375                adapter->ptp_caps.n_alarm = 0;
1376                adapter->ptp_caps.n_ext_ts = 0;
1377                adapter->ptp_caps.n_per_out = 0;
1378                adapter->ptp_caps.pps = 0;
1379                adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599;
1380                adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1381                adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1382                adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1383                adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1384                break;
1385        case ixgbe_mac_X550:
1386        case ixgbe_mac_X550EM_x:
1387        case ixgbe_mac_x550em_a:
1388                snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1389                adapter->ptp_caps.owner = THIS_MODULE;
1390                adapter->ptp_caps.max_adj = 30000000;
1391                adapter->ptp_caps.n_alarm = 0;
1392                adapter->ptp_caps.n_ext_ts = 0;
1393                adapter->ptp_caps.n_per_out = 0;
1394                adapter->ptp_caps.pps = 1;
1395                adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550;
1396                adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1397                adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1398                adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1399                adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1400                adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X550;
1401                break;
1402        default:
1403                adapter->ptp_clock = NULL;
1404                adapter->ptp_setup_sdp = NULL;
1405                return -EOPNOTSUPP;
1406        }
1407
1408        adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1409                                                &adapter->pdev->dev);
1410        if (IS_ERR(adapter->ptp_clock)) {
1411                err = PTR_ERR(adapter->ptp_clock);
1412                adapter->ptp_clock = NULL;
1413                e_dev_err("ptp_clock_register failed\n");
1414                return err;
1415        } else if (adapter->ptp_clock)
1416                e_dev_info("registered PHC device on %s\n", netdev->name);
1417
1418        /* set default timestamp mode to disabled here. We do this in
1419         * create_clock instead of init, because we don't want to override the
1420         * previous settings during a resume cycle.
1421         */
1422        adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1423        adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1424
1425        return 0;
1426}
1427
1428/**
1429 * ixgbe_ptp_init
1430 * @adapter: the ixgbe private adapter structure
1431 *
1432 * This function performs the required steps for enabling PTP
1433 * support. If PTP support has already been loaded it simply calls the
1434 * cyclecounter init routine and exits.
1435 */
1436void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1437{
1438        /* initialize the spin lock first since we can't control when a user
1439         * will call the entry functions once we have initialized the clock
1440         * device
1441         */
1442        spin_lock_init(&adapter->tmreg_lock);
1443
1444        /* obtain a PTP device, or re-use an existing device */
1445        if (ixgbe_ptp_create_clock(adapter))
1446                return;
1447
1448        /* we have a clock so we can initialize work now */
1449        INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1450
1451        /* reset the PTP related hardware bits */
1452        ixgbe_ptp_reset(adapter);
1453
1454        /* enter the IXGBE_PTP_RUNNING state */
1455        set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
1456
1457        return;
1458}
1459
1460/**
1461 * ixgbe_ptp_suspend - stop PTP work items
1462 * @adapter: pointer to adapter struct
1463 *
1464 * this function suspends PTP activity, and prevents more PTP work from being
1465 * generated, but does not destroy the PTP clock device.
1466 */
1467void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
1468{
1469        /* Leave the IXGBE_PTP_RUNNING state. */
1470        if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1471                return;
1472
1473        adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1474        if (adapter->ptp_setup_sdp)
1475                adapter->ptp_setup_sdp(adapter);
1476
1477        /* ensure that we cancel any pending PTP Tx work item in progress */
1478        cancel_work_sync(&adapter->ptp_tx_work);
1479        ixgbe_ptp_clear_tx_timestamp(adapter);
1480}
1481
1482/**
1483 * ixgbe_ptp_stop - close the PTP device
1484 * @adapter: pointer to adapter struct
1485 *
1486 * completely destroy the PTP device, should only be called when the device is
1487 * being fully closed.
1488 */
1489void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1490{
1491        /* first, suspend PTP activity */
1492        ixgbe_ptp_suspend(adapter);
1493
1494        /* disable the PTP clock device */
1495        if (adapter->ptp_clock) {
1496                ptp_clock_unregister(adapter->ptp_clock);
1497                adapter->ptp_clock = NULL;
1498                e_dev_info("removed PHC on %s\n",
1499                           adapter->netdev->name);
1500        }
1501}
1502