1
2
3
4
5
6
7
8
9
10#ifndef __DWMAC4_DMA_H__
11#define __DWMAC4_DMA_H__
12
13
14
15
16#define DMA_CHANNEL_NB_MAX 1
17
18#define DMA_BUS_MODE 0x00001000
19#define DMA_SYS_BUS_MODE 0x00001004
20#define DMA_STATUS 0x00001008
21#define DMA_DEBUG_STATUS_0 0x0000100c
22#define DMA_DEBUG_STATUS_1 0x00001010
23#define DMA_DEBUG_STATUS_2 0x00001014
24#define DMA_AXI_BUS_MODE 0x00001028
25#define DMA_TBS_CTRL 0x00001050
26
27
28#define DMA_BUS_MODE_SFT_RESET BIT(0)
29
30
31#define DMA_BUS_MODE_SPH BIT(24)
32#define DMA_BUS_MODE_PBL BIT(16)
33#define DMA_BUS_MODE_PBL_SHIFT 16
34#define DMA_BUS_MODE_RPBL_SHIFT 16
35#define DMA_BUS_MODE_MB BIT(14)
36#define DMA_BUS_MODE_FB BIT(0)
37
38
39#define DMA_STATUS_MAC BIT(17)
40#define DMA_STATUS_MTL BIT(16)
41#define DMA_STATUS_CHAN7 BIT(7)
42#define DMA_STATUS_CHAN6 BIT(6)
43#define DMA_STATUS_CHAN5 BIT(5)
44#define DMA_STATUS_CHAN4 BIT(4)
45#define DMA_STATUS_CHAN3 BIT(3)
46#define DMA_STATUS_CHAN2 BIT(2)
47#define DMA_STATUS_CHAN1 BIT(1)
48#define DMA_STATUS_CHAN0 BIT(0)
49
50
51#define DMA_DEBUG_STATUS_TS_MASK 0xf
52#define DMA_DEBUG_STATUS_RS_MASK 0xf
53
54
55#define DMA_AXI_EN_LPI BIT(31)
56#define DMA_AXI_LPI_XIT_FRM BIT(30)
57#define DMA_AXI_WR_OSR_LMT GENMASK(27, 24)
58#define DMA_AXI_WR_OSR_LMT_SHIFT 24
59#define DMA_AXI_RD_OSR_LMT GENMASK(19, 16)
60#define DMA_AXI_RD_OSR_LMT_SHIFT 16
61
62#define DMA_AXI_OSR_MAX 0xf
63#define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \
64 (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT))
65
66#define DMA_SYS_BUS_MB BIT(14)
67#define DMA_AXI_1KBBE BIT(13)
68#define DMA_SYS_BUS_AAL BIT(12)
69#define DMA_SYS_BUS_EAME BIT(11)
70#define DMA_AXI_BLEN256 BIT(7)
71#define DMA_AXI_BLEN128 BIT(6)
72#define DMA_AXI_BLEN64 BIT(5)
73#define DMA_AXI_BLEN32 BIT(4)
74#define DMA_AXI_BLEN16 BIT(3)
75#define DMA_AXI_BLEN8 BIT(2)
76#define DMA_AXI_BLEN4 BIT(1)
77#define DMA_SYS_BUS_FB BIT(0)
78
79#define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \
80 DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \
81 DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \
82 DMA_AXI_BLEN4)
83
84#define DMA_AXI_BURST_LEN_MASK 0x000000FE
85
86
87#define DMA_TBS_FTOS GENMASK(31, 8)
88#define DMA_TBS_FTOV BIT(0)
89#define DMA_TBS_DEF_FTOS (DMA_TBS_FTOS | DMA_TBS_FTOV)
90
91
92#define DMA_CHAN_BASE_ADDR 0x00001100
93#define DMA_CHAN_BASE_OFFSET 0x80
94#define DMA_CHANX_BASE_ADDR(x) (DMA_CHAN_BASE_ADDR + \
95 (x * DMA_CHAN_BASE_OFFSET))
96#define DMA_CHAN_REG_NUMBER 17
97
98#define DMA_CHAN_CONTROL(x) DMA_CHANX_BASE_ADDR(x)
99#define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4)
100#define DMA_CHAN_RX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x8)
101#define DMA_CHAN_TX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x10)
102#define DMA_CHAN_TX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x14)
103#define DMA_CHAN_RX_BASE_ADDR_HI(x) (DMA_CHANX_BASE_ADDR(x) + 0x18)
104#define DMA_CHAN_RX_BASE_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x1c)
105#define DMA_CHAN_TX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x20)
106#define DMA_CHAN_RX_END_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x28)
107#define DMA_CHAN_TX_RING_LEN(x) (DMA_CHANX_BASE_ADDR(x) + 0x2c)
108#define DMA_CHAN_RX_RING_LEN(x) (DMA_CHANX_BASE_ADDR(x) + 0x30)
109#define DMA_CHAN_INTR_ENA(x) (DMA_CHANX_BASE_ADDR(x) + 0x34)
110#define DMA_CHAN_RX_WATCHDOG(x) (DMA_CHANX_BASE_ADDR(x) + 0x38)
111#define DMA_CHAN_SLOT_CTRL_STATUS(x) (DMA_CHANX_BASE_ADDR(x) + 0x3c)
112#define DMA_CHAN_CUR_TX_DESC(x) (DMA_CHANX_BASE_ADDR(x) + 0x44)
113#define DMA_CHAN_CUR_RX_DESC(x) (DMA_CHANX_BASE_ADDR(x) + 0x4c)
114#define DMA_CHAN_CUR_TX_BUF_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x54)
115#define DMA_CHAN_CUR_RX_BUF_ADDR(x) (DMA_CHANX_BASE_ADDR(x) + 0x5c)
116#define DMA_CHAN_STATUS(x) (DMA_CHANX_BASE_ADDR(x) + 0x60)
117
118
119#define DMA_CONTROL_SPH BIT(24)
120#define DMA_CONTROL_MSS_MASK GENMASK(13, 0)
121
122
123#define DMA_CONTROL_EDSE BIT(28)
124#define DMA_CONTROL_TSE BIT(12)
125#define DMA_CONTROL_OSP BIT(4)
126#define DMA_CONTROL_ST BIT(0)
127
128
129#define DMA_CONTROL_SR BIT(0)
130#define DMA_RBSZ_MASK GENMASK(14, 1)
131#define DMA_RBSZ_SHIFT 1
132
133
134#define DMA_CHAN_STATUS_REB GENMASK(21, 19)
135#define DMA_CHAN_STATUS_REB_SHIFT 19
136#define DMA_CHAN_STATUS_TEB GENMASK(18, 16)
137#define DMA_CHAN_STATUS_TEB_SHIFT 16
138#define DMA_CHAN_STATUS_NIS BIT(15)
139#define DMA_CHAN_STATUS_AIS BIT(14)
140#define DMA_CHAN_STATUS_CDE BIT(13)
141#define DMA_CHAN_STATUS_FBE BIT(12)
142#define DMA_CHAN_STATUS_ERI BIT(11)
143#define DMA_CHAN_STATUS_ETI BIT(10)
144#define DMA_CHAN_STATUS_RWT BIT(9)
145#define DMA_CHAN_STATUS_RPS BIT(8)
146#define DMA_CHAN_STATUS_RBU BIT(7)
147#define DMA_CHAN_STATUS_RI BIT(6)
148#define DMA_CHAN_STATUS_TBU BIT(2)
149#define DMA_CHAN_STATUS_TPS BIT(1)
150#define DMA_CHAN_STATUS_TI BIT(0)
151
152
153#define DMA_CHAN_INTR_ENA_NIE BIT(16)
154#define DMA_CHAN_INTR_ENA_AIE BIT(15)
155#define DMA_CHAN_INTR_ENA_NIE_4_10 BIT(15)
156#define DMA_CHAN_INTR_ENA_AIE_4_10 BIT(14)
157#define DMA_CHAN_INTR_ENA_CDE BIT(13)
158#define DMA_CHAN_INTR_ENA_FBE BIT(12)
159#define DMA_CHAN_INTR_ENA_ERE BIT(11)
160#define DMA_CHAN_INTR_ENA_ETE BIT(10)
161#define DMA_CHAN_INTR_ENA_RWE BIT(9)
162#define DMA_CHAN_INTR_ENA_RSE BIT(8)
163#define DMA_CHAN_INTR_ENA_RBUE BIT(7)
164#define DMA_CHAN_INTR_ENA_RIE BIT(6)
165#define DMA_CHAN_INTR_ENA_TBUE BIT(2)
166#define DMA_CHAN_INTR_ENA_TSE BIT(1)
167#define DMA_CHAN_INTR_ENA_TIE BIT(0)
168
169#define DMA_CHAN_INTR_NORMAL (DMA_CHAN_INTR_ENA_NIE | \
170 DMA_CHAN_INTR_ENA_RIE | \
171 DMA_CHAN_INTR_ENA_TIE)
172
173#define DMA_CHAN_INTR_ABNORMAL (DMA_CHAN_INTR_ENA_AIE | \
174 DMA_CHAN_INTR_ENA_FBE)
175
176#define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
177 DMA_CHAN_INTR_ABNORMAL)
178#define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE)
179#define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE)
180
181#define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
182 DMA_CHAN_INTR_ENA_RIE | \
183 DMA_CHAN_INTR_ENA_TIE)
184
185#define DMA_CHAN_INTR_ABNORMAL_4_10 (DMA_CHAN_INTR_ENA_AIE_4_10 | \
186 DMA_CHAN_INTR_ENA_FBE)
187
188#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
189 DMA_CHAN_INTR_ABNORMAL_4_10)
190#define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
191#define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
192
193
194#define DMA_CHAN0_DBG_STAT_TPS GENMASK(15, 12)
195#define DMA_CHAN0_DBG_STAT_TPS_SHIFT 12
196#define DMA_CHAN0_DBG_STAT_RPS GENMASK(11, 8)
197#define DMA_CHAN0_DBG_STAT_RPS_SHIFT 8
198
199int dwmac4_dma_reset(void __iomem *ioaddr);
200void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
201void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
202void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
203void dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx);
204void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan);
205void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan);
206void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan);
207void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan);
208int dwmac4_dma_interrupt(void __iomem *ioaddr,
209 struct stmmac_extra_stats *x, u32 chan);
210void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
211void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan);
212void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
213void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
214
215#endif
216
