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9#ifndef _Z8530_H
10#define _Z8530_H
11
12#include <linux/tty.h>
13#include <linux/interrupt.h>
14
15
16
17
18#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
19#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
20
21
22
23#define FLAG 0x7e
24
25
26#define R0 0
27#define R1 1
28#define R2 2
29#define R3 3
30#define R4 4
31#define R5 5
32#define R6 6
33#define R7 7
34#define R8 8
35#define R9 9
36#define R10 10
37#define R11 11
38#define R12 12
39#define R13 13
40#define R14 14
41#define R15 15
42
43#define RPRIME 16
44
45#define NULLCODE 0
46#define POINT_HIGH 0x8
47#define RES_EXT_INT 0x10
48#define SEND_ABORT 0x18
49#define RES_RxINT_FC 0x20
50#define RES_Tx_P 0x28
51#define ERR_RES 0x30
52#define RES_H_IUS 0x38
53
54#define RES_Rx_CRC 0x40
55#define RES_Tx_CRC 0x80
56#define RES_EOM_L 0xC0
57
58
59
60#define EXT_INT_ENAB 0x1
61#define TxINT_ENAB 0x2
62#define PAR_SPEC 0x4
63
64#define RxINT_DISAB 0
65#define RxINT_FCERR 0x8
66#define INT_ALL_Rx 0x10
67#define INT_ERR_Rx 0x18
68
69#define WT_RDY_RT 0x20
70#define WT_FN_RDYFN 0x40
71#define WT_RDY_ENAB 0x80
72
73
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75
76
77#define RxENABLE 0x1
78#define SYNC_L_INH 0x2
79#define ADD_SM 0x4
80#define RxCRC_ENAB 0x8
81#define ENT_HM 0x10
82#define AUTO_ENAB 0x20
83#define Rx5 0x0
84#define Rx7 0x40
85#define Rx6 0x80
86#define Rx8 0xc0
87
88
89
90#define PAR_ENA 0x1
91#define PAR_EVEN 0x2
92
93#define SYNC_ENAB 0
94#define SB1 0x4
95#define SB15 0x8
96#define SB2 0xc
97
98#define MONSYNC 0
99#define BISYNC 0x10
100#define SDLC 0x20
101#define EXTSYNC 0x30
102
103#define X1CLK 0x0
104#define X16CLK 0x40
105#define X32CLK 0x80
106#define X64CLK 0xC0
107
108
109
110#define TxCRC_ENAB 0x1
111#define RTS 0x2
112#define SDLC_CRC 0x4
113#define TxENAB 0x8
114#define SND_BRK 0x10
115#define Tx5 0x0
116#define Tx7 0x20
117#define Tx6 0x40
118#define Tx8 0x60
119#define DTR 0x80
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127
128#define VIS 1
129#define NV 2
130#define DLC 4
131#define MIE 8
132#define STATHI 0x10
133#define NORESET 0
134#define CHRB 0x40
135#define CHRA 0x80
136#define FHWRES 0xc0
137
138
139#define BIT6 1
140#define LOOPMODE 2
141#define ABUNDER 4
142#define MARKIDLE 8
143#define GAOP 0x10
144#define NRZ 0
145#define NRZI 0x20
146#define FM1 0x40
147#define FM0 0x60
148#define CRCPS 0x80
149
150
151#define TRxCXT 0
152#define TRxCTC 1
153#define TRxCBR 2
154#define TRxCDP 3
155#define TRxCOI 4
156#define TCRTxCP 0
157#define TCTRxCP 8
158#define TCBR 0x10
159#define TCDPLL 0x18
160#define RCRTxCP 0
161#define RCTRxCP 0x20
162#define RCBR 0x40
163#define RCDPLL 0x60
164#define RTxCX 0x80
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170
171#define BRENABL 1
172#define BRSRC 2
173#define DTRREQ 4
174#define AUTOECHO 8
175#define LOOPBAK 0x10
176#define SEARCH 0x20
177#define RMC 0x40
178#define DISDPLL 0x60
179#define SSBR 0x80
180#define SSRTxC 0xa0
181#define SFMM 0xc0
182#define SNRZI 0xe0
183
184
185#define PRIME 1
186#define ZCIE 2
187#define FIFOE 4
188#define DCDIE 8
189#define SYNCIE 0x10
190#define CTSIE 0x20
191#define TxUIE 0x40
192#define BRKIE 0x80
193
194
195
196#define Rx_CH_AV 0x1
197#define ZCOUNT 0x2
198#define Tx_BUF_EMP 0x4
199#define DCD 0x8
200#define SYNC_HUNT 0x10
201#define CTS 0x20
202#define TxEOM 0x40
203#define BRK_ABRT 0x80
204
205
206#define ALL_SNT 0x1
207
208#define RES3 0x8
209#define RES4 0x4
210#define RES5 0xc
211#define RES6 0x2
212#define RES7 0xa
213#define RES8 0x6
214#define RES18 0xe
215#define RES28 0x0
216
217#define PAR_ERR 0x10
218#define Rx_OVR 0x20
219#define CRC_ERR 0x40
220#define END_FR 0x80
221
222
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224
225#define CHBEXT 0x1
226#define CHBTxIP 0x2
227#define CHBRxIP 0x4
228#define CHAEXT 0x8
229#define CHATxIP 0x10
230#define CHARxIP 0x20
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234
235#define ONLOOP 2
236#define LOOPSEND 0x10
237#define CLK2MIS 0x40
238#define CLK1MIS 0x80
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250
251struct z8530_channel;
252
253struct z8530_irqhandler
254{
255 void (*rx)(struct z8530_channel *);
256 void (*tx)(struct z8530_channel *);
257 void (*status)(struct z8530_channel *);
258};
259
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263
264struct z8530_channel
265{
266 struct z8530_irqhandler *irqs;
267
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269
270 u16 count;
271 u16 max;
272 u16 mtu;
273 u8 *dptr;
274 struct sk_buff *skb;
275 struct sk_buff *skb2;
276 u8 status;
277 u8 dcdcheck;
278 u8 sync;
279
280 u8 regs[32];
281 u8 pendregs[32];
282
283 struct sk_buff *tx_skb;
284 struct sk_buff *tx_next_skb;
285 u8 *tx_ptr;
286 u8 *tx_next_ptr;
287 u8 *tx_dma_buf[2];
288 u8 tx_dma_used;
289 u16 txcount;
290
291 void (*rx_function)(struct z8530_channel *, struct sk_buff *);
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297 u8 rxdma;
298 u8 txdma;
299 u8 rxdma_on;
300 u8 txdma_on;
301 u8 dma_num;
302 u8 dma_ready;
303 u8 dma_tx;
304 u8 *rx_buf[2];
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310 struct z8530_dev *dev;
311 unsigned long ctrlio;
312 unsigned long dataio;
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316
317#define Z8530_PORT_SLEEP 0x80000000
318#define Z8530_PORT_OF(x) ((x)&0xFFFF)
319
320 u32 rx_overrun;
321 u32 rx_crc_err;
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327 void *private;
328 struct net_device *netdevice;
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334 struct tty_struct *tty;
335 int line;
336 wait_queue_head_t open_wait;
337 wait_queue_head_t close_wait;
338 unsigned long event;
339 int fdcount;
340 int blocked_open;
341 int x_char;
342 unsigned char *xmit_buf;
343 int xmit_head;
344 int xmit_tail;
345 int xmit_cnt;
346 int flags;
347 int timeout;
348 int xmit_fifo_size;
349
350 int close_delay;
351 unsigned short closing_wait;
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358 unsigned char clk_divisor;
359 int zs_baud;
360
361 int magic;
362 int baud_base;
363 int custom_divisor;
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365
366 unsigned char tx_active;
367 unsigned char tx_stopped;
368
369 spinlock_t *lock;
370};
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375
376struct z8530_dev
377{
378 char *name;
379 struct z8530_channel chanA;
380 struct z8530_channel chanB;
381 int type;
382#define Z8530 0
383#define Z85C30 1
384#define Z85230 2
385 int irq;
386 int active;
387
388 spinlock_t lock;
389};
390
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396extern u8 z8530_dead_port[];
397extern u8 z8530_hdlc_kilostream_85230[];
398extern u8 z8530_hdlc_kilostream[];
399irqreturn_t z8530_interrupt(int, void *);
400void z8530_describe(struct z8530_dev *, char *mapping, unsigned long io);
401int z8530_init(struct z8530_dev *);
402int z8530_shutdown(struct z8530_dev *);
403int z8530_sync_open(struct net_device *, struct z8530_channel *);
404int z8530_sync_close(struct net_device *, struct z8530_channel *);
405int z8530_sync_dma_open(struct net_device *, struct z8530_channel *);
406int z8530_sync_dma_close(struct net_device *, struct z8530_channel *);
407int z8530_sync_txdma_open(struct net_device *, struct z8530_channel *);
408int z8530_sync_txdma_close(struct net_device *, struct z8530_channel *);
409int z8530_channel_load(struct z8530_channel *, u8 *);
410netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb);
411void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb);
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418extern struct z8530_irqhandler z8530_sync, z8530_async, z8530_nop;
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427
428#define SERIAL_XMIT_SIZE 4096
429#define WAKEUP_CHARS 256
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434
435#define RS_EVENT_WRITE_WAKEUP 0
436
437
438#define ZILOG_INITIALIZED 0x80000000
439#define ZILOG_CALLOUT_ACTIVE 0x40000000
440#define ZILOG_NORMAL_ACTIVE 0x20000000
441#define ZILOG_BOOT_AUTOCONF 0x10000000
442#define ZILOG_CLOSING 0x08000000
443#define ZILOG_CTS_FLOW 0x04000000
444#define ZILOG_CHECK_CD 0x02000000
445
446#endif
447