linux/drivers/net/wireless/ath/ath5k/base.c
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   1/*-
   2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4 * Copyright (c) 2006 Devicescape Software, Inc.
   5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7 *
   8 * All rights reserved.
   9 *
  10 * Redistribution and use in source and binary forms, with or without
  11 * modification, are permitted provided that the following conditions
  12 * are met:
  13 * 1. Redistributions of source code must retain the above copyright
  14 *    notice, this list of conditions and the following disclaimer,
  15 *    without modification.
  16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18 *    redistribution must be conditioned upon including a substantially
  19 *    similar Disclaimer requirement for further binary redistribution.
  20 * 3. Neither the names of the above-listed copyright holders nor the names
  21 *    of any contributors may be used to endorse or promote products derived
  22 *    from this software without specific prior written permission.
  23 *
  24 * Alternatively, this software may be distributed under the terms of the
  25 * GNU General Public License ("GPL") version 2 as published by the Free
  26 * Software Foundation.
  27 *
  28 * NO WARRANTY
  29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39 * THE POSSIBILITY OF SUCH DAMAGES.
  40 *
  41 */
  42
  43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  44
  45#include <linux/module.h>
  46#include <linux/delay.h>
  47#include <linux/dma-mapping.h>
  48#include <linux/hardirq.h>
  49#include <linux/if.h>
  50#include <linux/io.h>
  51#include <linux/netdevice.h>
  52#include <linux/cache.h>
  53#include <linux/ethtool.h>
  54#include <linux/uaccess.h>
  55#include <linux/slab.h>
  56#include <linux/etherdevice.h>
  57#include <linux/nl80211.h>
  58
  59#include <net/cfg80211.h>
  60#include <net/ieee80211_radiotap.h>
  61
  62#include <asm/unaligned.h>
  63
  64#include <net/mac80211.h>
  65#include "base.h"
  66#include "reg.h"
  67#include "debug.h"
  68#include "ani.h"
  69#include "ath5k.h"
  70#include "../regd.h"
  71
  72#define CREATE_TRACE_POINTS
  73#include "trace.h"
  74
  75bool ath5k_modparam_nohwcrypt;
  76module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, 0444);
  77MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  78
  79static bool modparam_fastchanswitch;
  80module_param_named(fastchanswitch, modparam_fastchanswitch, bool, 0444);
  81MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
  82
  83static bool ath5k_modparam_no_hw_rfkill_switch;
  84module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
  85                   bool, 0444);
  86MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
  87
  88
  89/* Module info */
  90MODULE_AUTHOR("Jiri Slaby");
  91MODULE_AUTHOR("Nick Kossifidis");
  92MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  93MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  94MODULE_LICENSE("Dual BSD/GPL");
  95
  96static int ath5k_init(struct ieee80211_hw *hw);
  97static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
  98                                                                bool skip_pcu);
  99
 100/* Known SREVs */
 101static const struct ath5k_srev_name srev_names[] = {
 102#ifdef CONFIG_ATH5K_AHB
 103        { "5312",       AR5K_VERSION_MAC,       AR5K_SREV_AR5312_R2 },
 104        { "5312",       AR5K_VERSION_MAC,       AR5K_SREV_AR5312_R7 },
 105        { "2313",       AR5K_VERSION_MAC,       AR5K_SREV_AR2313_R8 },
 106        { "2315",       AR5K_VERSION_MAC,       AR5K_SREV_AR2315_R6 },
 107        { "2315",       AR5K_VERSION_MAC,       AR5K_SREV_AR2315_R7 },
 108        { "2317",       AR5K_VERSION_MAC,       AR5K_SREV_AR2317_R1 },
 109        { "2317",       AR5K_VERSION_MAC,       AR5K_SREV_AR2317_R2 },
 110#else
 111        { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
 112        { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
 113        { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
 114        { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
 115        { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
 116        { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
 117        { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
 118        { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
 119        { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
 120        { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
 121        { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
 122        { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
 123        { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
 124        { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
 125        { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
 126        { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
 127        { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
 128        { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
 129#endif
 130        { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
 131        { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 132        { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 133        { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
 134        { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 135        { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 136        { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 137        { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
 138        { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 139        { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 140        { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
 141        { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
 142        { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
 143        { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
 144        { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 145#ifdef CONFIG_ATH5K_AHB
 146        { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
 147        { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
 148#endif
 149        { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 150};
 151
 152static const struct ieee80211_rate ath5k_rates[] = {
 153        { .bitrate = 10,
 154          .hw_value = ATH5K_RATE_CODE_1M, },
 155        { .bitrate = 20,
 156          .hw_value = ATH5K_RATE_CODE_2M,
 157          .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 158          .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 159        { .bitrate = 55,
 160          .hw_value = ATH5K_RATE_CODE_5_5M,
 161          .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 162          .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 163        { .bitrate = 110,
 164          .hw_value = ATH5K_RATE_CODE_11M,
 165          .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 166          .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 167        { .bitrate = 60,
 168          .hw_value = ATH5K_RATE_CODE_6M,
 169          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 170                   IEEE80211_RATE_SUPPORTS_10MHZ },
 171        { .bitrate = 90,
 172          .hw_value = ATH5K_RATE_CODE_9M,
 173          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 174                   IEEE80211_RATE_SUPPORTS_10MHZ },
 175        { .bitrate = 120,
 176          .hw_value = ATH5K_RATE_CODE_12M,
 177          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 178                   IEEE80211_RATE_SUPPORTS_10MHZ },
 179        { .bitrate = 180,
 180          .hw_value = ATH5K_RATE_CODE_18M,
 181          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 182                   IEEE80211_RATE_SUPPORTS_10MHZ },
 183        { .bitrate = 240,
 184          .hw_value = ATH5K_RATE_CODE_24M,
 185          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 186                   IEEE80211_RATE_SUPPORTS_10MHZ },
 187        { .bitrate = 360,
 188          .hw_value = ATH5K_RATE_CODE_36M,
 189          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 190                   IEEE80211_RATE_SUPPORTS_10MHZ },
 191        { .bitrate = 480,
 192          .hw_value = ATH5K_RATE_CODE_48M,
 193          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 194                   IEEE80211_RATE_SUPPORTS_10MHZ },
 195        { .bitrate = 540,
 196          .hw_value = ATH5K_RATE_CODE_54M,
 197          .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
 198                   IEEE80211_RATE_SUPPORTS_10MHZ },
 199};
 200
 201static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 202{
 203        u64 tsf = ath5k_hw_get_tsf64(ah);
 204
 205        if ((tsf & 0x7fff) < rstamp)
 206                tsf -= 0x8000;
 207
 208        return (tsf & ~0x7fff) | rstamp;
 209}
 210
 211const char *
 212ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 213{
 214        const char *name = "xxxxx";
 215        unsigned int i;
 216
 217        for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 218                if (srev_names[i].sr_type != type)
 219                        continue;
 220
 221                if ((val & 0xf0) == srev_names[i].sr_val)
 222                        name = srev_names[i].sr_name;
 223
 224                if ((val & 0xff) == srev_names[i].sr_val) {
 225                        name = srev_names[i].sr_name;
 226                        break;
 227                }
 228        }
 229
 230        return name;
 231}
 232static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
 233{
 234        struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
 235        return ath5k_hw_reg_read(ah, reg_offset);
 236}
 237
 238static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
 239{
 240        struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
 241        ath5k_hw_reg_write(ah, val, reg_offset);
 242}
 243
 244static const struct ath_ops ath5k_common_ops = {
 245        .read = ath5k_ioread32,
 246        .write = ath5k_iowrite32,
 247};
 248
 249/***********************\
 250* Driver Initialization *
 251\***********************/
 252
 253static void ath5k_reg_notifier(struct wiphy *wiphy,
 254                               struct regulatory_request *request)
 255{
 256        struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
 257        struct ath5k_hw *ah = hw->priv;
 258        struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
 259
 260        ath_reg_notifier_apply(wiphy, request, regulatory);
 261}
 262
 263/********************\
 264* Channel/mode setup *
 265\********************/
 266
 267/*
 268 * Returns true for the channel numbers used.
 269 */
 270#ifdef CONFIG_ATH5K_TEST_CHANNELS
 271static bool ath5k_is_standard_channel(short chan, enum nl80211_band band)
 272{
 273        return true;
 274}
 275
 276#else
 277static bool ath5k_is_standard_channel(short chan, enum nl80211_band band)
 278{
 279        if (band == NL80211_BAND_2GHZ && chan <= 14)
 280                return true;
 281
 282        return  /* UNII 1,2 */
 283                (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
 284                /* midband */
 285                ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
 286                /* UNII-3 */
 287                ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
 288                /* 802.11j 5.030-5.080 GHz (20MHz) */
 289                (chan == 8 || chan == 12 || chan == 16) ||
 290                /* 802.11j 4.9GHz (20MHz) */
 291                (chan == 184 || chan == 188 || chan == 192 || chan == 196));
 292}
 293#endif
 294
 295static unsigned int
 296ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
 297                unsigned int mode, unsigned int max)
 298{
 299        unsigned int count, size, freq, ch;
 300        enum nl80211_band band;
 301
 302        switch (mode) {
 303        case AR5K_MODE_11A:
 304                /* 1..220, but 2GHz frequencies are filtered by check_channel */
 305                size = 220;
 306                band = NL80211_BAND_5GHZ;
 307                break;
 308        case AR5K_MODE_11B:
 309        case AR5K_MODE_11G:
 310                size = 26;
 311                band = NL80211_BAND_2GHZ;
 312                break;
 313        default:
 314                ATH5K_WARN(ah, "bad mode, not copying channels\n");
 315                return 0;
 316        }
 317
 318        count = 0;
 319        for (ch = 1; ch <= size && count < max; ch++) {
 320                freq = ieee80211_channel_to_frequency(ch, band);
 321
 322                if (freq == 0) /* mapping failed - not a standard channel */
 323                        continue;
 324
 325                /* Write channel info, needed for ath5k_channel_ok() */
 326                channels[count].center_freq = freq;
 327                channels[count].band = band;
 328                channels[count].hw_value = mode;
 329
 330                /* Check if channel is supported by the chipset */
 331                if (!ath5k_channel_ok(ah, &channels[count]))
 332                        continue;
 333
 334                if (!ath5k_is_standard_channel(ch, band))
 335                        continue;
 336
 337                count++;
 338        }
 339
 340        return count;
 341}
 342
 343static void
 344ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
 345{
 346        u8 i;
 347
 348        for (i = 0; i < AR5K_MAX_RATES; i++)
 349                ah->rate_idx[b->band][i] = -1;
 350
 351        for (i = 0; i < b->n_bitrates; i++) {
 352                ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 353                if (b->bitrates[i].hw_value_short)
 354                        ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 355        }
 356}
 357
 358static int
 359ath5k_setup_bands(struct ieee80211_hw *hw)
 360{
 361        struct ath5k_hw *ah = hw->priv;
 362        struct ieee80211_supported_band *sband;
 363        int max_c, count_c = 0;
 364        int i;
 365
 366        BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS);
 367        max_c = ARRAY_SIZE(ah->channels);
 368
 369        /* 2GHz band */
 370        sband = &ah->sbands[NL80211_BAND_2GHZ];
 371        sband->band = NL80211_BAND_2GHZ;
 372        sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0];
 373
 374        if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
 375                /* G mode */
 376                memcpy(sband->bitrates, &ath5k_rates[0],
 377                       sizeof(struct ieee80211_rate) * 12);
 378                sband->n_bitrates = 12;
 379
 380                sband->channels = ah->channels;
 381                sband->n_channels = ath5k_setup_channels(ah, sband->channels,
 382                                        AR5K_MODE_11G, max_c);
 383
 384                hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
 385                count_c = sband->n_channels;
 386                max_c -= count_c;
 387        } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
 388                /* B mode */
 389                memcpy(sband->bitrates, &ath5k_rates[0],
 390                       sizeof(struct ieee80211_rate) * 4);
 391                sband->n_bitrates = 4;
 392
 393                /* 5211 only supports B rates and uses 4bit rate codes
 394                 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 395                 * fix them up here:
 396                 */
 397                if (ah->ah_version == AR5K_AR5211) {
 398                        for (i = 0; i < 4; i++) {
 399                                sband->bitrates[i].hw_value =
 400                                        sband->bitrates[i].hw_value & 0xF;
 401                                sband->bitrates[i].hw_value_short =
 402                                        sband->bitrates[i].hw_value_short & 0xF;
 403                        }
 404                }
 405
 406                sband->channels = ah->channels;
 407                sband->n_channels = ath5k_setup_channels(ah, sband->channels,
 408                                        AR5K_MODE_11B, max_c);
 409
 410                hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
 411                count_c = sband->n_channels;
 412                max_c -= count_c;
 413        }
 414        ath5k_setup_rate_idx(ah, sband);
 415
 416        /* 5GHz band, A mode */
 417        if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
 418                sband = &ah->sbands[NL80211_BAND_5GHZ];
 419                sband->band = NL80211_BAND_5GHZ;
 420                sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0];
 421
 422                memcpy(sband->bitrates, &ath5k_rates[4],
 423                       sizeof(struct ieee80211_rate) * 8);
 424                sband->n_bitrates = 8;
 425
 426                sband->channels = &ah->channels[count_c];
 427                sband->n_channels = ath5k_setup_channels(ah, sband->channels,
 428                                        AR5K_MODE_11A, max_c);
 429
 430                hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
 431        }
 432        ath5k_setup_rate_idx(ah, sband);
 433
 434        ath5k_debug_dump_bands(ah);
 435
 436        return 0;
 437}
 438
 439/*
 440 * Set/change channels. We always reset the chip.
 441 * To accomplish this we must first cleanup any pending DMA,
 442 * then restart stuff after a la  ath5k_init.
 443 *
 444 * Called with ah->lock.
 445 */
 446int
 447ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef)
 448{
 449        ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
 450                  "channel set, resetting (%u -> %u MHz)\n",
 451                  ah->curchan->center_freq, chandef->chan->center_freq);
 452
 453        switch (chandef->width) {
 454        case NL80211_CHAN_WIDTH_20:
 455        case NL80211_CHAN_WIDTH_20_NOHT:
 456                ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
 457                break;
 458        case NL80211_CHAN_WIDTH_5:
 459                ah->ah_bwmode = AR5K_BWMODE_5MHZ;
 460                break;
 461        case NL80211_CHAN_WIDTH_10:
 462                ah->ah_bwmode = AR5K_BWMODE_10MHZ;
 463                break;
 464        default:
 465                WARN_ON(1);
 466                return -EINVAL;
 467        }
 468
 469        /*
 470         * To switch channels clear any pending DMA operations;
 471         * wait long enough for the RX fifo to drain, reset the
 472         * hardware at the new frequency, and then re-enable
 473         * the relevant bits of the h/w.
 474         */
 475        return ath5k_reset(ah, chandef->chan, true);
 476}
 477
 478void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
 479{
 480        struct ath5k_vif_iter_data *iter_data = data;
 481        int i;
 482        struct ath5k_vif *avf = (void *)vif->drv_priv;
 483
 484        if (iter_data->hw_macaddr)
 485                for (i = 0; i < ETH_ALEN; i++)
 486                        iter_data->mask[i] &=
 487                                ~(iter_data->hw_macaddr[i] ^ mac[i]);
 488
 489        if (!iter_data->found_active) {
 490                iter_data->found_active = true;
 491                memcpy(iter_data->active_mac, mac, ETH_ALEN);
 492        }
 493
 494        if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
 495                if (ether_addr_equal(iter_data->hw_macaddr, mac))
 496                        iter_data->need_set_hw_addr = false;
 497
 498        if (!iter_data->any_assoc) {
 499                if (avf->assoc)
 500                        iter_data->any_assoc = true;
 501        }
 502
 503        /* Calculate combined mode - when APs are active, operate in AP mode.
 504         * Otherwise use the mode of the new interface. This can currently
 505         * only deal with combinations of APs and STAs. Only one ad-hoc
 506         * interfaces is allowed.
 507         */
 508        if (avf->opmode == NL80211_IFTYPE_AP)
 509                iter_data->opmode = NL80211_IFTYPE_AP;
 510        else {
 511                if (avf->opmode == NL80211_IFTYPE_STATION)
 512                        iter_data->n_stas++;
 513                if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
 514                        iter_data->opmode = avf->opmode;
 515        }
 516}
 517
 518void
 519ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
 520                                   struct ieee80211_vif *vif)
 521{
 522        struct ath_common *common = ath5k_hw_common(ah);
 523        struct ath5k_vif_iter_data iter_data;
 524        u32 rfilt;
 525
 526        /*
 527         * Use the hardware MAC address as reference, the hardware uses it
 528         * together with the BSSID mask when matching addresses.
 529         */
 530        iter_data.hw_macaddr = common->macaddr;
 531        eth_broadcast_addr(iter_data.mask);
 532        iter_data.found_active = false;
 533        iter_data.need_set_hw_addr = true;
 534        iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
 535        iter_data.n_stas = 0;
 536
 537        if (vif)
 538                ath5k_vif_iter(&iter_data, vif->addr, vif);
 539
 540        /* Get list of all active MAC addresses */
 541        ieee80211_iterate_active_interfaces_atomic(
 542                ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
 543                ath5k_vif_iter, &iter_data);
 544        memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
 545
 546        ah->opmode = iter_data.opmode;
 547        if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
 548                /* Nothing active, default to station mode */
 549                ah->opmode = NL80211_IFTYPE_STATION;
 550
 551        ath5k_hw_set_opmode(ah, ah->opmode);
 552        ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
 553                  ah->opmode, ath_opmode_to_string(ah->opmode));
 554
 555        if (iter_data.need_set_hw_addr && iter_data.found_active)
 556                ath5k_hw_set_lladdr(ah, iter_data.active_mac);
 557
 558        if (ath5k_hw_hasbssidmask(ah))
 559                ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
 560
 561        /* Set up RX Filter */
 562        if (iter_data.n_stas > 1) {
 563                /* If you have multiple STA interfaces connected to
 564                 * different APs, ARPs are not received (most of the time?)
 565                 * Enabling PROMISC appears to fix that problem.
 566                 */
 567                ah->filter_flags |= AR5K_RX_FILTER_PROM;
 568        }
 569
 570        rfilt = ah->filter_flags;
 571        ath5k_hw_set_rx_filter(ah, rfilt);
 572        ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
 573}
 574
 575static inline int
 576ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
 577{
 578        int rix;
 579
 580        /* return base rate on errors */
 581        if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
 582                        "hw_rix out of bounds: %x\n", hw_rix))
 583                return 0;
 584
 585        rix = ah->rate_idx[ah->curchan->band][hw_rix];
 586        if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
 587                rix = 0;
 588
 589        return rix;
 590}
 591
 592/***************\
 593* Buffers setup *
 594\***************/
 595
 596static
 597struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
 598{
 599        struct ath_common *common = ath5k_hw_common(ah);
 600        struct sk_buff *skb;
 601
 602        /*
 603         * Allocate buffer with headroom_needed space for the
 604         * fake physical layer header at the start.
 605         */
 606        skb = ath_rxbuf_alloc(common,
 607                              common->rx_bufsize,
 608                              GFP_ATOMIC);
 609
 610        if (!skb) {
 611                ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
 612                                common->rx_bufsize);
 613                return NULL;
 614        }
 615
 616        *skb_addr = dma_map_single(ah->dev,
 617                                   skb->data, common->rx_bufsize,
 618                                   DMA_FROM_DEVICE);
 619
 620        if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
 621                ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
 622                dev_kfree_skb(skb);
 623                return NULL;
 624        }
 625        return skb;
 626}
 627
 628static int
 629ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
 630{
 631        struct sk_buff *skb = bf->skb;
 632        struct ath5k_desc *ds;
 633        int ret;
 634
 635        if (!skb) {
 636                skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
 637                if (!skb)
 638                        return -ENOMEM;
 639                bf->skb = skb;
 640        }
 641
 642        /*
 643         * Setup descriptors.  For receive we always terminate
 644         * the descriptor list with a self-linked entry so we'll
 645         * not get overrun under high load (as can happen with a
 646         * 5212 when ANI processing enables PHY error frames).
 647         *
 648         * To ensure the last descriptor is self-linked we create
 649         * each descriptor as self-linked and add it to the end.  As
 650         * each additional descriptor is added the previous self-linked
 651         * entry is "fixed" naturally.  This should be safe even
 652         * if DMA is happening.  When processing RX interrupts we
 653         * never remove/process the last, self-linked, entry on the
 654         * descriptor list.  This ensures the hardware always has
 655         * someplace to write a new frame.
 656         */
 657        ds = bf->desc;
 658        ds->ds_link = bf->daddr;        /* link to self */
 659        ds->ds_data = bf->skbaddr;
 660        ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
 661        if (ret) {
 662                ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
 663                return ret;
 664        }
 665
 666        if (ah->rxlink != NULL)
 667                *ah->rxlink = bf->daddr;
 668        ah->rxlink = &ds->ds_link;
 669        return 0;
 670}
 671
 672static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
 673{
 674        struct ieee80211_hdr *hdr;
 675        enum ath5k_pkt_type htype;
 676        __le16 fc;
 677
 678        hdr = (struct ieee80211_hdr *)skb->data;
 679        fc = hdr->frame_control;
 680
 681        if (ieee80211_is_beacon(fc))
 682                htype = AR5K_PKT_TYPE_BEACON;
 683        else if (ieee80211_is_probe_resp(fc))
 684                htype = AR5K_PKT_TYPE_PROBE_RESP;
 685        else if (ieee80211_is_atim(fc))
 686                htype = AR5K_PKT_TYPE_ATIM;
 687        else if (ieee80211_is_pspoll(fc))
 688                htype = AR5K_PKT_TYPE_PSPOLL;
 689        else
 690                htype = AR5K_PKT_TYPE_NORMAL;
 691
 692        return htype;
 693}
 694
 695static struct ieee80211_rate *
 696ath5k_get_rate(const struct ieee80211_hw *hw,
 697               const struct ieee80211_tx_info *info,
 698               struct ath5k_buf *bf, int idx)
 699{
 700        /*
 701        * convert a ieee80211_tx_rate RC-table entry to
 702        * the respective ieee80211_rate struct
 703        */
 704        if (bf->rates[idx].idx < 0) {
 705                return NULL;
 706        }
 707
 708        return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ];
 709}
 710
 711static u16
 712ath5k_get_rate_hw_value(const struct ieee80211_hw *hw,
 713                        const struct ieee80211_tx_info *info,
 714                        struct ath5k_buf *bf, int idx)
 715{
 716        struct ieee80211_rate *rate;
 717        u16 hw_rate;
 718        u8 rc_flags;
 719
 720        rate = ath5k_get_rate(hw, info, bf, idx);
 721        if (!rate)
 722                return 0;
 723
 724        rc_flags = bf->rates[idx].flags;
 725        hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
 726                   rate->hw_value_short : rate->hw_value;
 727
 728        return hw_rate;
 729}
 730
 731static int
 732ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
 733                  struct ath5k_txq *txq, int padsize,
 734                  struct ieee80211_tx_control *control)
 735{
 736        struct ath5k_desc *ds = bf->desc;
 737        struct sk_buff *skb = bf->skb;
 738        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 739        unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
 740        struct ieee80211_rate *rate;
 741        unsigned int mrr_rate[3], mrr_tries[3];
 742        int i, ret;
 743        u16 hw_rate;
 744        u16 cts_rate = 0;
 745        u16 duration = 0;
 746        u8 rc_flags;
 747
 748        flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
 749
 750        /* XXX endianness */
 751        bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
 752                        DMA_TO_DEVICE);
 753
 754        if (dma_mapping_error(ah->dev, bf->skbaddr))
 755                return -ENOSPC;
 756
 757        ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates,
 758                               ARRAY_SIZE(bf->rates));
 759
 760        rate = ath5k_get_rate(ah->hw, info, bf, 0);
 761
 762        if (!rate) {
 763                ret = -EINVAL;
 764                goto err_unmap;
 765        }
 766
 767        if (info->flags & IEEE80211_TX_CTL_NO_ACK)
 768                flags |= AR5K_TXDESC_NOACK;
 769
 770        rc_flags = bf->rates[0].flags;
 771
 772        hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0);
 773
 774        pktlen = skb->len;
 775
 776        /* FIXME: If we are in g mode and rate is a CCK rate
 777         * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
 778         * from tx power (value is in dB units already) */
 779        if (info->control.hw_key) {
 780                keyidx = info->control.hw_key->hw_key_idx;
 781                pktlen += info->control.hw_key->icv_len;
 782        }
 783        if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
 784                flags |= AR5K_TXDESC_RTSENA;
 785                cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
 786                duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
 787                        info->control.vif, pktlen, info));
 788        }
 789        if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
 790                flags |= AR5K_TXDESC_CTSENA;
 791                cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
 792                duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
 793                        info->control.vif, pktlen, info));
 794        }
 795
 796        ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
 797                ieee80211_get_hdrlen_from_skb(skb), padsize,
 798                get_hw_packet_type(skb),
 799                (ah->ah_txpower.txp_requested * 2),
 800                hw_rate,
 801                bf->rates[0].count, keyidx, ah->ah_tx_ant, flags,
 802                cts_rate, duration);
 803        if (ret)
 804                goto err_unmap;
 805
 806        /* Set up MRR descriptor */
 807        if (ah->ah_capabilities.cap_has_mrr_support) {
 808                memset(mrr_rate, 0, sizeof(mrr_rate));
 809                memset(mrr_tries, 0, sizeof(mrr_tries));
 810
 811                for (i = 0; i < 3; i++) {
 812
 813                        rate = ath5k_get_rate(ah->hw, info, bf, i);
 814                        if (!rate)
 815                                break;
 816
 817                        mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i);
 818                        mrr_tries[i] = bf->rates[i].count;
 819                }
 820
 821                ath5k_hw_setup_mrr_tx_desc(ah, ds,
 822                        mrr_rate[0], mrr_tries[0],
 823                        mrr_rate[1], mrr_tries[1],
 824                        mrr_rate[2], mrr_tries[2]);
 825        }
 826
 827        ds->ds_link = 0;
 828        ds->ds_data = bf->skbaddr;
 829
 830        spin_lock_bh(&txq->lock);
 831        list_add_tail(&bf->list, &txq->q);
 832        txq->txq_len++;
 833        if (txq->link == NULL) /* is this first packet? */
 834                ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
 835        else /* no, so only link it */
 836                *txq->link = bf->daddr;
 837
 838        txq->link = &ds->ds_link;
 839        ath5k_hw_start_tx_dma(ah, txq->qnum);
 840        spin_unlock_bh(&txq->lock);
 841
 842        return 0;
 843err_unmap:
 844        dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
 845        return ret;
 846}
 847
 848/*******************\
 849* Descriptors setup *
 850\*******************/
 851
 852static int
 853ath5k_desc_alloc(struct ath5k_hw *ah)
 854{
 855        struct ath5k_desc *ds;
 856        struct ath5k_buf *bf;
 857        dma_addr_t da;
 858        unsigned int i;
 859        int ret;
 860
 861        /* allocate descriptors */
 862        ah->desc_len = sizeof(struct ath5k_desc) *
 863                        (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
 864
 865        ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
 866                                &ah->desc_daddr, GFP_KERNEL);
 867        if (ah->desc == NULL) {
 868                ATH5K_ERR(ah, "can't allocate descriptors\n");
 869                ret = -ENOMEM;
 870                goto err;
 871        }
 872        ds = ah->desc;
 873        da = ah->desc_daddr;
 874        ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
 875                ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
 876
 877        bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
 878                        sizeof(struct ath5k_buf), GFP_KERNEL);
 879        if (bf == NULL) {
 880                ATH5K_ERR(ah, "can't allocate bufptr\n");
 881                ret = -ENOMEM;
 882                goto err_free;
 883        }
 884        ah->bufptr = bf;
 885
 886        INIT_LIST_HEAD(&ah->rxbuf);
 887        for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
 888                bf->desc = ds;
 889                bf->daddr = da;
 890                list_add_tail(&bf->list, &ah->rxbuf);
 891        }
 892
 893        INIT_LIST_HEAD(&ah->txbuf);
 894        ah->txbuf_len = ATH_TXBUF;
 895        for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
 896                bf->desc = ds;
 897                bf->daddr = da;
 898                list_add_tail(&bf->list, &ah->txbuf);
 899        }
 900
 901        /* beacon buffers */
 902        INIT_LIST_HEAD(&ah->bcbuf);
 903        for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
 904                bf->desc = ds;
 905                bf->daddr = da;
 906                list_add_tail(&bf->list, &ah->bcbuf);
 907        }
 908
 909        return 0;
 910err_free:
 911        dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
 912err:
 913        ah->desc = NULL;
 914        return ret;
 915}
 916
 917void
 918ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
 919{
 920        BUG_ON(!bf);
 921        if (!bf->skb)
 922                return;
 923        dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
 924                        DMA_TO_DEVICE);
 925        ieee80211_free_txskb(ah->hw, bf->skb);
 926        bf->skb = NULL;
 927        bf->skbaddr = 0;
 928        bf->desc->ds_data = 0;
 929}
 930
 931void
 932ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
 933{
 934        struct ath_common *common = ath5k_hw_common(ah);
 935
 936        BUG_ON(!bf);
 937        if (!bf->skb)
 938                return;
 939        dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
 940                        DMA_FROM_DEVICE);
 941        dev_kfree_skb_any(bf->skb);
 942        bf->skb = NULL;
 943        bf->skbaddr = 0;
 944        bf->desc->ds_data = 0;
 945}
 946
 947static void
 948ath5k_desc_free(struct ath5k_hw *ah)
 949{
 950        struct ath5k_buf *bf;
 951
 952        list_for_each_entry(bf, &ah->txbuf, list)
 953                ath5k_txbuf_free_skb(ah, bf);
 954        list_for_each_entry(bf, &ah->rxbuf, list)
 955                ath5k_rxbuf_free_skb(ah, bf);
 956        list_for_each_entry(bf, &ah->bcbuf, list)
 957                ath5k_txbuf_free_skb(ah, bf);
 958
 959        /* Free memory associated with all descriptors */
 960        dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
 961        ah->desc = NULL;
 962        ah->desc_daddr = 0;
 963
 964        kfree(ah->bufptr);
 965        ah->bufptr = NULL;
 966}
 967
 968
 969/**************\
 970* Queues setup *
 971\**************/
 972
 973static struct ath5k_txq *
 974ath5k_txq_setup(struct ath5k_hw *ah,
 975                int qtype, int subtype)
 976{
 977        struct ath5k_txq *txq;
 978        struct ath5k_txq_info qi = {
 979                .tqi_subtype = subtype,
 980                /* XXX: default values not correct for B and XR channels,
 981                 * but who cares? */
 982                .tqi_aifs = AR5K_TUNE_AIFS,
 983                .tqi_cw_min = AR5K_TUNE_CWMIN,
 984                .tqi_cw_max = AR5K_TUNE_CWMAX
 985        };
 986        int qnum;
 987
 988        /*
 989         * Enable interrupts only for EOL and DESC conditions.
 990         * We mark tx descriptors to receive a DESC interrupt
 991         * when a tx queue gets deep; otherwise we wait for the
 992         * EOL to reap descriptors.  Note that this is done to
 993         * reduce interrupt load and this only defers reaping
 994         * descriptors, never transmitting frames.  Aside from
 995         * reducing interrupts this also permits more concurrency.
 996         * The only potential downside is if the tx queue backs
 997         * up in which case the top half of the kernel may backup
 998         * due to a lack of tx descriptors.
 999         */
1000        qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1001                                AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1002        qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1003        if (qnum < 0) {
1004                /*
1005                 * NB: don't print a message, this happens
1006                 * normally on parts with too few tx queues
1007                 */
1008                return ERR_PTR(qnum);
1009        }
1010        txq = &ah->txqs[qnum];
1011        if (!txq->setup) {
1012                txq->qnum = qnum;
1013                txq->link = NULL;
1014                INIT_LIST_HEAD(&txq->q);
1015                spin_lock_init(&txq->lock);
1016                txq->setup = true;
1017                txq->txq_len = 0;
1018                txq->txq_max = ATH5K_TXQ_LEN_MAX;
1019                txq->txq_poll_mark = false;
1020                txq->txq_stuck = 0;
1021        }
1022        return &ah->txqs[qnum];
1023}
1024
1025static int
1026ath5k_beaconq_setup(struct ath5k_hw *ah)
1027{
1028        struct ath5k_txq_info qi = {
1029                /* XXX: default values not correct for B and XR channels,
1030                 * but who cares? */
1031                .tqi_aifs = AR5K_TUNE_AIFS,
1032                .tqi_cw_min = AR5K_TUNE_CWMIN,
1033                .tqi_cw_max = AR5K_TUNE_CWMAX,
1034                /* NB: for dynamic turbo, don't enable any other interrupts */
1035                .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1036        };
1037
1038        return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1039}
1040
1041static int
1042ath5k_beaconq_config(struct ath5k_hw *ah)
1043{
1044        struct ath5k_txq_info qi;
1045        int ret;
1046
1047        ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
1048        if (ret)
1049                goto err;
1050
1051        if (ah->opmode == NL80211_IFTYPE_AP ||
1052            ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1053                /*
1054                 * Always burst out beacon and CAB traffic
1055                 * (aifs = cwmin = cwmax = 0)
1056                 */
1057                qi.tqi_aifs = 0;
1058                qi.tqi_cw_min = 0;
1059                qi.tqi_cw_max = 0;
1060        } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
1061                /*
1062                 * Adhoc mode; backoff between 0 and (2 * cw_min).
1063                 */
1064                qi.tqi_aifs = 0;
1065                qi.tqi_cw_min = 0;
1066                qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1067        }
1068
1069        ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1070                "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1071                qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1072
1073        ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1074        if (ret) {
1075                ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1076                        "hardware queue!\n", __func__);
1077                goto err;
1078        }
1079        ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
1080        if (ret)
1081                goto err;
1082
1083        /* reconfigure cabq with ready time to 80% of beacon_interval */
1084        ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1085        if (ret)
1086                goto err;
1087
1088        qi.tqi_ready_time = (ah->bintval * 80) / 100;
1089        ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1090        if (ret)
1091                goto err;
1092
1093        ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1094err:
1095        return ret;
1096}
1097
1098/**
1099 * ath5k_drain_tx_buffs - Empty tx buffers
1100 *
1101 * @ah: The &struct ath5k_hw
1102 *
1103 * Empty tx buffers from all queues in preparation
1104 * of a reset or during shutdown.
1105 *
1106 * NB:  this assumes output has been stopped and
1107 *      we do not need to block ath5k_tx_tasklet
1108 */
1109static void
1110ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1111{
1112        struct ath5k_txq *txq;
1113        struct ath5k_buf *bf, *bf0;
1114        int i;
1115
1116        for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1117                if (ah->txqs[i].setup) {
1118                        txq = &ah->txqs[i];
1119                        spin_lock_bh(&txq->lock);
1120                        list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1121                                ath5k_debug_printtxbuf(ah, bf);
1122
1123                                ath5k_txbuf_free_skb(ah, bf);
1124
1125                                spin_lock(&ah->txbuflock);
1126                                list_move_tail(&bf->list, &ah->txbuf);
1127                                ah->txbuf_len++;
1128                                txq->txq_len--;
1129                                spin_unlock(&ah->txbuflock);
1130                        }
1131                        txq->link = NULL;
1132                        txq->txq_poll_mark = false;
1133                        spin_unlock_bh(&txq->lock);
1134                }
1135        }
1136}
1137
1138static void
1139ath5k_txq_release(struct ath5k_hw *ah)
1140{
1141        struct ath5k_txq *txq = ah->txqs;
1142        unsigned int i;
1143
1144        for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1145                if (txq->setup) {
1146                        ath5k_hw_release_tx_queue(ah, txq->qnum);
1147                        txq->setup = false;
1148                }
1149}
1150
1151
1152/*************\
1153* RX Handling *
1154\*************/
1155
1156/*
1157 * Enable the receive h/w following a reset.
1158 */
1159static int
1160ath5k_rx_start(struct ath5k_hw *ah)
1161{
1162        struct ath_common *common = ath5k_hw_common(ah);
1163        struct ath5k_buf *bf;
1164        int ret;
1165
1166        common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1167
1168        ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1169                  common->cachelsz, common->rx_bufsize);
1170
1171        spin_lock_bh(&ah->rxbuflock);
1172        ah->rxlink = NULL;
1173        list_for_each_entry(bf, &ah->rxbuf, list) {
1174                ret = ath5k_rxbuf_setup(ah, bf);
1175                if (ret != 0) {
1176                        spin_unlock_bh(&ah->rxbuflock);
1177                        goto err;
1178                }
1179        }
1180        bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1181        ath5k_hw_set_rxdp(ah, bf->daddr);
1182        spin_unlock_bh(&ah->rxbuflock);
1183
1184        ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1185        ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
1186        ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1187
1188        return 0;
1189err:
1190        return ret;
1191}
1192
1193/*
1194 * Disable the receive logic on PCU (DRU)
1195 * In preparation for a shutdown.
1196 *
1197 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1198 * does.
1199 */
1200static void
1201ath5k_rx_stop(struct ath5k_hw *ah)
1202{
1203
1204        ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1205        ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1206
1207        ath5k_debug_printrxbuffs(ah);
1208}
1209
1210static unsigned int
1211ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1212                   struct ath5k_rx_status *rs)
1213{
1214        struct ath_common *common = ath5k_hw_common(ah);
1215        struct ieee80211_hdr *hdr = (void *)skb->data;
1216        unsigned int keyix, hlen;
1217
1218        if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1219                        rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1220                return RX_FLAG_DECRYPTED;
1221
1222        /* Apparently when a default key is used to decrypt the packet
1223           the hw does not set the index used to decrypt.  In such cases
1224           get the index from the packet. */
1225        hlen = ieee80211_hdrlen(hdr->frame_control);
1226        if (ieee80211_has_protected(hdr->frame_control) &&
1227            !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1228            skb->len >= hlen + 4) {
1229                keyix = skb->data[hlen + 3] >> 6;
1230
1231                if (test_bit(keyix, common->keymap))
1232                        return RX_FLAG_DECRYPTED;
1233        }
1234
1235        return 0;
1236}
1237
1238
1239static void
1240ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1241                     struct ieee80211_rx_status *rxs)
1242{
1243        u64 tsf, bc_tstamp;
1244        u32 hw_tu;
1245        struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1246
1247        if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) {
1248                /*
1249                 * Received an IBSS beacon with the same BSSID. Hardware *must*
1250                 * have updated the local TSF. We have to work around various
1251                 * hardware bugs, though...
1252                 */
1253                tsf = ath5k_hw_get_tsf64(ah);
1254                bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1255                hw_tu = TSF_TO_TU(tsf);
1256
1257                ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1258                        "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1259                        (unsigned long long)bc_tstamp,
1260                        (unsigned long long)rxs->mactime,
1261                        (unsigned long long)(rxs->mactime - bc_tstamp),
1262                        (unsigned long long)tsf);
1263
1264                /*
1265                 * Sometimes the HW will give us a wrong tstamp in the rx
1266                 * status, causing the timestamp extension to go wrong.
1267                 * (This seems to happen especially with beacon frames bigger
1268                 * than 78 byte (incl. FCS))
1269                 * But we know that the receive timestamp must be later than the
1270                 * timestamp of the beacon since HW must have synced to that.
1271                 *
1272                 * NOTE: here we assume mactime to be after the frame was
1273                 * received, not like mac80211 which defines it at the start.
1274                 */
1275                if (bc_tstamp > rxs->mactime) {
1276                        ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1277                                "fixing mactime from %llx to %llx\n",
1278                                (unsigned long long)rxs->mactime,
1279                                (unsigned long long)tsf);
1280                        rxs->mactime = tsf;
1281                }
1282
1283                /*
1284                 * Local TSF might have moved higher than our beacon timers,
1285                 * in that case we have to update them to continue sending
1286                 * beacons. This also takes care of synchronizing beacon sending
1287                 * times with other stations.
1288                 */
1289                if (hw_tu >= ah->nexttbtt)
1290                        ath5k_beacon_update_timers(ah, bc_tstamp);
1291
1292                /* Check if the beacon timers are still correct, because a TSF
1293                 * update might have created a window between them - for a
1294                 * longer description see the comment of this function: */
1295                if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1296                        ath5k_beacon_update_timers(ah, bc_tstamp);
1297                        ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1298                                "fixed beacon timers after beacon receive\n");
1299                }
1300        }
1301}
1302
1303/*
1304 * Compute padding position. skb must contain an IEEE 802.11 frame
1305 */
1306static int ath5k_common_padpos(struct sk_buff *skb)
1307{
1308        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1309        __le16 frame_control = hdr->frame_control;
1310        int padpos = 24;
1311
1312        if (ieee80211_has_a4(frame_control))
1313                padpos += ETH_ALEN;
1314
1315        if (ieee80211_is_data_qos(frame_control))
1316                padpos += IEEE80211_QOS_CTL_LEN;
1317
1318        return padpos;
1319}
1320
1321/*
1322 * This function expects an 802.11 frame and returns the number of
1323 * bytes added, or -1 if we don't have enough header room.
1324 */
1325static int ath5k_add_padding(struct sk_buff *skb)
1326{
1327        int padpos = ath5k_common_padpos(skb);
1328        int padsize = padpos & 3;
1329
1330        if (padsize && skb->len > padpos) {
1331
1332                if (skb_headroom(skb) < padsize)
1333                        return -1;
1334
1335                skb_push(skb, padsize);
1336                memmove(skb->data, skb->data + padsize, padpos);
1337                return padsize;
1338        }
1339
1340        return 0;
1341}
1342
1343/*
1344 * The MAC header is padded to have 32-bit boundary if the
1345 * packet payload is non-zero. The general calculation for
1346 * padsize would take into account odd header lengths:
1347 * padsize = 4 - (hdrlen & 3); however, since only
1348 * even-length headers are used, padding can only be 0 or 2
1349 * bytes and we can optimize this a bit.  We must not try to
1350 * remove padding from short control frames that do not have a
1351 * payload.
1352 *
1353 * This function expects an 802.11 frame and returns the number of
1354 * bytes removed.
1355 */
1356static int ath5k_remove_padding(struct sk_buff *skb)
1357{
1358        int padpos = ath5k_common_padpos(skb);
1359        int padsize = padpos & 3;
1360
1361        if (padsize && skb->len >= padpos + padsize) {
1362                memmove(skb->data + padsize, skb->data, padpos);
1363                skb_pull(skb, padsize);
1364                return padsize;
1365        }
1366
1367        return 0;
1368}
1369
1370static void
1371ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1372                    struct ath5k_rx_status *rs)
1373{
1374        struct ieee80211_rx_status *rxs;
1375        struct ath_common *common = ath5k_hw_common(ah);
1376
1377        ath5k_remove_padding(skb);
1378
1379        rxs = IEEE80211_SKB_RXCB(skb);
1380
1381        rxs->flag = 0;
1382        if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1383                rxs->flag |= RX_FLAG_MMIC_ERROR;
1384        if (unlikely(rs->rs_status & AR5K_RXERR_CRC))
1385                rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
1386
1387
1388        /*
1389         * always extend the mac timestamp, since this information is
1390         * also needed for proper IBSS merging.
1391         *
1392         * XXX: it might be too late to do it here, since rs_tstamp is
1393         * 15bit only. that means TSF extension has to be done within
1394         * 32768usec (about 32ms). it might be necessary to move this to
1395         * the interrupt handler, like it is done in madwifi.
1396         */
1397        rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1398        rxs->flag |= RX_FLAG_MACTIME_END;
1399
1400        rxs->freq = ah->curchan->center_freq;
1401        rxs->band = ah->curchan->band;
1402
1403        rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1404
1405        rxs->antenna = rs->rs_antenna;
1406
1407        if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1408                ah->stats.antenna_rx[rs->rs_antenna]++;
1409        else
1410                ah->stats.antenna_rx[0]++; /* invalid */
1411
1412        rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1413        rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1414        switch (ah->ah_bwmode) {
1415        case AR5K_BWMODE_5MHZ:
1416                rxs->bw = RATE_INFO_BW_5;
1417                break;
1418        case AR5K_BWMODE_10MHZ:
1419                rxs->bw = RATE_INFO_BW_10;
1420                break;
1421        default:
1422                break;
1423        }
1424
1425        if (rs->rs_rate ==
1426            ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1427                rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE;
1428
1429        trace_ath5k_rx(ah, skb);
1430
1431        if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) {
1432                ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi);
1433
1434                /* check beacons in IBSS mode */
1435                if (ah->opmode == NL80211_IFTYPE_ADHOC)
1436                        ath5k_check_ibss_tsf(ah, skb, rxs);
1437        }
1438
1439        ieee80211_rx(ah->hw, skb);
1440}
1441
1442/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1443 *
1444 * Check if we want to further process this frame or not. Also update
1445 * statistics. Return true if we want this frame, false if not.
1446 */
1447static bool
1448ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1449{
1450        ah->stats.rx_all_count++;
1451        ah->stats.rx_bytes_count += rs->rs_datalen;
1452
1453        if (unlikely(rs->rs_status)) {
1454                unsigned int filters;
1455
1456                if (rs->rs_status & AR5K_RXERR_CRC)
1457                        ah->stats.rxerr_crc++;
1458                if (rs->rs_status & AR5K_RXERR_FIFO)
1459                        ah->stats.rxerr_fifo++;
1460                if (rs->rs_status & AR5K_RXERR_PHY) {
1461                        ah->stats.rxerr_phy++;
1462                        if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1463                                ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1464
1465                        /*
1466                         * Treat packets that underwent a CCK or OFDM reset as having a bad CRC.
1467                         * These restarts happen when the radio resynchronizes to a stronger frame
1468                         * while receiving a weaker frame. Here we receive the prefix of the weak
1469                         * frame. Since these are incomplete packets, mark their CRC as invalid.
1470                         */
1471                        if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART ||
1472                            rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) {
1473                                rs->rs_status |= AR5K_RXERR_CRC;
1474                                rs->rs_status &= ~AR5K_RXERR_PHY;
1475                        } else {
1476                                return false;
1477                        }
1478                }
1479                if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1480                        /*
1481                         * Decrypt error.  If the error occurred
1482                         * because there was no hardware key, then
1483                         * let the frame through so the upper layers
1484                         * can process it.  This is necessary for 5210
1485                         * parts which have no way to setup a ``clear''
1486                         * key cache entry.
1487                         *
1488                         * XXX do key cache faulting
1489                         */
1490                        ah->stats.rxerr_decrypt++;
1491                        if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1492                            !(rs->rs_status & AR5K_RXERR_CRC))
1493                                return true;
1494                }
1495                if (rs->rs_status & AR5K_RXERR_MIC) {
1496                        ah->stats.rxerr_mic++;
1497                        return true;
1498                }
1499
1500                /*
1501                 * Reject any frames with non-crypto errors, and take into account the
1502                 * current FIF_* filters.
1503                 */
1504                filters = AR5K_RXERR_DECRYPT;
1505                if (ah->fif_filter_flags & FIF_FCSFAIL)
1506                        filters |= AR5K_RXERR_CRC;
1507
1508                if (rs->rs_status & ~filters)
1509                        return false;
1510        }
1511
1512        if (unlikely(rs->rs_more)) {
1513                ah->stats.rxerr_jumbo++;
1514                return false;
1515        }
1516        return true;
1517}
1518
1519static void
1520ath5k_set_current_imask(struct ath5k_hw *ah)
1521{
1522        enum ath5k_int imask;
1523        unsigned long flags;
1524
1525        if (test_bit(ATH_STAT_RESET, ah->status))
1526                return;
1527
1528        spin_lock_irqsave(&ah->irqlock, flags);
1529        imask = ah->imask;
1530        if (ah->rx_pending)
1531                imask &= ~AR5K_INT_RX_ALL;
1532        if (ah->tx_pending)
1533                imask &= ~AR5K_INT_TX_ALL;
1534        ath5k_hw_set_imr(ah, imask);
1535        spin_unlock_irqrestore(&ah->irqlock, flags);
1536}
1537
1538static void
1539ath5k_tasklet_rx(struct tasklet_struct *t)
1540{
1541        struct ath5k_rx_status rs = {};
1542        struct sk_buff *skb, *next_skb;
1543        dma_addr_t next_skb_addr;
1544        struct ath5k_hw *ah = from_tasklet(ah, t, rxtq);
1545        struct ath_common *common = ath5k_hw_common(ah);
1546        struct ath5k_buf *bf;
1547        struct ath5k_desc *ds;
1548        int ret;
1549
1550        spin_lock(&ah->rxbuflock);
1551        if (list_empty(&ah->rxbuf)) {
1552                ATH5K_WARN(ah, "empty rx buf pool\n");
1553                goto unlock;
1554        }
1555        do {
1556                bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1557                BUG_ON(bf->skb == NULL);
1558                skb = bf->skb;
1559                ds = bf->desc;
1560
1561                /* bail if HW is still using self-linked descriptor */
1562                if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1563                        break;
1564
1565                ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1566                if (unlikely(ret == -EINPROGRESS))
1567                        break;
1568                else if (unlikely(ret)) {
1569                        ATH5K_ERR(ah, "error in processing rx descriptor\n");
1570                        ah->stats.rxerr_proc++;
1571                        break;
1572                }
1573
1574                if (ath5k_receive_frame_ok(ah, &rs)) {
1575                        next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1576
1577                        /*
1578                         * If we can't replace bf->skb with a new skb under
1579                         * memory pressure, just skip this packet
1580                         */
1581                        if (!next_skb)
1582                                goto next;
1583
1584                        dma_unmap_single(ah->dev, bf->skbaddr,
1585                                         common->rx_bufsize,
1586                                         DMA_FROM_DEVICE);
1587
1588                        skb_put(skb, rs.rs_datalen);
1589
1590                        ath5k_receive_frame(ah, skb, &rs);
1591
1592                        bf->skb = next_skb;
1593                        bf->skbaddr = next_skb_addr;
1594                }
1595next:
1596                list_move_tail(&bf->list, &ah->rxbuf);
1597        } while (ath5k_rxbuf_setup(ah, bf) == 0);
1598unlock:
1599        spin_unlock(&ah->rxbuflock);
1600        ah->rx_pending = false;
1601        ath5k_set_current_imask(ah);
1602}
1603
1604
1605/*************\
1606* TX Handling *
1607\*************/
1608
1609void
1610ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1611               struct ath5k_txq *txq, struct ieee80211_tx_control *control)
1612{
1613        struct ath5k_hw *ah = hw->priv;
1614        struct ath5k_buf *bf;
1615        unsigned long flags;
1616        int padsize;
1617
1618        trace_ath5k_tx(ah, skb, txq);
1619
1620        /*
1621         * The hardware expects the header padded to 4 byte boundaries.
1622         * If this is not the case, we add the padding after the header.
1623         */
1624        padsize = ath5k_add_padding(skb);
1625        if (padsize < 0) {
1626                ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1627                          " headroom to pad");
1628                goto drop_packet;
1629        }
1630
1631        if (txq->txq_len >= txq->txq_max &&
1632            txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1633                ieee80211_stop_queue(hw, txq->qnum);
1634
1635        spin_lock_irqsave(&ah->txbuflock, flags);
1636        if (list_empty(&ah->txbuf)) {
1637                ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1638                spin_unlock_irqrestore(&ah->txbuflock, flags);
1639                ieee80211_stop_queues(hw);
1640                goto drop_packet;
1641        }
1642        bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1643        list_del(&bf->list);
1644        ah->txbuf_len--;
1645        if (list_empty(&ah->txbuf))
1646                ieee80211_stop_queues(hw);
1647        spin_unlock_irqrestore(&ah->txbuflock, flags);
1648
1649        bf->skb = skb;
1650
1651        if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) {
1652                bf->skb = NULL;
1653                spin_lock_irqsave(&ah->txbuflock, flags);
1654                list_add_tail(&bf->list, &ah->txbuf);
1655                ah->txbuf_len++;
1656                spin_unlock_irqrestore(&ah->txbuflock, flags);
1657                goto drop_packet;
1658        }
1659        return;
1660
1661drop_packet:
1662        ieee80211_free_txskb(hw, skb);
1663}
1664
1665static void
1666ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1667                         struct ath5k_txq *txq, struct ath5k_tx_status *ts,
1668                         struct ath5k_buf *bf)
1669{
1670        struct ieee80211_tx_info *info;
1671        u8 tries[3];
1672        int i;
1673        int size = 0;
1674
1675        ah->stats.tx_all_count++;
1676        ah->stats.tx_bytes_count += skb->len;
1677        info = IEEE80211_SKB_CB(skb);
1678
1679        size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates));
1680        memcpy(info->status.rates, bf->rates, size);
1681
1682        tries[0] = info->status.rates[0].count;
1683        tries[1] = info->status.rates[1].count;
1684        tries[2] = info->status.rates[2].count;
1685
1686        ieee80211_tx_info_clear_status(info);
1687
1688        for (i = 0; i < ts->ts_final_idx; i++) {
1689                struct ieee80211_tx_rate *r =
1690                        &info->status.rates[i];
1691
1692                r->count = tries[i];
1693        }
1694
1695        info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
1696        info->status.rates[ts->ts_final_idx + 1].idx = -1;
1697
1698        if (unlikely(ts->ts_status)) {
1699                ah->stats.ack_fail++;
1700                if (ts->ts_status & AR5K_TXERR_FILT) {
1701                        info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1702                        ah->stats.txerr_filt++;
1703                }
1704                if (ts->ts_status & AR5K_TXERR_XRETRY)
1705                        ah->stats.txerr_retry++;
1706                if (ts->ts_status & AR5K_TXERR_FIFO)
1707                        ah->stats.txerr_fifo++;
1708        } else {
1709                info->flags |= IEEE80211_TX_STAT_ACK;
1710                info->status.ack_signal = ts->ts_rssi;
1711
1712                /* count the successful attempt as well */
1713                info->status.rates[ts->ts_final_idx].count++;
1714        }
1715
1716        /*
1717        * Remove MAC header padding before giving the frame
1718        * back to mac80211.
1719        */
1720        ath5k_remove_padding(skb);
1721
1722        if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1723                ah->stats.antenna_tx[ts->ts_antenna]++;
1724        else
1725                ah->stats.antenna_tx[0]++; /* invalid */
1726
1727        trace_ath5k_tx_complete(ah, skb, txq, ts);
1728        ieee80211_tx_status(ah->hw, skb);
1729}
1730
1731static void
1732ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1733{
1734        struct ath5k_tx_status ts = {};
1735        struct ath5k_buf *bf, *bf0;
1736        struct ath5k_desc *ds;
1737        struct sk_buff *skb;
1738        int ret;
1739
1740        spin_lock(&txq->lock);
1741        list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1742
1743                txq->txq_poll_mark = false;
1744
1745                /* skb might already have been processed last time. */
1746                if (bf->skb != NULL) {
1747                        ds = bf->desc;
1748
1749                        ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1750                        if (unlikely(ret == -EINPROGRESS))
1751                                break;
1752                        else if (unlikely(ret)) {
1753                                ATH5K_ERR(ah,
1754                                        "error %d while processing "
1755                                        "queue %u\n", ret, txq->qnum);
1756                                break;
1757                        }
1758
1759                        skb = bf->skb;
1760                        bf->skb = NULL;
1761
1762                        dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1763                                        DMA_TO_DEVICE);
1764                        ath5k_tx_frame_completed(ah, skb, txq, &ts, bf);
1765                }
1766
1767                /*
1768                 * It's possible that the hardware can say the buffer is
1769                 * completed when it hasn't yet loaded the ds_link from
1770                 * host memory and moved on.
1771                 * Always keep the last descriptor to avoid HW races...
1772                 */
1773                if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1774                        spin_lock(&ah->txbuflock);
1775                        list_move_tail(&bf->list, &ah->txbuf);
1776                        ah->txbuf_len++;
1777                        txq->txq_len--;
1778                        spin_unlock(&ah->txbuflock);
1779                }
1780        }
1781        spin_unlock(&txq->lock);
1782        if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1783                ieee80211_wake_queue(ah->hw, txq->qnum);
1784}
1785
1786static void
1787ath5k_tasklet_tx(struct tasklet_struct *t)
1788{
1789        int i;
1790        struct ath5k_hw *ah = from_tasklet(ah, t, txtq);
1791
1792        for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1793                if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
1794                        ath5k_tx_processq(ah, &ah->txqs[i]);
1795
1796        ah->tx_pending = false;
1797        ath5k_set_current_imask(ah);
1798}
1799
1800
1801/*****************\
1802* Beacon handling *
1803\*****************/
1804
1805/*
1806 * Setup the beacon frame for transmit.
1807 */
1808static int
1809ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1810{
1811        struct sk_buff *skb = bf->skb;
1812        struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1813        struct ath5k_desc *ds;
1814        int ret = 0;
1815        u8 antenna;
1816        u32 flags;
1817        const int padsize = 0;
1818
1819        bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1820                        DMA_TO_DEVICE);
1821        ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1822                        "skbaddr %llx\n", skb, skb->data, skb->len,
1823                        (unsigned long long)bf->skbaddr);
1824
1825        if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1826                ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1827                dev_kfree_skb_any(skb);
1828                bf->skb = NULL;
1829                return -EIO;
1830        }
1831
1832        ds = bf->desc;
1833        antenna = ah->ah_tx_ant;
1834
1835        flags = AR5K_TXDESC_NOACK;
1836        if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1837                ds->ds_link = bf->daddr;        /* self-linked */
1838                flags |= AR5K_TXDESC_VEOL;
1839        } else
1840                ds->ds_link = 0;
1841
1842        /*
1843         * If we use multiple antennas on AP and use
1844         * the Sectored AP scenario, switch antenna every
1845         * 4 beacons to make sure everybody hears our AP.
1846         * When a client tries to associate, hw will keep
1847         * track of the tx antenna to be used for this client
1848         * automatically, based on ACKed packets.
1849         *
1850         * Note: AP still listens and transmits RTS on the
1851         * default antenna which is supposed to be an omni.
1852         *
1853         * Note2: On sectored scenarios it's possible to have
1854         * multiple antennas (1 omni -- the default -- and 14
1855         * sectors), so if we choose to actually support this
1856         * mode, we need to allow the user to set how many antennas
1857         * we have and tweak the code below to send beacons
1858         * on all of them.
1859         */
1860        if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1861                antenna = ah->bsent & 4 ? 2 : 1;
1862
1863
1864        /* FIXME: If we are in g mode and rate is a CCK rate
1865         * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1866         * from tx power (value is in dB units already) */
1867        ds->ds_data = bf->skbaddr;
1868        ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1869                        ieee80211_get_hdrlen_from_skb(skb), padsize,
1870                        AR5K_PKT_TYPE_BEACON,
1871                        (ah->ah_txpower.txp_requested * 2),
1872                        ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1873                        1, AR5K_TXKEYIX_INVALID,
1874                        antenna, flags, 0, 0);
1875        if (ret)
1876                goto err_unmap;
1877
1878        return 0;
1879err_unmap:
1880        dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1881        return ret;
1882}
1883
1884/*
1885 * Updates the beacon that is sent by ath5k_beacon_send.  For adhoc,
1886 * this is called only once at config_bss time, for AP we do it every
1887 * SWBA interrupt so that the TIM will reflect buffered frames.
1888 *
1889 * Called with the beacon lock.
1890 */
1891int
1892ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1893{
1894        int ret;
1895        struct ath5k_hw *ah = hw->priv;
1896        struct ath5k_vif *avf;
1897        struct sk_buff *skb;
1898
1899        if (WARN_ON(!vif)) {
1900                ret = -EINVAL;
1901                goto out;
1902        }
1903
1904        skb = ieee80211_beacon_get(hw, vif);
1905
1906        if (!skb) {
1907                ret = -ENOMEM;
1908                goto out;
1909        }
1910
1911        avf = (void *)vif->drv_priv;
1912        ath5k_txbuf_free_skb(ah, avf->bbuf);
1913        avf->bbuf->skb = skb;
1914        ret = ath5k_beacon_setup(ah, avf->bbuf);
1915out:
1916        return ret;
1917}
1918
1919/*
1920 * Transmit a beacon frame at SWBA.  Dynamic updates to the
1921 * frame contents are done as needed and the slot time is
1922 * also adjusted based on current state.
1923 *
1924 * This is called from software irq context (beacontq tasklets)
1925 * or user context from ath5k_beacon_config.
1926 */
1927static void
1928ath5k_beacon_send(struct ath5k_hw *ah)
1929{
1930        struct ieee80211_vif *vif;
1931        struct ath5k_vif *avf;
1932        struct ath5k_buf *bf;
1933        struct sk_buff *skb;
1934        int err;
1935
1936        ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1937
1938        /*
1939         * Check if the previous beacon has gone out.  If
1940         * not, don't don't try to post another: skip this
1941         * period and wait for the next.  Missed beacons
1942         * indicate a problem and should not occur.  If we
1943         * miss too many consecutive beacons reset the device.
1944         */
1945        if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1946                ah->bmisscount++;
1947                ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1948                        "missed %u consecutive beacons\n", ah->bmisscount);
1949                if (ah->bmisscount > 10) {      /* NB: 10 is a guess */
1950                        ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1951                                "stuck beacon time (%u missed)\n",
1952                                ah->bmisscount);
1953                        ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1954                                  "stuck beacon, resetting\n");
1955                        ieee80211_queue_work(ah->hw, &ah->reset_work);
1956                }
1957                return;
1958        }
1959        if (unlikely(ah->bmisscount != 0)) {
1960                ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1961                        "resume beacon xmit after %u misses\n",
1962                        ah->bmisscount);
1963                ah->bmisscount = 0;
1964        }
1965
1966        if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1967                        ah->num_mesh_vifs > 1) ||
1968                        ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1969                u64 tsf = ath5k_hw_get_tsf64(ah);
1970                u32 tsftu = TSF_TO_TU(tsf);
1971                int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1972                vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1973                ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1974                        "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1975                        (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1976        } else /* only one interface */
1977                vif = ah->bslot[0];
1978
1979        if (!vif)
1980                return;
1981
1982        avf = (void *)vif->drv_priv;
1983        bf = avf->bbuf;
1984
1985        /*
1986         * Stop any current dma and put the new frame on the queue.
1987         * This should never fail since we check above that no frames
1988         * are still pending on the queue.
1989         */
1990        if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1991                ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1992                /* NB: hw still stops DMA, so proceed */
1993        }
1994
1995        /* refresh the beacon for AP or MESH mode */
1996        if (ah->opmode == NL80211_IFTYPE_AP ||
1997            ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1998                err = ath5k_beacon_update(ah->hw, vif);
1999                if (err)
2000                        return;
2001        }
2002
2003        if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
2004                     ah->opmode == NL80211_IFTYPE_MONITOR)) {
2005                ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
2006                return;
2007        }
2008
2009        trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
2010
2011        ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
2012        ath5k_hw_start_tx_dma(ah, ah->bhalq);
2013        ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2014                ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
2015
2016        skb = ieee80211_get_buffered_bc(ah->hw, vif);
2017        while (skb) {
2018                ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL);
2019
2020                if (ah->cabq->txq_len >= ah->cabq->txq_max)
2021                        break;
2022
2023                skb = ieee80211_get_buffered_bc(ah->hw, vif);
2024        }
2025
2026        ah->bsent++;
2027}
2028
2029/**
2030 * ath5k_beacon_update_timers - update beacon timers
2031 *
2032 * @ah: struct ath5k_hw pointer we are operating on
2033 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2034 *          beacon timer update based on the current HW TSF.
2035 *
2036 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2037 * of a received beacon or the current local hardware TSF and write it to the
2038 * beacon timer registers.
2039 *
2040 * This is called in a variety of situations, e.g. when a beacon is received,
2041 * when a TSF update has been detected, but also when an new IBSS is created or
2042 * when we otherwise know we have to update the timers, but we keep it in this
2043 * function to have it all together in one place.
2044 */
2045void
2046ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
2047{
2048        u32 nexttbtt, intval, hw_tu, bc_tu;
2049        u64 hw_tsf;
2050
2051        intval = ah->bintval & AR5K_BEACON_PERIOD;
2052        if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
2053                + ah->num_mesh_vifs > 1) {
2054                intval /= ATH_BCBUF;    /* staggered multi-bss beacons */
2055                if (intval < 15)
2056                        ATH5K_WARN(ah, "intval %u is too low, min 15\n",
2057                                   intval);
2058        }
2059        if (WARN_ON(!intval))
2060                return;
2061
2062        /* beacon TSF converted to TU */
2063        bc_tu = TSF_TO_TU(bc_tsf);
2064
2065        /* current TSF converted to TU */
2066        hw_tsf = ath5k_hw_get_tsf64(ah);
2067        hw_tu = TSF_TO_TU(hw_tsf);
2068
2069#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
2070        /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
2071         * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
2072         * configuration we need to make sure it is bigger than that. */
2073
2074        if (bc_tsf == -1) {
2075                /*
2076                 * no beacons received, called internally.
2077                 * just need to refresh timers based on HW TSF.
2078                 */
2079                nexttbtt = roundup(hw_tu + FUDGE, intval);
2080        } else if (bc_tsf == 0) {
2081                /*
2082                 * no beacon received, probably called by ath5k_reset_tsf().
2083                 * reset TSF to start with 0.
2084                 */
2085                nexttbtt = intval;
2086                intval |= AR5K_BEACON_RESET_TSF;
2087        } else if (bc_tsf > hw_tsf) {
2088                /*
2089                 * beacon received, SW merge happened but HW TSF not yet updated.
2090                 * not possible to reconfigure timers yet, but next time we
2091                 * receive a beacon with the same BSSID, the hardware will
2092                 * automatically update the TSF and then we need to reconfigure
2093                 * the timers.
2094                 */
2095                ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2096                        "need to wait for HW TSF sync\n");
2097                return;
2098        } else {
2099                /*
2100                 * most important case for beacon synchronization between STA.
2101                 *
2102                 * beacon received and HW TSF has been already updated by HW.
2103                 * update next TBTT based on the TSF of the beacon, but make
2104                 * sure it is ahead of our local TSF timer.
2105                 */
2106                nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2107        }
2108#undef FUDGE
2109
2110        ah->nexttbtt = nexttbtt;
2111
2112        intval |= AR5K_BEACON_ENA;
2113        ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
2114
2115        /*
2116         * debugging output last in order to preserve the time critical aspect
2117         * of this function
2118         */
2119        if (bc_tsf == -1)
2120                ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2121                        "reconfigured timers based on HW TSF\n");
2122        else if (bc_tsf == 0)
2123                ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2124                        "reset HW TSF and timers\n");
2125        else
2126                ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2127                        "updated timers based on beacon TSF\n");
2128
2129        ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2130                          "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2131                          (unsigned long long) bc_tsf,
2132                          (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2133        ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2134                intval & AR5K_BEACON_PERIOD,
2135                intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2136                intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2137}
2138
2139/**
2140 * ath5k_beacon_config - Configure the beacon queues and interrupts
2141 *
2142 * @ah: struct ath5k_hw pointer we are operating on
2143 *
2144 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2145 * interrupts to detect TSF updates only.
2146 */
2147void
2148ath5k_beacon_config(struct ath5k_hw *ah)
2149{
2150        spin_lock_bh(&ah->block);
2151        ah->bmisscount = 0;
2152        ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2153
2154        if (ah->enable_beacon) {
2155                /*
2156                 * In IBSS mode we use a self-linked tx descriptor and let the
2157                 * hardware send the beacons automatically. We have to load it
2158                 * only once here.
2159                 * We use the SWBA interrupt only to keep track of the beacon
2160                 * timers in order to detect automatic TSF updates.
2161                 */
2162                ath5k_beaconq_config(ah);
2163
2164                ah->imask |= AR5K_INT_SWBA;
2165
2166                if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2167                        if (ath5k_hw_hasveol(ah))
2168                                ath5k_beacon_send(ah);
2169                } else
2170                        ath5k_beacon_update_timers(ah, -1);
2171        } else {
2172                ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2173        }
2174
2175        ath5k_hw_set_imr(ah, ah->imask);
2176        spin_unlock_bh(&ah->block);
2177}
2178
2179static void ath5k_tasklet_beacon(struct tasklet_struct *t)
2180{
2181        struct ath5k_hw *ah = from_tasklet(ah, t, beacontq);
2182
2183        /*
2184         * Software beacon alert--time to send a beacon.
2185         *
2186         * In IBSS mode we use this interrupt just to
2187         * keep track of the next TBTT (target beacon
2188         * transmission time) in order to detect whether
2189         * automatic TSF updates happened.
2190         */
2191        if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2192                /* XXX: only if VEOL supported */
2193                u64 tsf = ath5k_hw_get_tsf64(ah);
2194                ah->nexttbtt += ah->bintval;
2195                ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2196                                "SWBA nexttbtt: %x hw_tu: %x "
2197                                "TSF: %llx\n",
2198                                ah->nexttbtt,
2199                                TSF_TO_TU(tsf),
2200                                (unsigned long long) tsf);
2201        } else {
2202                spin_lock(&ah->block);
2203                ath5k_beacon_send(ah);
2204                spin_unlock(&ah->block);
2205        }
2206}
2207
2208
2209/********************\
2210* Interrupt handling *
2211\********************/
2212
2213static void
2214ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2215{
2216        if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2217           !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2218           !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2219
2220                /* Run ANI only when calibration is not active */
2221
2222                ah->ah_cal_next_ani = jiffies +
2223                        msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2224                tasklet_schedule(&ah->ani_tasklet);
2225
2226        } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2227                !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2228                !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2229
2230                /* Run calibration only when another calibration
2231                 * is not running.
2232                 *
2233                 * Note: This is for both full/short calibration,
2234                 * if it's time for a full one, ath5k_calibrate_work will deal
2235                 * with it. */
2236
2237                ah->ah_cal_next_short = jiffies +
2238                        msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2239                ieee80211_queue_work(ah->hw, &ah->calib_work);
2240        }
2241        /* we could use SWI to generate enough interrupts to meet our
2242         * calibration interval requirements, if necessary:
2243         * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2244}
2245
2246static void
2247ath5k_schedule_rx(struct ath5k_hw *ah)
2248{
2249        ah->rx_pending = true;
2250        tasklet_schedule(&ah->rxtq);
2251}
2252
2253static void
2254ath5k_schedule_tx(struct ath5k_hw *ah)
2255{
2256        ah->tx_pending = true;
2257        tasklet_schedule(&ah->txtq);
2258}
2259
2260static irqreturn_t
2261ath5k_intr(int irq, void *dev_id)
2262{
2263        struct ath5k_hw *ah = dev_id;
2264        enum ath5k_int status;
2265        unsigned int counter = 1000;
2266
2267
2268        /*
2269         * If hw is not ready (or detached) and we get an
2270         * interrupt, or if we have no interrupts pending
2271         * (that means it's not for us) skip it.
2272         *
2273         * NOTE: Group 0/1 PCI interface registers are not
2274         * supported on WiSOCs, so we can't check for pending
2275         * interrupts (ISR belongs to another register group
2276         * so we are ok).
2277         */
2278        if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2279                        ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2280                        !ath5k_hw_is_intr_pending(ah))))
2281                return IRQ_NONE;
2282
2283        /** Main loop **/
2284        do {
2285                ath5k_hw_get_isr(ah, &status);  /* NB: clears IRQ too */
2286
2287                ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2288                                status, ah->imask);
2289
2290                /*
2291                 * Fatal hw error -> Log and reset
2292                 *
2293                 * Fatal errors are unrecoverable so we have to
2294                 * reset the card. These errors include bus and
2295                 * dma errors.
2296                 */
2297                if (unlikely(status & AR5K_INT_FATAL)) {
2298
2299                        ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2300                                  "fatal int, resetting\n");
2301                        ieee80211_queue_work(ah->hw, &ah->reset_work);
2302
2303                /*
2304                 * RX Overrun -> Count and reset if needed
2305                 *
2306                 * Receive buffers are full. Either the bus is busy or
2307                 * the CPU is not fast enough to process all received
2308                 * frames.
2309                 */
2310                } else if (unlikely(status & AR5K_INT_RXORN)) {
2311
2312                        /*
2313                         * Older chipsets need a reset to come out of this
2314                         * condition, but we treat it as RX for newer chips.
2315                         * We don't know exactly which versions need a reset
2316                         * this guess is copied from the HAL.
2317                         */
2318                        ah->stats.rxorn_intr++;
2319
2320                        if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2321                                ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2322                                          "rx overrun, resetting\n");
2323                                ieee80211_queue_work(ah->hw, &ah->reset_work);
2324                        } else
2325                                ath5k_schedule_rx(ah);
2326
2327                } else {
2328
2329                        /* Software Beacon Alert -> Schedule beacon tasklet */
2330                        if (status & AR5K_INT_SWBA)
2331                                tasklet_hi_schedule(&ah->beacontq);
2332
2333                        /*
2334                         * No more RX descriptors -> Just count
2335                         *
2336                         * NB: the hardware should re-read the link when
2337                         *     RXE bit is written, but it doesn't work at
2338                         *     least on older hardware revs.
2339                         */
2340                        if (status & AR5K_INT_RXEOL)
2341                                ah->stats.rxeol_intr++;
2342
2343
2344                        /* TX Underrun -> Bump tx trigger level */
2345                        if (status & AR5K_INT_TXURN)
2346                                ath5k_hw_update_tx_triglevel(ah, true);
2347
2348                        /* RX -> Schedule rx tasklet */
2349                        if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2350                                ath5k_schedule_rx(ah);
2351
2352                        /* TX -> Schedule tx tasklet */
2353                        if (status & (AR5K_INT_TXOK
2354                                        | AR5K_INT_TXDESC
2355                                        | AR5K_INT_TXERR
2356                                        | AR5K_INT_TXEOL))
2357                                ath5k_schedule_tx(ah);
2358
2359                        /* Missed beacon -> TODO
2360                        if (status & AR5K_INT_BMISS)
2361                        */
2362
2363                        /* MIB event -> Update counters and notify ANI */
2364                        if (status & AR5K_INT_MIB) {
2365                                ah->stats.mib_intr++;
2366                                ath5k_hw_update_mib_counters(ah);
2367                                ath5k_ani_mib_intr(ah);
2368                        }
2369
2370                        /* GPIO -> Notify RFKill layer */
2371                        if (status & AR5K_INT_GPIO)
2372                                tasklet_schedule(&ah->rf_kill.toggleq);
2373
2374                }
2375
2376                if (ath5k_get_bus_type(ah) == ATH_AHB)
2377                        break;
2378
2379        } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2380
2381        /*
2382         * Until we handle rx/tx interrupts mask them on IMR
2383         *
2384         * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2385         * and unset after we 've handled the interrupts.
2386         */
2387        if (ah->rx_pending || ah->tx_pending)
2388                ath5k_set_current_imask(ah);
2389
2390        if (unlikely(!counter))
2391                ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2392
2393        /* Fire up calibration poll */
2394        ath5k_intr_calibration_poll(ah);
2395
2396        return IRQ_HANDLED;
2397}
2398
2399/*
2400 * Periodically recalibrate the PHY to account
2401 * for temperature/environment changes.
2402 */
2403static void
2404ath5k_calibrate_work(struct work_struct *work)
2405{
2406        struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2407                calib_work);
2408
2409        /* Should we run a full calibration ? */
2410        if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2411
2412                ah->ah_cal_next_full = jiffies +
2413                        msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2414                ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2415
2416                ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2417                                "running full calibration\n");
2418
2419                if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2420                        /*
2421                         * Rfgain is out of bounds, reset the chip
2422                         * to load new gain values.
2423                         */
2424                        ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2425                                        "got new rfgain, resetting\n");
2426                        ieee80211_queue_work(ah->hw, &ah->reset_work);
2427                }
2428        } else
2429                ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2430
2431
2432        ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2433                ieee80211_frequency_to_channel(ah->curchan->center_freq),
2434                ah->curchan->hw_value);
2435
2436        if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2437                ATH5K_ERR(ah, "calibration of channel %u failed\n",
2438                        ieee80211_frequency_to_channel(
2439                                ah->curchan->center_freq));
2440
2441        /* Clear calibration flags */
2442        if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
2443                ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2444        else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
2445                ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
2446}
2447
2448
2449static void
2450ath5k_tasklet_ani(struct tasklet_struct *t)
2451{
2452        struct ath5k_hw *ah = from_tasklet(ah, t, ani_tasklet);
2453
2454        ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2455        ath5k_ani_calibration(ah);
2456        ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2457}
2458
2459
2460static void
2461ath5k_tx_complete_poll_work(struct work_struct *work)
2462{
2463        struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2464                        tx_complete_work.work);
2465        struct ath5k_txq *txq;
2466        int i;
2467        bool needreset = false;
2468
2469        if (!test_bit(ATH_STAT_STARTED, ah->status))
2470                return;
2471
2472        mutex_lock(&ah->lock);
2473
2474        for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2475                if (ah->txqs[i].setup) {
2476                        txq = &ah->txqs[i];
2477                        spin_lock_bh(&txq->lock);
2478                        if (txq->txq_len > 1) {
2479                                if (txq->txq_poll_mark) {
2480                                        ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2481                                                  "TX queue stuck %d\n",
2482                                                  txq->qnum);
2483                                        needreset = true;
2484                                        txq->txq_stuck++;
2485                                        spin_unlock_bh(&txq->lock);
2486                                        break;
2487                                } else {
2488                                        txq->txq_poll_mark = true;
2489                                }
2490                        }
2491                        spin_unlock_bh(&txq->lock);
2492                }
2493        }
2494
2495        if (needreset) {
2496                ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2497                          "TX queues stuck, resetting\n");
2498                ath5k_reset(ah, NULL, true);
2499        }
2500
2501        mutex_unlock(&ah->lock);
2502
2503        ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2504                msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2505}
2506
2507
2508/*************************\
2509* Initialization routines *
2510\*************************/
2511
2512static const struct ieee80211_iface_limit if_limits[] = {
2513        { .max = 2048,  .types = BIT(NL80211_IFTYPE_STATION) },
2514        { .max = 4,     .types =
2515#ifdef CONFIG_MAC80211_MESH
2516                                 BIT(NL80211_IFTYPE_MESH_POINT) |
2517#endif
2518                                 BIT(NL80211_IFTYPE_AP) },
2519};
2520
2521static const struct ieee80211_iface_combination if_comb = {
2522        .limits = if_limits,
2523        .n_limits = ARRAY_SIZE(if_limits),
2524        .max_interfaces = 2048,
2525        .num_different_channels = 1,
2526};
2527
2528int
2529ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2530{
2531        struct ieee80211_hw *hw = ah->hw;
2532        struct ath_common *common;
2533        int ret;
2534        int csz;
2535
2536        /* Initialize driver private data */
2537        SET_IEEE80211_DEV(hw, ah->dev);
2538        ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
2539        ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
2540        ieee80211_hw_set(hw, MFP_CAPABLE);
2541        ieee80211_hw_set(hw, SIGNAL_DBM);
2542        ieee80211_hw_set(hw, RX_INCLUDES_FCS);
2543        ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
2544
2545        hw->wiphy->interface_modes =
2546                BIT(NL80211_IFTYPE_AP) |
2547                BIT(NL80211_IFTYPE_STATION) |
2548                BIT(NL80211_IFTYPE_ADHOC) |
2549                BIT(NL80211_IFTYPE_MESH_POINT);
2550
2551        hw->wiphy->iface_combinations = &if_comb;
2552        hw->wiphy->n_iface_combinations = 1;
2553
2554        /* SW support for IBSS_RSN is provided by mac80211 */
2555        hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2556
2557        hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2558
2559        /* both antennas can be configured as RX or TX */
2560        hw->wiphy->available_antennas_tx = 0x3;
2561        hw->wiphy->available_antennas_rx = 0x3;
2562
2563        hw->extra_tx_headroom = 2;
2564
2565        wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
2566
2567        /*
2568         * Mark the device as detached to avoid processing
2569         * interrupts until setup is complete.
2570         */
2571        __set_bit(ATH_STAT_INVALID, ah->status);
2572
2573        ah->opmode = NL80211_IFTYPE_STATION;
2574        ah->bintval = 1000;
2575        mutex_init(&ah->lock);
2576        spin_lock_init(&ah->rxbuflock);
2577        spin_lock_init(&ah->txbuflock);
2578        spin_lock_init(&ah->block);
2579        spin_lock_init(&ah->irqlock);
2580
2581        /* Setup interrupt handler */
2582        ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2583        if (ret) {
2584                ATH5K_ERR(ah, "request_irq failed\n");
2585                goto err;
2586        }
2587
2588        common = ath5k_hw_common(ah);
2589        common->ops = &ath5k_common_ops;
2590        common->bus_ops = bus_ops;
2591        common->ah = ah;
2592        common->hw = hw;
2593        common->priv = ah;
2594        common->clockrate = 40;
2595
2596        /*
2597         * Cache line size is used to size and align various
2598         * structures used to communicate with the hardware.
2599         */
2600        ath5k_read_cachesize(common, &csz);
2601        common->cachelsz = csz << 2; /* convert to bytes */
2602
2603        spin_lock_init(&common->cc_lock);
2604
2605        /* Initialize device */
2606        ret = ath5k_hw_init(ah);
2607        if (ret)
2608                goto err_irq;
2609
2610        /* Set up multi-rate retry capabilities */
2611        if (ah->ah_capabilities.cap_has_mrr_support) {
2612                hw->max_rates = 4;
2613                hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2614                                         AR5K_INIT_RETRY_LONG);
2615        }
2616
2617        hw->vif_data_size = sizeof(struct ath5k_vif);
2618
2619        /* Finish private driver data initialization */
2620        ret = ath5k_init(hw);
2621        if (ret)
2622                goto err_ah;
2623
2624        ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2625                        ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2626                                        ah->ah_mac_srev,
2627                                        ah->ah_phy_revision);
2628
2629        if (!ah->ah_single_chip) {
2630                /* Single chip radio (!RF5111) */
2631                if (ah->ah_radio_5ghz_revision &&
2632                        !ah->ah_radio_2ghz_revision) {
2633                        /* No 5GHz support -> report 2GHz radio */
2634                        if (!test_bit(AR5K_MODE_11A,
2635                                ah->ah_capabilities.cap_mode)) {
2636                                ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2637                                        ath5k_chip_name(AR5K_VERSION_RAD,
2638                                                ah->ah_radio_5ghz_revision),
2639                                                ah->ah_radio_5ghz_revision);
2640                        /* No 2GHz support (5110 and some
2641                         * 5GHz only cards) -> report 5GHz radio */
2642                        } else if (!test_bit(AR5K_MODE_11B,
2643                                ah->ah_capabilities.cap_mode)) {
2644                                ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2645                                        ath5k_chip_name(AR5K_VERSION_RAD,
2646                                                ah->ah_radio_5ghz_revision),
2647                                                ah->ah_radio_5ghz_revision);
2648                        /* Multiband radio */
2649                        } else {
2650                                ATH5K_INFO(ah, "RF%s multiband radio found"
2651                                        " (0x%x)\n",
2652                                        ath5k_chip_name(AR5K_VERSION_RAD,
2653                                                ah->ah_radio_5ghz_revision),
2654                                                ah->ah_radio_5ghz_revision);
2655                        }
2656                }
2657                /* Multi chip radio (RF5111 - RF2111) ->
2658                 * report both 2GHz/5GHz radios */
2659                else if (ah->ah_radio_5ghz_revision &&
2660                                ah->ah_radio_2ghz_revision) {
2661                        ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2662                                ath5k_chip_name(AR5K_VERSION_RAD,
2663                                        ah->ah_radio_5ghz_revision),
2664                                        ah->ah_radio_5ghz_revision);
2665                        ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2666                                ath5k_chip_name(AR5K_VERSION_RAD,
2667                                        ah->ah_radio_2ghz_revision),
2668                                        ah->ah_radio_2ghz_revision);
2669                }
2670        }
2671
2672        ath5k_debug_init_device(ah);
2673
2674        /* ready to process interrupts */
2675        __clear_bit(ATH_STAT_INVALID, ah->status);
2676
2677        return 0;
2678err_ah:
2679        ath5k_hw_deinit(ah);
2680err_irq:
2681        free_irq(ah->irq, ah);
2682err:
2683        return ret;
2684}
2685
2686static int
2687ath5k_stop_locked(struct ath5k_hw *ah)
2688{
2689
2690        ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2691                        test_bit(ATH_STAT_INVALID, ah->status));
2692
2693        /*
2694         * Shutdown the hardware and driver:
2695         *    stop output from above
2696         *    disable interrupts
2697         *    turn off timers
2698         *    turn off the radio
2699         *    clear transmit machinery
2700         *    clear receive machinery
2701         *    drain and release tx queues
2702         *    reclaim beacon resources
2703         *    power down hardware
2704         *
2705         * Note that some of this work is not possible if the
2706         * hardware is gone (invalid).
2707         */
2708        ieee80211_stop_queues(ah->hw);
2709
2710        if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2711                ath5k_led_off(ah);
2712                ath5k_hw_set_imr(ah, 0);
2713                synchronize_irq(ah->irq);
2714                ath5k_rx_stop(ah);
2715                ath5k_hw_dma_stop(ah);
2716                ath5k_drain_tx_buffs(ah);
2717                ath5k_hw_phy_disable(ah);
2718        }
2719
2720        return 0;
2721}
2722
2723int ath5k_start(struct ieee80211_hw *hw)
2724{
2725        struct ath5k_hw *ah = hw->priv;
2726        struct ath_common *common = ath5k_hw_common(ah);
2727        int ret, i;
2728
2729        mutex_lock(&ah->lock);
2730
2731        ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2732
2733        /*
2734         * Stop anything previously setup.  This is safe
2735         * no matter this is the first time through or not.
2736         */
2737        ath5k_stop_locked(ah);
2738
2739        /*
2740         * The basic interface to setting the hardware in a good
2741         * state is ``reset''.  On return the hardware is known to
2742         * be powered up and with interrupts disabled.  This must
2743         * be followed by initialization of the appropriate bits
2744         * and then setup of the interrupt mask.
2745         */
2746        ah->curchan = ah->hw->conf.chandef.chan;
2747        ah->imask = AR5K_INT_RXOK
2748                | AR5K_INT_RXERR
2749                | AR5K_INT_RXEOL
2750                | AR5K_INT_RXORN
2751                | AR5K_INT_TXDESC
2752                | AR5K_INT_TXEOL
2753                | AR5K_INT_FATAL
2754                | AR5K_INT_GLOBAL
2755                | AR5K_INT_MIB;
2756
2757        ret = ath5k_reset(ah, NULL, false);
2758        if (ret)
2759                goto done;
2760
2761        if (!ath5k_modparam_no_hw_rfkill_switch)
2762                ath5k_rfkill_hw_start(ah);
2763
2764        /*
2765         * Reset the key cache since some parts do not reset the
2766         * contents on initial power up or resume from suspend.
2767         */
2768        for (i = 0; i < common->keymax; i++)
2769                ath_hw_keyreset(common, (u16) i);
2770
2771        /* Use higher rates for acks instead of base
2772         * rate */
2773        ah->ah_ack_bitrate_high = true;
2774
2775        for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2776                ah->bslot[i] = NULL;
2777
2778        ret = 0;
2779done:
2780        mutex_unlock(&ah->lock);
2781
2782        set_bit(ATH_STAT_STARTED, ah->status);
2783        ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2784                        msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2785
2786        return ret;
2787}
2788
2789static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2790{
2791        ah->rx_pending = false;
2792        ah->tx_pending = false;
2793        tasklet_kill(&ah->rxtq);
2794        tasklet_kill(&ah->txtq);
2795        tasklet_kill(&ah->beacontq);
2796        tasklet_kill(&ah->ani_tasklet);
2797}
2798
2799/*
2800 * Stop the device, grabbing the top-level lock to protect
2801 * against concurrent entry through ath5k_init (which can happen
2802 * if another thread does a system call and the thread doing the
2803 * stop is preempted).
2804 */
2805void ath5k_stop(struct ieee80211_hw *hw)
2806{
2807        struct ath5k_hw *ah = hw->priv;
2808        int ret;
2809
2810        mutex_lock(&ah->lock);
2811        ret = ath5k_stop_locked(ah);
2812        if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2813                /*
2814                 * Don't set the card in full sleep mode!
2815                 *
2816                 * a) When the device is in this state it must be carefully
2817                 * woken up or references to registers in the PCI clock
2818                 * domain may freeze the bus (and system).  This varies
2819                 * by chip and is mostly an issue with newer parts
2820                 * (madwifi sources mentioned srev >= 0x78) that go to
2821                 * sleep more quickly.
2822                 *
2823                 * b) On older chips full sleep results a weird behaviour
2824                 * during wakeup. I tested various cards with srev < 0x78
2825                 * and they don't wake up after module reload, a second
2826                 * module reload is needed to bring the card up again.
2827                 *
2828                 * Until we figure out what's going on don't enable
2829                 * full chip reset on any chip (this is what Legacy HAL
2830                 * and Sam's HAL do anyway). Instead Perform a full reset
2831                 * on the device (same as initial state after attach) and
2832                 * leave it idle (keep MAC/BB on warm reset) */
2833                ret = ath5k_hw_on_hold(ah);
2834
2835                ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2836                                "putting device to sleep\n");
2837        }
2838
2839        mutex_unlock(&ah->lock);
2840
2841        ath5k_stop_tasklets(ah);
2842
2843        clear_bit(ATH_STAT_STARTED, ah->status);
2844        cancel_delayed_work_sync(&ah->tx_complete_work);
2845
2846        if (!ath5k_modparam_no_hw_rfkill_switch)
2847                ath5k_rfkill_hw_stop(ah);
2848}
2849
2850/*
2851 * Reset the hardware.  If chan is not NULL, then also pause rx/tx
2852 * and change to the given channel.
2853 *
2854 * This should be called with ah->lock.
2855 */
2856static int
2857ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2858                                                        bool skip_pcu)
2859{
2860        struct ath_common *common = ath5k_hw_common(ah);
2861        int ret, ani_mode;
2862        bool fast = chan && modparam_fastchanswitch ? 1 : 0;
2863
2864        ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2865
2866        __set_bit(ATH_STAT_RESET, ah->status);
2867
2868        ath5k_hw_set_imr(ah, 0);
2869        synchronize_irq(ah->irq);
2870        ath5k_stop_tasklets(ah);
2871
2872        /* Save ani mode and disable ANI during
2873         * reset. If we don't we might get false
2874         * PHY error interrupts. */
2875        ani_mode = ah->ani_state.ani_mode;
2876        ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2877
2878        /* We are going to empty hw queues
2879         * so we should also free any remaining
2880         * tx buffers */
2881        ath5k_drain_tx_buffs(ah);
2882
2883        /* Stop PCU */
2884        ath5k_hw_stop_rx_pcu(ah);
2885
2886        /* Stop DMA
2887         *
2888         * Note: If DMA didn't stop continue
2889         * since only a reset will fix it.
2890         */
2891        ret = ath5k_hw_dma_stop(ah);
2892
2893        /* RF Bus grant won't work if we have pending
2894         * frames
2895         */
2896        if (ret && fast) {
2897                ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2898                          "DMA didn't stop, falling back to normal reset\n");
2899                fast = false;
2900        }
2901
2902        if (chan)
2903                ah->curchan = chan;
2904
2905        ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2906        if (ret) {
2907                ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2908                goto err;
2909        }
2910
2911        ret = ath5k_rx_start(ah);
2912        if (ret) {
2913                ATH5K_ERR(ah, "can't start recv logic\n");
2914                goto err;
2915        }
2916
2917        ath5k_ani_init(ah, ani_mode);
2918
2919        /*
2920         * Set calibration intervals
2921         *
2922         * Note: We don't need to run calibration imediately
2923         * since some initial calibration is done on reset
2924         * even for fast channel switching. Also on scanning
2925         * this will get set again and again and it won't get
2926         * executed unless we connect somewhere and spend some
2927         * time on the channel (that's what calibration needs
2928         * anyway to be accurate).
2929         */
2930        ah->ah_cal_next_full = jiffies +
2931                msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2932        ah->ah_cal_next_ani = jiffies +
2933                msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2934        ah->ah_cal_next_short = jiffies +
2935                msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2936
2937        ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg);
2938
2939        /* clear survey data and cycle counters */
2940        memset(&ah->survey, 0, sizeof(ah->survey));
2941        spin_lock_bh(&common->cc_lock);
2942        ath_hw_cycle_counters_update(common);
2943        memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2944        memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2945        spin_unlock_bh(&common->cc_lock);
2946
2947        /*
2948         * Change channels and update the h/w rate map if we're switching;
2949         * e.g. 11a to 11b/g.
2950         *
2951         * We may be doing a reset in response to an ioctl that changes the
2952         * channel so update any state that might change as a result.
2953         *
2954         * XXX needed?
2955         */
2956/*      ath5k_chan_change(ah, c); */
2957
2958        __clear_bit(ATH_STAT_RESET, ah->status);
2959
2960        ath5k_beacon_config(ah);
2961        /* intrs are enabled by ath5k_beacon_config */
2962
2963        ieee80211_wake_queues(ah->hw);
2964
2965        return 0;
2966err:
2967        return ret;
2968}
2969
2970static void ath5k_reset_work(struct work_struct *work)
2971{
2972        struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2973                reset_work);
2974
2975        mutex_lock(&ah->lock);
2976        ath5k_reset(ah, NULL, true);
2977        mutex_unlock(&ah->lock);
2978}
2979
2980static int
2981ath5k_init(struct ieee80211_hw *hw)
2982{
2983
2984        struct ath5k_hw *ah = hw->priv;
2985        struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2986        struct ath5k_txq *txq;
2987        u8 mac[ETH_ALEN] = {};
2988        int ret;
2989
2990
2991        /*
2992         * Collect the channel list.  The 802.11 layer
2993         * is responsible for filtering this list based
2994         * on settings like the phy mode and regulatory
2995         * domain restrictions.
2996         */
2997        ret = ath5k_setup_bands(hw);
2998        if (ret) {
2999                ATH5K_ERR(ah, "can't get channels\n");
3000                goto err;
3001        }
3002
3003        /*
3004         * Allocate tx+rx descriptors and populate the lists.
3005         */
3006        ret = ath5k_desc_alloc(ah);
3007        if (ret) {
3008                ATH5K_ERR(ah, "can't allocate descriptors\n");
3009                goto err;
3010        }
3011
3012        /*
3013         * Allocate hardware transmit queues: one queue for
3014         * beacon frames and one data queue for each QoS
3015         * priority.  Note that hw functions handle resetting
3016         * these queues at the needed time.
3017         */
3018        ret = ath5k_beaconq_setup(ah);
3019        if (ret < 0) {
3020                ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
3021                goto err_desc;
3022        }
3023        ah->bhalq = ret;
3024        ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
3025        if (IS_ERR(ah->cabq)) {
3026                ATH5K_ERR(ah, "can't setup cab queue\n");
3027                ret = PTR_ERR(ah->cabq);
3028                goto err_bhal;
3029        }
3030
3031        /* 5211 and 5212 usually support 10 queues but we better rely on the
3032         * capability information */
3033        if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
3034                /* This order matches mac80211's queue priority, so we can
3035                * directly use the mac80211 queue number without any mapping */
3036                txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
3037                if (IS_ERR(txq)) {
3038                        ATH5K_ERR(ah, "can't setup xmit queue\n");
3039                        ret = PTR_ERR(txq);
3040                        goto err_queues;
3041                }
3042                txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
3043                if (IS_ERR(txq)) {
3044                        ATH5K_ERR(ah, "can't setup xmit queue\n");
3045                        ret = PTR_ERR(txq);
3046                        goto err_queues;
3047                }
3048                txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3049                if (IS_ERR(txq)) {
3050                        ATH5K_ERR(ah, "can't setup xmit queue\n");
3051                        ret = PTR_ERR(txq);
3052                        goto err_queues;
3053                }
3054                txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
3055                if (IS_ERR(txq)) {
3056                        ATH5K_ERR(ah, "can't setup xmit queue\n");
3057                        ret = PTR_ERR(txq);
3058                        goto err_queues;
3059                }
3060                hw->queues = 4;
3061        } else {
3062                /* older hardware (5210) can only support one data queue */
3063                txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
3064                if (IS_ERR(txq)) {
3065                        ATH5K_ERR(ah, "can't setup xmit queue\n");
3066                        ret = PTR_ERR(txq);
3067                        goto err_queues;
3068                }
3069                hw->queues = 1;
3070        }
3071
3072        tasklet_setup(&ah->rxtq, ath5k_tasklet_rx);
3073        tasklet_setup(&ah->txtq, ath5k_tasklet_tx);
3074        tasklet_setup(&ah->beacontq, ath5k_tasklet_beacon);
3075        tasklet_setup(&ah->ani_tasklet, ath5k_tasklet_ani);
3076
3077        INIT_WORK(&ah->reset_work, ath5k_reset_work);
3078        INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
3079        INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
3080
3081        ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
3082        if (ret) {
3083                ATH5K_ERR(ah, "unable to read address from EEPROM\n");
3084                goto err_queues;
3085        }
3086
3087        SET_IEEE80211_PERM_ADDR(hw, mac);
3088        /* All MAC address bits matter for ACKs */
3089        ath5k_update_bssid_mask_and_opmode(ah, NULL);
3090
3091        regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
3092        ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
3093        if (ret) {
3094                ATH5K_ERR(ah, "can't initialize regulatory system\n");
3095                goto err_queues;
3096        }
3097
3098        ret = ieee80211_register_hw(hw);
3099        if (ret) {
3100                ATH5K_ERR(ah, "can't register ieee80211 hw\n");
3101                goto err_queues;
3102        }
3103
3104        if (!ath_is_world_regd(regulatory))
3105                regulatory_hint(hw->wiphy, regulatory->alpha2);
3106
3107        ath5k_init_leds(ah);
3108
3109        ath5k_sysfs_register(ah);
3110
3111        return 0;
3112err_queues:
3113        ath5k_txq_release(ah);
3114err_bhal:
3115        ath5k_hw_release_tx_queue(ah, ah->bhalq);
3116err_desc:
3117        ath5k_desc_free(ah);
3118err:
3119        return ret;
3120}
3121
3122void
3123ath5k_deinit_ah(struct ath5k_hw *ah)
3124{
3125        struct ieee80211_hw *hw = ah->hw;
3126
3127        /*
3128         * NB: the order of these is important:
3129         * o call the 802.11 layer before detaching ath5k_hw to
3130         *   ensure callbacks into the driver to delete global
3131         *   key cache entries can be handled
3132         * o reclaim the tx queue data structures after calling
3133         *   the 802.11 layer as we'll get called back to reclaim
3134         *   node state and potentially want to use them
3135         * o to cleanup the tx queues the hal is called, so detach
3136         *   it last
3137         * XXX: ??? detach ath5k_hw ???
3138         * Other than that, it's straightforward...
3139         */
3140        ieee80211_unregister_hw(hw);
3141        ath5k_desc_free(ah);
3142        ath5k_txq_release(ah);
3143        ath5k_hw_release_tx_queue(ah, ah->bhalq);
3144        ath5k_unregister_leds(ah);
3145
3146        ath5k_sysfs_unregister(ah);
3147        /*
3148         * NB: can't reclaim these until after ieee80211_ifdetach
3149         * returns because we'll get called back to reclaim node
3150         * state and potentially want to use them.
3151         */
3152        ath5k_hw_deinit(ah);
3153        free_irq(ah->irq, ah);
3154}
3155
3156bool
3157ath5k_any_vif_assoc(struct ath5k_hw *ah)
3158{
3159        struct ath5k_vif_iter_data iter_data;
3160        iter_data.hw_macaddr = NULL;
3161        iter_data.any_assoc = false;
3162        iter_data.need_set_hw_addr = false;
3163        iter_data.found_active = true;
3164
3165        ieee80211_iterate_active_interfaces_atomic(
3166                ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3167                ath5k_vif_iter, &iter_data);
3168        return iter_data.any_assoc;
3169}
3170
3171void
3172ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3173{
3174        struct ath5k_hw *ah = hw->priv;
3175        u32 rfilt;
3176        rfilt = ath5k_hw_get_rx_filter(ah);
3177        if (enable)
3178                rfilt |= AR5K_RX_FILTER_BEACON;
3179        else
3180                rfilt &= ~AR5K_RX_FILTER_BEACON;
3181        ath5k_hw_set_rx_filter(ah, rfilt);
3182        ah->filter_flags = rfilt;
3183}
3184
3185void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3186                   const char *fmt, ...)
3187{
3188        struct va_format vaf;
3189        va_list args;
3190
3191        va_start(args, fmt);
3192
3193        vaf.fmt = fmt;
3194        vaf.va = &args;
3195
3196        if (ah && ah->hw)
3197                printk("%s" pr_fmt("%s: %pV"),
3198                       level, wiphy_name(ah->hw->wiphy), &vaf);
3199        else
3200                printk("%s" pr_fmt("%pV"), level, &vaf);
3201
3202        va_end(args);
3203}
3204