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4#ifndef __MT7615_MCU_H
5#define __MT7615_MCU_H
6
7struct mt7615_mcu_txd {
8 __le32 txd[8];
9
10 __le16 len;
11 __le16 pq_id;
12
13 u8 cid;
14 u8 pkt_type;
15 u8 set_query;
16 u8 seq;
17
18 u8 uc_d2b0_rev;
19 u8 ext_cid;
20 u8 s2d_index;
21 u8 ext_cid_ack;
22
23 u32 reserved[5];
24} __packed __aligned(4);
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54
55struct mt7615_uni_txd {
56 __le32 txd[8];
57
58
59 __le16 len;
60 __le16 cid;
61
62
63 u8 reserved;
64 u8 pkt_type;
65 u8 frag_n;
66 u8 seq;
67
68
69 __le16 checksum;
70 u8 s2d_index;
71 u8 option;
72
73
74 u8 reserved2[4];
75} __packed __aligned(4);
76
77
78enum {
79 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
80 MCU_EVENT_FW_START = 0x01,
81 MCU_EVENT_GENERIC = 0x01,
82 MCU_EVENT_ACCESS_REG = 0x02,
83 MCU_EVENT_MT_PATCH_SEM = 0x04,
84 MCU_EVENT_REG_ACCESS = 0x05,
85 MCU_EVENT_SCAN_DONE = 0x0d,
86 MCU_EVENT_ROC = 0x10,
87 MCU_EVENT_BSS_ABSENCE = 0x11,
88 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
89 MCU_EVENT_CH_PRIVILEGE = 0x18,
90 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
91 MCU_EVENT_EXT = 0xed,
92 MCU_EVENT_RESTART_DL = 0xef,
93};
94
95
96enum {
97 MCU_EXT_EVENT_PS_SYNC = 0x5,
98 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
99 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
100 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
101 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
102 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
103};
104
105enum {
106 MT_SKU_CCK_1_2 = 0,
107 MT_SKU_CCK_55_11,
108 MT_SKU_OFDM_6_9,
109 MT_SKU_OFDM_12_18,
110 MT_SKU_OFDM_24_36,
111 MT_SKU_OFDM_48,
112 MT_SKU_OFDM_54,
113 MT_SKU_HT20_0_8,
114 MT_SKU_HT20_32,
115 MT_SKU_HT20_1_2_9_10,
116 MT_SKU_HT20_3_4_11_12,
117 MT_SKU_HT20_5_13,
118 MT_SKU_HT20_6_14,
119 MT_SKU_HT20_7_15,
120 MT_SKU_HT40_0_8,
121 MT_SKU_HT40_32,
122 MT_SKU_HT40_1_2_9_10,
123 MT_SKU_HT40_3_4_11_12,
124 MT_SKU_HT40_5_13,
125 MT_SKU_HT40_6_14,
126 MT_SKU_HT40_7_15,
127 MT_SKU_VHT20_0,
128 MT_SKU_VHT20_1_2,
129 MT_SKU_VHT20_3_4,
130 MT_SKU_VHT20_5_6,
131 MT_SKU_VHT20_7,
132 MT_SKU_VHT20_8,
133 MT_SKU_VHT20_9,
134 MT_SKU_VHT40_0,
135 MT_SKU_VHT40_1_2,
136 MT_SKU_VHT40_3_4,
137 MT_SKU_VHT40_5_6,
138 MT_SKU_VHT40_7,
139 MT_SKU_VHT40_8,
140 MT_SKU_VHT40_9,
141 MT_SKU_VHT80_0,
142 MT_SKU_VHT80_1_2,
143 MT_SKU_VHT80_3_4,
144 MT_SKU_VHT80_5_6,
145 MT_SKU_VHT80_7,
146 MT_SKU_VHT80_8,
147 MT_SKU_VHT80_9,
148 MT_SKU_VHT160_0,
149 MT_SKU_VHT160_1_2,
150 MT_SKU_VHT160_3_4,
151 MT_SKU_VHT160_5_6,
152 MT_SKU_VHT160_7,
153 MT_SKU_VHT160_8,
154 MT_SKU_VHT160_9,
155 MT_SKU_1SS_DELTA,
156 MT_SKU_2SS_DELTA,
157 MT_SKU_3SS_DELTA,
158 MT_SKU_4SS_DELTA,
159};
160
161struct mt7615_mcu_rxd {
162 __le32 rxd[4];
163
164 __le16 len;
165 __le16 pkt_type_id;
166
167 u8 eid;
168 u8 seq;
169 __le16 __rsv;
170
171 u8 ext_eid;
172 u8 __rsv1[2];
173 u8 s2d_index;
174};
175
176struct mt7615_mcu_rdd_report {
177 struct mt7615_mcu_rxd rxd;
178
179 u8 idx;
180 u8 long_detected;
181 u8 constant_prf_detected;
182 u8 staggered_prf_detected;
183 u8 radar_type_idx;
184 u8 periodic_pulse_num;
185 u8 long_pulse_num;
186 u8 hw_pulse_num;
187
188 u8 out_lpn;
189 u8 out_spn;
190 u8 out_crpn;
191 u8 out_crpw;
192 u8 out_crbn;
193 u8 out_stgpn;
194 u8 out_stgpw;
195
196 u8 _rsv[2];
197
198 __le32 out_pri_const;
199 __le32 out_pri_stg[3];
200
201 struct {
202 __le32 start;
203 __le16 pulse_width;
204 __le16 pulse_power;
205 } long_pulse[32];
206
207 struct {
208 __le32 start;
209 __le16 pulse_width;
210 __le16 pulse_power;
211 } periodic_pulse[32];
212
213 struct {
214 __le32 start;
215 __le16 pulse_width;
216 __le16 pulse_power;
217 u8 sc_pass;
218 u8 sw_reset;
219 } hw_pulse[32];
220};
221
222#define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
223#define MCU_PKT_ID 0xa0
224
225enum {
226 MCU_Q_QUERY,
227 MCU_Q_SET,
228 MCU_Q_RESERVED,
229 MCU_Q_NA
230};
231
232enum {
233 MCU_S2D_H2N,
234 MCU_S2D_C2N,
235 MCU_S2D_H2C,
236 MCU_S2D_H2CN
237};
238
239#define MCU_FW_PREFIX BIT(31)
240#define MCU_UNI_PREFIX BIT(30)
241#define MCU_CE_PREFIX BIT(29)
242#define MCU_QUERY_PREFIX BIT(28)
243#define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \
244 MCU_CE_PREFIX | MCU_QUERY_PREFIX)
245
246#define MCU_QUERY_MASK BIT(16)
247
248enum {
249 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01,
250 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02,
251 MCU_CMD_INIT_ACCESS_REG = 0x3,
252 MCU_CMD_PATCH_START_REQ = 0x05,
253 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07,
254 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10,
255 MCU_CMD_EXT_CID = 0xED,
256 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xEE,
257 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xEF,
258};
259
260enum {
261 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
262 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
263 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
264 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
265 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
266 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
267 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
268 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
269 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
270 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
271 MCU_EXT_CMD_GET_TEMP = 0x2c,
272 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
273 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
274 MCU_EXT_CMD_ATE_CTRL = 0x3d,
275 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
276 MCU_EXT_CMD_DBDC_CTRL = 0x45,
277 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
278 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
279 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
280 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
281 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
282 MCU_EXT_CMD_TXDPD_CAL = 0x60,
283 MCU_EXT_CMD_SET_RDD_TH = 0x7c,
284 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
285};
286
287enum {
288 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01,
289 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02,
290 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03,
291 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05,
292 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06,
293 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07,
294};
295
296enum {
297 MCU_ATE_SET_FREQ_OFFSET = 0xa,
298 MCU_ATE_SET_TX_POWER_CONTROL = 0x15,
299};
300
301struct mt7615_mcu_uni_event {
302 u8 cid;
303 u8 pad[3];
304 __le32 status;
305} __packed;
306
307struct mt7615_beacon_loss_event {
308 u8 bss_idx;
309 u8 reason;
310 u8 pad[2];
311} __packed;
312
313struct mt7615_mcu_scan_ssid {
314 __le32 ssid_len;
315 u8 ssid[IEEE80211_MAX_SSID_LEN];
316} __packed;
317
318struct mt7615_mcu_scan_channel {
319 u8 band;
320
321
322
323 u8 channel_num;
324} __packed;
325
326struct mt7615_mcu_scan_match {
327 __le32 rssi_th;
328 u8 ssid[IEEE80211_MAX_SSID_LEN];
329 u8 ssid_len;
330 u8 rsv[3];
331} __packed;
332
333struct mt7615_hw_scan_req {
334 u8 seq_num;
335 u8 bss_idx;
336 u8 scan_type;
337
338
339 u8 ssid_type;
340
341
342
343
344 u8 ssids_num;
345 u8 probe_req_num;
346 u8 scan_func;
347
348
349
350 u8 version;
351
352
353 struct mt7615_mcu_scan_ssid ssids[4];
354 __le16 probe_delay_time;
355 __le16 channel_dwell_time;
356 __le16 timeout_value;
357 u8 channel_type;
358
359
360
361
362
363
364 u8 channels_num;
365
366 struct mt7615_mcu_scan_channel channels[32];
367 __le16 ies_len;
368 u8 ies[MT7615_SCAN_IE_LEN];
369
370 u8 ext_channels_num;
371 u8 ext_ssids_num;
372 __le16 channel_min_dwell_time;
373 struct mt7615_mcu_scan_channel ext_channels[32];
374 struct mt7615_mcu_scan_ssid ext_ssids[6];
375 u8 bssid[ETH_ALEN];
376 u8 random_mac[ETH_ALEN];
377 u8 pad[63];
378 u8 ssid_type_ext;
379} __packed;
380
381#define SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
382struct mt7615_hw_scan_done {
383 u8 seq_num;
384 u8 sparse_channel_num;
385 struct mt7615_mcu_scan_channel sparse_channel;
386 u8 complete_channel_num;
387 u8 current_state;
388 u8 version;
389 u8 pad;
390 __le32 beacon_scan_num;
391 u8 pno_enabled;
392 u8 pad2[3];
393 u8 sparse_channel_valid_num;
394 u8 pad3[3];
395 u8 channel_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
396
397
398
399
400
401 __le16 channel_idle_time[SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
402
403 u8 beacon_probe_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
404 u8 mdrdy_count[SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
405 __le32 beacon_2g_num;
406 __le32 beacon_5g_num;
407} __packed;
408
409struct mt7615_sched_scan_req {
410 u8 version;
411 u8 seq_num;
412 u8 stop_on_match;
413 u8 ssids_num;
414 u8 match_num;
415 u8 pad;
416 __le16 ie_len;
417 struct mt7615_mcu_scan_ssid ssids[MT7615_MAX_SCHED_SCAN_SSID];
418 struct mt7615_mcu_scan_match match[MT7615_MAX_SCAN_MATCH];
419 u8 channel_type;
420 u8 channels_num;
421 u8 intervals_num;
422 u8 scan_func;
423 struct mt7615_mcu_scan_channel channels[64];
424 __le16 intervals[MT7615_MAX_SCHED_SCAN_INTERVAL];
425 u8 random_mac[ETH_ALEN];
426 u8 pad2[58];
427} __packed;
428
429struct nt7615_sched_scan_done {
430 u8 seq_num;
431 u8 status;
432 __le16 pad;
433} __packed;
434
435struct mt7615_mcu_reg_event {
436 __le32 reg;
437 __le32 val;
438} __packed;
439
440struct mt7615_mcu_bss_event {
441 u8 bss_idx;
442 u8 is_absent;
443 u8 free_quota;
444 u8 pad;
445} __packed;
446
447struct mt7615_bss_basic_tlv {
448 __le16 tag;
449 __le16 len;
450 u8 active;
451 u8 omac_idx;
452 u8 hw_bss_idx;
453 u8 band_idx;
454 __le32 conn_type;
455 u8 conn_state;
456 u8 wmm_idx;
457 u8 bssid[ETH_ALEN];
458 __le16 bmc_tx_wlan_idx;
459 __le16 bcn_interval;
460 u8 dtim_period;
461 u8 phymode;
462
463
464
465
466
467
468 __le16 sta_idx;
469 u8 nonht_basic_phy;
470 u8 pad[3];
471} __packed;
472
473struct mt7615_bss_qos_tlv {
474 __le16 tag;
475 __le16 len;
476 u8 qos;
477 u8 pad[3];
478} __packed;
479
480struct mt7615_wow_ctrl_tlv {
481 __le16 tag;
482 __le16 len;
483 u8 cmd;
484
485
486
487 u8 trigger;
488
489
490
491
492
493
494
495 u8 wakeup_hif;
496
497
498
499
500 u8 pad;
501 u8 rsv[4];
502} __packed;
503
504#define MT7615_WOW_MASK_MAX_LEN 16
505#define MT7615_WOW_PATTEN_MAX_LEN 128
506struct mt7615_wow_pattern_tlv {
507 __le16 tag;
508 __le16 len;
509 u8 index;
510 u8 enable;
511
512
513 u8 data_len;
514 u8 pad;
515 u8 mask[MT7615_WOW_MASK_MAX_LEN];
516 u8 pattern[MT7615_WOW_PATTEN_MAX_LEN];
517 u8 rsv[4];
518} __packed;
519
520struct mt7615_suspend_tlv {
521 __le16 tag;
522 __le16 len;
523 u8 enable;
524
525
526 u8 mdtim;
527 u8 wow_suspend;
528
529
530 u8 pad[5];
531} __packed;
532
533struct mt7615_gtk_rekey_tlv {
534 __le16 tag;
535 __le16 len;
536 u8 kek[NL80211_KEK_LEN];
537 u8 kck[NL80211_KCK_LEN];
538 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
539 u8 rekey_mode;
540
541
542
543 u8 keyid;
544 u8 pad[2];
545 __le32 proto;
546 __le32 pairwise_cipher;
547 __le32 group_cipher;
548 __le32 key_mgmt;
549 __le32 mgmt_group_cipher;
550 u8 option;
551 u8 reserverd[3];
552} __packed;
553
554struct mt7615_roc_tlv {
555 u8 bss_idx;
556 u8 token;
557 u8 active;
558 u8 primary_chan;
559 u8 sco;
560 u8 band;
561 u8 width;
562 u8 freq_seg1;
563 u8 freq_seg2;
564 u8 req_type;
565 u8 dbdc_band;
566 u8 rsv0;
567 __le32 max_interval;
568 u8 rsv1[8];
569} __packed;
570
571struct mt7615_arpns_tlv {
572 __le16 tag;
573 __le16 len;
574 u8 mode;
575 u8 ips_num;
576 u8 option;
577 u8 pad[1];
578} __packed;
579
580
581enum {
582 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03,
583 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05,
584 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f,
585 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16,
586 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17,
587 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b,
588 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1c,
589 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33,
590 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61,
591 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62,
592 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0,
593 MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0,
594};
595
596#define MCU_CMD_ACK BIT(0)
597#define MCU_CMD_UNI BIT(1)
598#define MCU_CMD_QUERY BIT(2)
599
600#define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | MCU_CMD_QUERY)
601
602enum {
603 UNI_BSS_INFO_BASIC = 0,
604 UNI_BSS_INFO_RLM = 2,
605 UNI_BSS_INFO_BCN_CONTENT = 7,
606 UNI_BSS_INFO_QBSS = 15,
607 UNI_BSS_INFO_UAPSD = 19,
608};
609
610enum {
611 UNI_SUSPEND_MODE_SETTING,
612 UNI_SUSPEND_WOW_CTRL,
613 UNI_SUSPEND_WOW_GPIO_PARAM,
614 UNI_SUSPEND_WOW_WAKEUP_PORT,
615 UNI_SUSPEND_WOW_PATTERN,
616};
617
618enum {
619 UNI_OFFLOAD_OFFLOAD_ARP,
620 UNI_OFFLOAD_OFFLOAD_ND,
621 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
622 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
623};
624
625enum {
626 PATCH_SEM_RELEASE = 0x0,
627 PATCH_SEM_GET = 0x1
628};
629
630enum {
631 PATCH_NOT_DL_SEM_FAIL = 0x0,
632 PATCH_IS_DL = 0x1,
633 PATCH_NOT_DL_SEM_SUCCESS = 0x2,
634 PATCH_REL_SEM_SUCCESS = 0x3
635};
636
637enum {
638 FW_STATE_INITIAL = 0,
639 FW_STATE_FW_DOWNLOAD = 1,
640 FW_STATE_NORMAL_OPERATION = 2,
641 FW_STATE_NORMAL_TRX = 3,
642 FW_STATE_CR4_RDY = 7
643};
644
645enum {
646 FW_STATE_PWR_ON = 1,
647 FW_STATE_N9_RDY = 2,
648};
649
650#define STA_TYPE_STA BIT(0)
651#define STA_TYPE_AP BIT(1)
652#define STA_TYPE_ADHOC BIT(2)
653#define STA_TYPE_WDS BIT(4)
654#define STA_TYPE_BC BIT(5)
655
656#define NETWORK_INFRA BIT(16)
657#define NETWORK_P2P BIT(17)
658#define NETWORK_IBSS BIT(18)
659#define NETWORK_WDS BIT(21)
660
661#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
662#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
663#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
664#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
665#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
666#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
667#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
668
669#define CONN_STATE_DISCONNECT 0
670#define CONN_STATE_CONNECT 1
671#define CONN_STATE_PORT_SECURE 2
672
673enum {
674 DEV_INFO_ACTIVE,
675 DEV_INFO_MAX_NUM
676};
677
678enum {
679 DBDC_TYPE_WMM,
680 DBDC_TYPE_MGMT,
681 DBDC_TYPE_BSS,
682 DBDC_TYPE_MBSS,
683 DBDC_TYPE_REPEATER,
684 DBDC_TYPE_MU,
685 DBDC_TYPE_BF,
686 DBDC_TYPE_PTA,
687 __DBDC_TYPE_MAX,
688};
689
690struct tlv {
691 __le16 tag;
692 __le16 len;
693} __packed;
694
695struct bss_info_omac {
696 __le16 tag;
697 __le16 len;
698 u8 hw_bss_idx;
699 u8 omac_idx;
700 u8 band_idx;
701 u8 rsv0;
702 __le32 conn_type;
703 u32 rsv1;
704} __packed;
705
706struct bss_info_basic {
707 __le16 tag;
708 __le16 len;
709 __le32 network_type;
710 u8 active;
711 u8 rsv0;
712 __le16 bcn_interval;
713 u8 bssid[ETH_ALEN];
714 u8 wmm_idx;
715 u8 dtim_period;
716 u8 bmc_tx_wlan_idx;
717 u8 cipher;
718 u8 phymode;
719 u8 rsv1[5];
720} __packed;
721
722struct bss_info_rf_ch {
723 __le16 tag;
724 __le16 len;
725 u8 pri_ch;
726 u8 central_ch0;
727 u8 central_ch1;
728 u8 bw;
729} __packed;
730
731struct bss_info_ext_bss {
732 __le16 tag;
733 __le16 len;
734 __le32 mbss_tsf_offset;
735 u8 rsv[8];
736} __packed;
737
738enum {
739 BSS_INFO_OMAC,
740 BSS_INFO_BASIC,
741 BSS_INFO_RF_CH,
742 BSS_INFO_PM,
743 BSS_INFO_UAPSD,
744 BSS_INFO_ROAM_DETECTION,
745 BSS_INFO_LQ_RM,
746 BSS_INFO_EXT_BSS,
747 BSS_INFO_BMC_INFO,
748 BSS_INFO_SYNC_MODE,
749 BSS_INFO_RA,
750 BSS_INFO_MAX_NUM
751};
752
753enum {
754 WTBL_RESET_AND_SET = 1,
755 WTBL_SET,
756 WTBL_QUERY,
757 WTBL_RESET_ALL
758};
759
760struct wtbl_req_hdr {
761 u8 wlan_idx;
762 u8 operation;
763 __le16 tlv_num;
764 u8 rsv[4];
765} __packed;
766
767struct wtbl_generic {
768 __le16 tag;
769 __le16 len;
770 u8 peer_addr[ETH_ALEN];
771 u8 muar_idx;
772 u8 skip_tx;
773 u8 cf_ack;
774 u8 qos;
775 u8 mesh;
776 u8 adm;
777 __le16 partial_aid;
778 u8 baf_en;
779 u8 aad_om;
780} __packed;
781
782struct wtbl_rx {
783 __le16 tag;
784 __le16 len;
785 u8 rcid;
786 u8 rca1;
787 u8 rca2;
788 u8 rv;
789 u8 rsv[4];
790} __packed;
791
792struct wtbl_ht {
793 __le16 tag;
794 __le16 len;
795 u8 ht;
796 u8 ldpc;
797 u8 af;
798 u8 mm;
799 u8 rsv[4];
800} __packed;
801
802struct wtbl_vht {
803 __le16 tag;
804 __le16 len;
805 u8 ldpc;
806 u8 dyn_bw;
807 u8 vht;
808 u8 txop_ps;
809 u8 rsv[4];
810} __packed;
811
812struct wtbl_tx_ps {
813 __le16 tag;
814 __le16 len;
815 u8 txps;
816 u8 rsv[3];
817} __packed;
818
819struct wtbl_hdr_trans {
820 __le16 tag;
821 __le16 len;
822 u8 to_ds;
823 u8 from_ds;
824 u8 disable_rx_trans;
825 u8 rsv;
826} __packed;
827
828enum {
829 MT_BA_TYPE_INVALID,
830 MT_BA_TYPE_ORIGINATOR,
831 MT_BA_TYPE_RECIPIENT
832};
833
834enum {
835 RST_BA_MAC_TID_MATCH,
836 RST_BA_MAC_MATCH,
837 RST_BA_NO_MATCH
838};
839
840struct wtbl_ba {
841 __le16 tag;
842 __le16 len;
843
844 u8 tid;
845 u8 ba_type;
846 u8 rsv0[2];
847
848 __le16 sn;
849 u8 ba_en;
850 u8 ba_winsize_idx;
851 __le16 ba_winsize;
852
853 u8 peer_addr[ETH_ALEN];
854 u8 rst_ba_tid;
855 u8 rst_ba_sel;
856 u8 rst_ba_sb;
857 u8 band_idx;
858 u8 rsv1[4];
859} __packed;
860
861struct wtbl_bf {
862 __le16 tag;
863 __le16 len;
864 u8 ibf;
865 u8 ebf;
866 u8 ibf_vht;
867 u8 ebf_vht;
868 u8 gid;
869 u8 pfmu_idx;
870 u8 rsv[2];
871} __packed;
872
873struct wtbl_smps {
874 __le16 tag;
875 __le16 len;
876 u8 smps;
877 u8 rsv[3];
878} __packed;
879
880struct wtbl_pn {
881 __le16 tag;
882 __le16 len;
883 u8 pn[6];
884 u8 rsv[2];
885} __packed;
886
887struct wtbl_spe {
888 __le16 tag;
889 __le16 len;
890 u8 spe_idx;
891 u8 rsv[3];
892} __packed;
893
894struct wtbl_raw {
895 __le16 tag;
896 __le16 len;
897 u8 wtbl_idx;
898 u8 dw;
899 u8 rsv[2];
900 __le32 msk;
901 __le32 val;
902} __packed;
903
904#define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
905 sizeof(struct wtbl_generic) + \
906 sizeof(struct wtbl_rx) + \
907 sizeof(struct wtbl_ht) + \
908 sizeof(struct wtbl_vht) + \
909 sizeof(struct wtbl_tx_ps) + \
910 sizeof(struct wtbl_hdr_trans) +\
911 sizeof(struct wtbl_ba) + \
912 sizeof(struct wtbl_bf) + \
913 sizeof(struct wtbl_smps) + \
914 sizeof(struct wtbl_pn) + \
915 sizeof(struct wtbl_spe))
916
917#define MT7615_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
918 sizeof(struct sta_rec_basic) + \
919 sizeof(struct sta_rec_ht) + \
920 sizeof(struct sta_rec_vht) + \
921 sizeof(struct sta_rec_uapsd) + \
922 sizeof(struct tlv) + \
923 MT7615_WTBL_UPDATE_MAX_SIZE)
924
925#define MT7615_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \
926 sizeof(struct wtbl_ba))
927
928enum {
929 WTBL_GENERIC,
930 WTBL_RX,
931 WTBL_HT,
932 WTBL_VHT,
933 WTBL_PEER_PS,
934 WTBL_TX_PS,
935 WTBL_HDR_TRANS,
936 WTBL_SEC_KEY,
937 WTBL_BA,
938 WTBL_RDG,
939 WTBL_PROTECT,
940 WTBL_CLEAR,
941 WTBL_BF,
942 WTBL_SMPS,
943 WTBL_RAW_DATA,
944 WTBL_PN,
945 WTBL_SPE,
946 WTBL_MAX_NUM
947};
948
949struct sta_ntlv_hdr {
950 u8 rsv[2];
951 __le16 tlv_num;
952} __packed;
953
954struct sta_req_hdr {
955 u8 bss_idx;
956 u8 wlan_idx;
957 __le16 tlv_num;
958 u8 is_tlv_append;
959 u8 muar_idx;
960 u8 rsv[2];
961} __packed;
962
963struct sta_rec_state {
964 __le16 tag;
965 __le16 len;
966 u8 state;
967 __le32 flags;
968 u8 vhtop;
969 u8 pad[2];
970} __packed;
971
972struct sta_rec_basic {
973 __le16 tag;
974 __le16 len;
975 __le32 conn_type;
976 u8 conn_state;
977 u8 qos;
978 __le16 aid;
979 u8 peer_addr[ETH_ALEN];
980#define EXTRA_INFO_VER BIT(0)
981#define EXTRA_INFO_NEW BIT(1)
982 __le16 extra_info;
983} __packed;
984
985struct sta_rec_ht {
986 __le16 tag;
987 __le16 len;
988 __le16 ht_cap;
989 u16 rsv;
990} __packed;
991
992struct sta_rec_vht {
993 __le16 tag;
994 __le16 len;
995 __le32 vht_cap;
996 __le16 vht_rx_mcs_map;
997 __le16 vht_tx_mcs_map;
998} __packed;
999
1000struct sta_rec_ba {
1001 __le16 tag;
1002 __le16 len;
1003 u8 tid;
1004 u8 ba_type;
1005 u8 amsdu;
1006 u8 ba_en;
1007 __le16 ssn;
1008 __le16 winsize;
1009} __packed;
1010
1011struct sta_rec_uapsd {
1012 __le16 tag;
1013 __le16 len;
1014 u8 dac_map;
1015 u8 tac_map;
1016 u8 max_sp;
1017 u8 rsv0;
1018 __le16 listen_interval;
1019 u8 rsv1[2];
1020} __packed;
1021
1022enum {
1023 STA_REC_BASIC,
1024 STA_REC_RA,
1025 STA_REC_RA_CMM_INFO,
1026 STA_REC_RA_UPDATE,
1027 STA_REC_BF,
1028 STA_REC_AMSDU,
1029 STA_REC_BA,
1030 STA_REC_STATE,
1031 STA_REC_TX_PROC,
1032 STA_REC_HT,
1033 STA_REC_VHT,
1034 STA_REC_APPS,
1035 STA_REC_WTBL = 13,
1036 STA_REC_MAX_NUM
1037};
1038
1039enum {
1040 CMD_CBW_20MHZ,
1041 CMD_CBW_40MHZ,
1042 CMD_CBW_80MHZ,
1043 CMD_CBW_160MHZ,
1044 CMD_CBW_10MHZ,
1045 CMD_CBW_5MHZ,
1046 CMD_CBW_8080MHZ
1047};
1048
1049enum {
1050 CH_SWITCH_NORMAL = 0,
1051 CH_SWITCH_SCAN = 3,
1052 CH_SWITCH_MCC = 4,
1053 CH_SWITCH_DFS = 5,
1054 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1055 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1056 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1057 CH_SWITCH_SCAN_BYPASS_DPD = 9
1058};
1059
1060#endif
1061
