1
2
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4
5
6#include <linux/delay.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/phy/phy.h>
11#include <linux/regulator/consumer.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/slab.h>
15
16#include <soc/tegra/fuse.h>
17
18#include "xusb.h"
19
20
21#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22#define HS_CURR_LEVEL_PAD_MASK 0x3f
23#define HS_TERM_RANGE_ADJ_SHIFT 7
24#define HS_TERM_RANGE_ADJ_MASK 0xf
25#define HS_SQUELCH_SHIFT 29
26#define HS_SQUELCH_MASK 0x7
27
28#define RPD_CTRL_SHIFT 0
29#define RPD_CTRL_MASK 0x1f
30
31
32#define XUSB_PADCTL_USB2_PAD_MUX 0x4
33#define USB2_PORT_SHIFT(x) ((x) * 2)
34#define USB2_PORT_MASK 0x3
35#define PORT_XUSB 1
36#define HSIC_PORT_SHIFT(x) ((x) + 20)
37#define HSIC_PORT_MASK 0x1
38#define PORT_HSIC 0
39
40#define XUSB_PADCTL_USB2_PORT_CAP 0x8
41#define XUSB_PADCTL_SS_PORT_CAP 0xc
42#define PORTX_CAP_SHIFT(x) ((x) * 4)
43#define PORT_CAP_MASK 0x3
44#define PORT_CAP_DISABLED 0x0
45#define PORT_CAP_HOST 0x1
46#define PORT_CAP_DEVICE 0x2
47#define PORT_CAP_OTG 0x3
48
49#define XUSB_PADCTL_ELPG_PROGRAM 0x20
50#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56#define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
61
62#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63#define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64#define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65#define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66#define XUSB_PADCTL_SS_PORT_CFG 0x2c
67#define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68#define PORTX_SPEED_SUPPORT_MASK (0x3)
69#define PORT_SPEED_SUPPORT_GEN1 (0x0)
70
71#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72#define HS_CURR_LEVEL(x) ((x) & 0x3f)
73#define TERM_SEL BIT(25)
74#define USB2_OTG_PD BIT(26)
75#define USB2_OTG_PD2 BIT(27)
76#define USB2_OTG_PD2_OVRD_EN BIT(28)
77#define USB2_OTG_PD_ZI BIT(29)
78
79#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80#define USB2_OTG_PD_DR BIT(2)
81#define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82#define RPD_CTRL(x) (((x) & 0x1f) << 26)
83
84#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85#define BIAS_PAD_PD BIT(11)
86#define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
87
88#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89#define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90#define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91#define USB2_PD_TRK BIT(26)
92
93#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
94#define HSIC_PD_TX_DATA0 BIT(1)
95#define HSIC_PD_TX_STROBE BIT(3)
96#define HSIC_PD_RX_DATA0 BIT(4)
97#define HSIC_PD_RX_STROBE BIT(6)
98#define HSIC_PD_ZI_DATA0 BIT(7)
99#define HSIC_PD_ZI_STROBE BIT(9)
100#define HSIC_RPD_DATA0 BIT(13)
101#define HSIC_RPD_STROBE BIT(15)
102#define HSIC_RPU_DATA0 BIT(16)
103#define HSIC_RPU_STROBE BIT(18)
104
105#define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
106#define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
107#define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
108#define HSIC_PD_TRK BIT(19)
109
110#define USB2_VBUS_ID 0x360
111#define VBUS_OVERRIDE BIT(14)
112#define ID_OVERRIDE(x) (((x) & 0xf) << 18)
113#define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
114#define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
115
116#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
117 { \
118 .name = _name, \
119 .offset = _offset, \
120 .shift = _shift, \
121 .mask = _mask, \
122 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
123 .funcs = tegra186_##_type##_functions, \
124 }
125
126struct tegra_xusb_fuse_calibration {
127 u32 *hs_curr_level;
128 u32 hs_squelch;
129 u32 hs_term_range_adj;
130 u32 rpd_ctrl;
131};
132
133struct tegra186_xusb_padctl {
134 struct tegra_xusb_padctl base;
135
136 struct tegra_xusb_fuse_calibration calib;
137
138
139 struct clk *usb2_trk_clk;
140 unsigned int bias_pad_enable;
141};
142
143static inline struct tegra186_xusb_padctl *
144to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
145{
146 return container_of(padctl, struct tegra186_xusb_padctl, base);
147}
148
149
150static struct tegra_xusb_lane *
151tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
152 unsigned int index)
153{
154 struct tegra_xusb_usb2_lane *usb2;
155 int err;
156
157 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
158 if (!usb2)
159 return ERR_PTR(-ENOMEM);
160
161 INIT_LIST_HEAD(&usb2->base.list);
162 usb2->base.soc = &pad->soc->lanes[index];
163 usb2->base.index = index;
164 usb2->base.pad = pad;
165 usb2->base.np = np;
166
167 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
168 if (err < 0) {
169 kfree(usb2);
170 return ERR_PTR(err);
171 }
172
173 return &usb2->base;
174}
175
176static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
177{
178 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
179
180 kfree(usb2);
181}
182
183static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
184 .probe = tegra186_usb2_lane_probe,
185 .remove = tegra186_usb2_lane_remove,
186};
187
188static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
189{
190 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
191 struct device *dev = padctl->dev;
192 u32 value;
193 int err;
194
195 mutex_lock(&padctl->lock);
196
197 if (priv->bias_pad_enable++ > 0) {
198 mutex_unlock(&padctl->lock);
199 return;
200 }
201
202 err = clk_prepare_enable(priv->usb2_trk_clk);
203 if (err < 0)
204 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
205
206 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
207 value &= ~USB2_TRK_START_TIMER(~0);
208 value |= USB2_TRK_START_TIMER(0x1e);
209 value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
210 value |= USB2_TRK_DONE_RESET_TIMER(0xa);
211 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
212
213 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
214 value &= ~BIAS_PAD_PD;
215 value &= ~HS_SQUELCH_LEVEL(~0);
216 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
217 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
218
219 udelay(1);
220
221 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
222 value &= ~USB2_PD_TRK;
223 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
224
225 mutex_unlock(&padctl->lock);
226}
227
228static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
229{
230 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
231 u32 value;
232
233 mutex_lock(&padctl->lock);
234
235 if (WARN_ON(priv->bias_pad_enable == 0)) {
236 mutex_unlock(&padctl->lock);
237 return;
238 }
239
240 if (--priv->bias_pad_enable > 0) {
241 mutex_unlock(&padctl->lock);
242 return;
243 }
244
245 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
246 value |= USB2_PD_TRK;
247 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
248
249 clk_disable_unprepare(priv->usb2_trk_clk);
250
251 mutex_unlock(&padctl->lock);
252}
253
254static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
255{
256 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
257 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
258 struct tegra_xusb_usb2_port *port;
259 struct device *dev = padctl->dev;
260 unsigned int index = lane->index;
261 u32 value;
262
263 if (!phy)
264 return;
265
266 port = tegra_xusb_find_usb2_port(padctl, index);
267 if (!port) {
268 dev_err(dev, "no port found for USB2 lane %u\n", index);
269 return;
270 }
271
272 tegra186_utmi_bias_pad_power_on(padctl);
273
274 udelay(2);
275
276 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
277 value &= ~USB2_OTG_PD;
278 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
279
280 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
281 value &= ~USB2_OTG_PD_DR;
282 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
283}
284
285static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
286{
287 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
288 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
289 unsigned int index = lane->index;
290 u32 value;
291
292 if (!phy)
293 return;
294
295 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
296 value |= USB2_OTG_PD;
297 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
298
299 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
300 value |= USB2_OTG_PD_DR;
301 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
302
303 udelay(2);
304
305 tegra186_utmi_bias_pad_power_off(padctl);
306}
307
308static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
309 bool status)
310{
311 u32 value;
312
313 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
314
315 value = padctl_readl(padctl, USB2_VBUS_ID);
316
317 if (status) {
318 value |= VBUS_OVERRIDE;
319 value &= ~ID_OVERRIDE(~0);
320 value |= ID_OVERRIDE_FLOATING;
321 } else {
322 value &= ~VBUS_OVERRIDE;
323 }
324
325 padctl_writel(padctl, value, USB2_VBUS_ID);
326
327 return 0;
328}
329
330static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
331 bool status)
332{
333 u32 value;
334
335 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
336
337 value = padctl_readl(padctl, USB2_VBUS_ID);
338
339 if (status) {
340 if (value & VBUS_OVERRIDE) {
341 value &= ~VBUS_OVERRIDE;
342 padctl_writel(padctl, value, USB2_VBUS_ID);
343 usleep_range(1000, 2000);
344
345 value = padctl_readl(padctl, USB2_VBUS_ID);
346 }
347
348 value &= ~ID_OVERRIDE(~0);
349 value |= ID_OVERRIDE_GROUNDED;
350 } else {
351 value &= ~ID_OVERRIDE(~0);
352 value |= ID_OVERRIDE_FLOATING;
353 }
354
355 padctl_writel(padctl, value, USB2_VBUS_ID);
356
357 return 0;
358}
359
360static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
361 int submode)
362{
363 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
364 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
365 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
366 lane->index);
367 int err = 0;
368
369 mutex_lock(&padctl->lock);
370
371 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
372
373 if (mode == PHY_MODE_USB_OTG) {
374 if (submode == USB_ROLE_HOST) {
375 tegra186_xusb_padctl_id_override(padctl, true);
376
377 err = regulator_enable(port->supply);
378 } else if (submode == USB_ROLE_DEVICE) {
379 tegra186_xusb_padctl_vbus_override(padctl, true);
380 } else if (submode == USB_ROLE_NONE) {
381
382
383
384
385
386 if (regulator_is_enabled(port->supply))
387 regulator_disable(port->supply);
388
389 tegra186_xusb_padctl_id_override(padctl, false);
390 tegra186_xusb_padctl_vbus_override(padctl, false);
391 }
392 }
393
394 mutex_unlock(&padctl->lock);
395
396 return err;
397}
398
399static int tegra186_utmi_phy_power_on(struct phy *phy)
400{
401 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
402 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
403 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
404 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
405 struct tegra_xusb_usb2_port *port;
406 unsigned int index = lane->index;
407 struct device *dev = padctl->dev;
408 u32 value;
409
410 port = tegra_xusb_find_usb2_port(padctl, index);
411 if (!port) {
412 dev_err(dev, "no port found for USB2 lane %u\n", index);
413 return -ENODEV;
414 }
415
416 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
417 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
418 value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
419 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
420
421 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
422 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
423
424 if (port->mode == USB_DR_MODE_UNKNOWN)
425 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
426 else if (port->mode == USB_DR_MODE_PERIPHERAL)
427 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
428 else if (port->mode == USB_DR_MODE_HOST)
429 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
430 else if (port->mode == USB_DR_MODE_OTG)
431 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
432
433 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
434
435 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
436 value &= ~USB2_OTG_PD_ZI;
437 value |= TERM_SEL;
438 value &= ~HS_CURR_LEVEL(~0);
439
440 if (usb2->hs_curr_level_offset) {
441 int hs_current_level;
442
443 hs_current_level = (int)priv->calib.hs_curr_level[index] +
444 usb2->hs_curr_level_offset;
445
446 if (hs_current_level < 0)
447 hs_current_level = 0;
448 if (hs_current_level > 0x3f)
449 hs_current_level = 0x3f;
450
451 value |= HS_CURR_LEVEL(hs_current_level);
452 } else {
453 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
454 }
455
456 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
457
458 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
459 value &= ~TERM_RANGE_ADJ(~0);
460 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
461 value &= ~RPD_CTRL(~0);
462 value |= RPD_CTRL(priv->calib.rpd_ctrl);
463 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
464
465
466 tegra_phy_xusb_utmi_pad_power_on(phy);
467 return 0;
468}
469
470static int tegra186_utmi_phy_power_off(struct phy *phy)
471{
472
473 tegra_phy_xusb_utmi_pad_power_down(phy);
474
475 return 0;
476}
477
478static int tegra186_utmi_phy_init(struct phy *phy)
479{
480 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
481 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
482 struct tegra_xusb_usb2_port *port;
483 unsigned int index = lane->index;
484 struct device *dev = padctl->dev;
485 int err;
486
487 port = tegra_xusb_find_usb2_port(padctl, index);
488 if (!port) {
489 dev_err(dev, "no port found for USB2 lane %u\n", index);
490 return -ENODEV;
491 }
492
493 if (port->supply && port->mode == USB_DR_MODE_HOST) {
494 err = regulator_enable(port->supply);
495 if (err) {
496 dev_err(dev, "failed to enable port %u VBUS: %d\n",
497 index, err);
498 return err;
499 }
500 }
501
502 return 0;
503}
504
505static int tegra186_utmi_phy_exit(struct phy *phy)
506{
507 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
508 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
509 struct tegra_xusb_usb2_port *port;
510 unsigned int index = lane->index;
511 struct device *dev = padctl->dev;
512 int err;
513
514 port = tegra_xusb_find_usb2_port(padctl, index);
515 if (!port) {
516 dev_err(dev, "no port found for USB2 lane %u\n", index);
517 return -ENODEV;
518 }
519
520 if (port->supply && port->mode == USB_DR_MODE_HOST) {
521 err = regulator_disable(port->supply);
522 if (err) {
523 dev_err(dev, "failed to disable port %u VBUS: %d\n",
524 index, err);
525 return err;
526 }
527 }
528
529 return 0;
530}
531
532static const struct phy_ops utmi_phy_ops = {
533 .init = tegra186_utmi_phy_init,
534 .exit = tegra186_utmi_phy_exit,
535 .power_on = tegra186_utmi_phy_power_on,
536 .power_off = tegra186_utmi_phy_power_off,
537 .set_mode = tegra186_utmi_phy_set_mode,
538 .owner = THIS_MODULE,
539};
540
541static struct tegra_xusb_pad *
542tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
543 const struct tegra_xusb_pad_soc *soc,
544 struct device_node *np)
545{
546 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
547 struct tegra_xusb_usb2_pad *usb2;
548 struct tegra_xusb_pad *pad;
549 int err;
550
551 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
552 if (!usb2)
553 return ERR_PTR(-ENOMEM);
554
555 pad = &usb2->base;
556 pad->ops = &tegra186_usb2_lane_ops;
557 pad->soc = soc;
558
559 err = tegra_xusb_pad_init(pad, padctl, np);
560 if (err < 0) {
561 kfree(usb2);
562 goto out;
563 }
564
565 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
566 if (IS_ERR(priv->usb2_trk_clk)) {
567 err = PTR_ERR(priv->usb2_trk_clk);
568 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
569 goto unregister;
570 }
571
572 err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
573 if (err < 0)
574 goto unregister;
575
576 dev_set_drvdata(&pad->dev, pad);
577
578 return pad;
579
580unregister:
581 device_unregister(&pad->dev);
582out:
583 return ERR_PTR(err);
584}
585
586static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
587{
588 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
589
590 kfree(usb2);
591}
592
593static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
594 .probe = tegra186_usb2_pad_probe,
595 .remove = tegra186_usb2_pad_remove,
596};
597
598static const char * const tegra186_usb2_functions[] = {
599 "xusb",
600};
601
602static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
603{
604 return 0;
605}
606
607static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
608{
609}
610
611static struct tegra_xusb_lane *
612tegra186_usb2_port_map(struct tegra_xusb_port *port)
613{
614 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
615}
616
617static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
618 .release = tegra_xusb_usb2_port_release,
619 .remove = tegra_xusb_usb2_port_remove,
620 .enable = tegra186_usb2_port_enable,
621 .disable = tegra186_usb2_port_disable,
622 .map = tegra186_usb2_port_map,
623};
624
625
626static struct tegra_xusb_lane *
627tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
628 unsigned int index)
629{
630 struct tegra_xusb_usb3_lane *usb3;
631 int err;
632
633 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
634 if (!usb3)
635 return ERR_PTR(-ENOMEM);
636
637 INIT_LIST_HEAD(&usb3->base.list);
638 usb3->base.soc = &pad->soc->lanes[index];
639 usb3->base.index = index;
640 usb3->base.pad = pad;
641 usb3->base.np = np;
642
643 err = tegra_xusb_lane_parse_dt(&usb3->base, np);
644 if (err < 0) {
645 kfree(usb3);
646 return ERR_PTR(err);
647 }
648
649 return &usb3->base;
650}
651
652static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
653{
654 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
655
656 kfree(usb3);
657}
658
659static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
660 .probe = tegra186_usb3_lane_probe,
661 .remove = tegra186_usb3_lane_remove,
662};
663static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
664{
665 return 0;
666}
667
668static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
669{
670}
671
672static struct tegra_xusb_lane *
673tegra186_usb3_port_map(struct tegra_xusb_port *port)
674{
675 return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
676}
677
678static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
679 .release = tegra_xusb_usb3_port_release,
680 .remove = tegra_xusb_usb3_port_remove,
681 .enable = tegra186_usb3_port_enable,
682 .disable = tegra186_usb3_port_disable,
683 .map = tegra186_usb3_port_map,
684};
685
686static int tegra186_usb3_phy_power_on(struct phy *phy)
687{
688 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
689 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
690 struct tegra_xusb_usb3_port *port;
691 struct tegra_xusb_usb2_port *usb2;
692 unsigned int index = lane->index;
693 struct device *dev = padctl->dev;
694 u32 value;
695
696 port = tegra_xusb_find_usb3_port(padctl, index);
697 if (!port) {
698 dev_err(dev, "no port found for USB3 lane %u\n", index);
699 return -ENODEV;
700 }
701
702 usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
703 if (!usb2) {
704 dev_err(dev, "no companion port found for USB3 lane %u\n",
705 index);
706 return -ENODEV;
707 }
708
709 mutex_lock(&padctl->lock);
710
711 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
712 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
713
714 if (usb2->mode == USB_DR_MODE_UNKNOWN)
715 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
716 else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
717 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
718 else if (usb2->mode == USB_DR_MODE_HOST)
719 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
720 else if (usb2->mode == USB_DR_MODE_OTG)
721 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
722
723 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
724
725 if (padctl->soc->supports_gen2 && port->disable_gen2) {
726 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
727 value &= ~(PORTX_SPEED_SUPPORT_MASK <<
728 PORTX_SPEED_SUPPORT_SHIFT(index));
729 value |= (PORT_SPEED_SUPPORT_GEN1 <<
730 PORTX_SPEED_SUPPORT_SHIFT(index));
731 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
732 }
733
734 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
735 value &= ~SSPX_ELPG_VCORE_DOWN(index);
736 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
737
738 usleep_range(100, 200);
739
740 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
741 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
742 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
743
744 usleep_range(100, 200);
745
746 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
747 value &= ~SSPX_ELPG_CLAMP_EN(index);
748 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
749
750 mutex_unlock(&padctl->lock);
751
752 return 0;
753}
754
755static int tegra186_usb3_phy_power_off(struct phy *phy)
756{
757 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
758 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
759 struct tegra_xusb_usb3_port *port;
760 unsigned int index = lane->index;
761 struct device *dev = padctl->dev;
762 u32 value;
763
764 port = tegra_xusb_find_usb3_port(padctl, index);
765 if (!port) {
766 dev_err(dev, "no port found for USB3 lane %u\n", index);
767 return -ENODEV;
768 }
769
770 mutex_lock(&padctl->lock);
771
772 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
773 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
774 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
775
776 usleep_range(100, 200);
777
778 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
779 value |= SSPX_ELPG_CLAMP_EN(index);
780 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
781
782 usleep_range(250, 350);
783
784 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
785 value |= SSPX_ELPG_VCORE_DOWN(index);
786 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
787
788 mutex_unlock(&padctl->lock);
789
790 return 0;
791}
792
793static int tegra186_usb3_phy_init(struct phy *phy)
794{
795 return 0;
796}
797
798static int tegra186_usb3_phy_exit(struct phy *phy)
799{
800 return 0;
801}
802
803static const struct phy_ops usb3_phy_ops = {
804 .init = tegra186_usb3_phy_init,
805 .exit = tegra186_usb3_phy_exit,
806 .power_on = tegra186_usb3_phy_power_on,
807 .power_off = tegra186_usb3_phy_power_off,
808 .owner = THIS_MODULE,
809};
810
811static struct tegra_xusb_pad *
812tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
813 const struct tegra_xusb_pad_soc *soc,
814 struct device_node *np)
815{
816 struct tegra_xusb_usb3_pad *usb3;
817 struct tegra_xusb_pad *pad;
818 int err;
819
820 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
821 if (!usb3)
822 return ERR_PTR(-ENOMEM);
823
824 pad = &usb3->base;
825 pad->ops = &tegra186_usb3_lane_ops;
826 pad->soc = soc;
827
828 err = tegra_xusb_pad_init(pad, padctl, np);
829 if (err < 0) {
830 kfree(usb3);
831 goto out;
832 }
833
834 err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
835 if (err < 0)
836 goto unregister;
837
838 dev_set_drvdata(&pad->dev, pad);
839
840 return pad;
841
842unregister:
843 device_unregister(&pad->dev);
844out:
845 return ERR_PTR(err);
846}
847
848static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
849{
850 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
851
852 kfree(usb2);
853}
854
855static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
856 .probe = tegra186_usb3_pad_probe,
857 .remove = tegra186_usb3_pad_remove,
858};
859
860static const char * const tegra186_usb3_functions[] = {
861 "xusb",
862};
863
864static int
865tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
866{
867 struct device *dev = padctl->base.dev;
868 unsigned int i, count;
869 u32 value, *level;
870 int err;
871
872 count = padctl->base.soc->ports.usb2.count;
873
874 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
875 if (!level)
876 return -ENOMEM;
877
878 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
879 if (err) {
880 if (err != -EPROBE_DEFER)
881 dev_err(dev, "failed to read calibration fuse: %d\n",
882 err);
883 return err;
884 }
885
886 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
887
888 for (i = 0; i < count; i++)
889 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
890 HS_CURR_LEVEL_PAD_MASK;
891
892 padctl->calib.hs_curr_level = level;
893
894 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
895 HS_SQUELCH_MASK;
896 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
897 HS_TERM_RANGE_ADJ_MASK;
898
899 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
900 if (err) {
901 dev_err(dev, "failed to read calibration fuse: %d\n", err);
902 return err;
903 }
904
905 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
906
907 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
908
909 return 0;
910}
911
912static struct tegra_xusb_padctl *
913tegra186_xusb_padctl_probe(struct device *dev,
914 const struct tegra_xusb_padctl_soc *soc)
915{
916 struct tegra186_xusb_padctl *priv;
917 int err;
918
919 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
920 if (!priv)
921 return ERR_PTR(-ENOMEM);
922
923 priv->base.dev = dev;
924 priv->base.soc = soc;
925
926 err = tegra186_xusb_read_fuse_calibration(priv);
927 if (err < 0)
928 return ERR_PTR(err);
929
930 return &priv->base;
931}
932
933static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
934{
935}
936
937static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
938 .probe = tegra186_xusb_padctl_probe,
939 .remove = tegra186_xusb_padctl_remove,
940 .vbus_override = tegra186_xusb_padctl_vbus_override,
941};
942
943#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
944static const char * const tegra186_xusb_padctl_supply_names[] = {
945 "avdd-pll-erefeut",
946 "avdd-usb",
947 "vclamp-usb",
948 "vddio-hsic",
949};
950
951static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
952 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
953 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
954 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
955};
956
957static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
958 .name = "usb2",
959 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
960 .lanes = tegra186_usb2_lanes,
961 .ops = &tegra186_usb2_pad_ops,
962};
963
964static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
965 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
966 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
967 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
968};
969
970static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
971 .name = "usb3",
972 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
973 .lanes = tegra186_usb3_lanes,
974 .ops = &tegra186_usb3_pad_ops,
975};
976
977static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
978 &tegra186_usb2_pad,
979 &tegra186_usb3_pad,
980#if 0
981 &tegra186_hsic_pad,
982#endif
983};
984
985const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
986 .num_pads = ARRAY_SIZE(tegra186_pads),
987 .pads = tegra186_pads,
988 .ports = {
989 .usb2 = {
990 .ops = &tegra186_usb2_port_ops,
991 .count = 3,
992 },
993#if 0
994 .hsic = {
995 .ops = &tegra186_hsic_port_ops,
996 .count = 1,
997 },
998#endif
999 .usb3 = {
1000 .ops = &tegra186_usb3_port_ops,
1001 .count = 3,
1002 },
1003 },
1004 .ops = &tegra186_xusb_padctl_ops,
1005 .supply_names = tegra186_xusb_padctl_supply_names,
1006 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1007};
1008EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1009#endif
1010
1011#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
1012static const char * const tegra194_xusb_padctl_supply_names[] = {
1013 "avdd-usb",
1014 "vclamp-usb",
1015};
1016
1017static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1018 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1019 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1020 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1021 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1022};
1023
1024static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1025 .name = "usb2",
1026 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1027 .lanes = tegra194_usb2_lanes,
1028 .ops = &tegra186_usb2_pad_ops,
1029};
1030
1031static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1032 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1033 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1034 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1035 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1036};
1037
1038static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1039 .name = "usb3",
1040 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1041 .lanes = tegra194_usb3_lanes,
1042 .ops = &tegra186_usb3_pad_ops,
1043};
1044
1045static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1046 &tegra194_usb2_pad,
1047 &tegra194_usb3_pad,
1048};
1049
1050const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1051 .num_pads = ARRAY_SIZE(tegra194_pads),
1052 .pads = tegra194_pads,
1053 .ports = {
1054 .usb2 = {
1055 .ops = &tegra186_usb2_port_ops,
1056 .count = 4,
1057 },
1058 .usb3 = {
1059 .ops = &tegra186_usb3_port_ops,
1060 .count = 4,
1061 },
1062 },
1063 .ops = &tegra186_xusb_padctl_ops,
1064 .supply_names = tegra194_xusb_padctl_supply_names,
1065 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1066 .supports_gen2 = true,
1067};
1068EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1069#endif
1070
1071MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1072MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1073MODULE_LICENSE("GPL v2");
1074
