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10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/firmware.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/io.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/qcom_scm.h>
21#include <linux/regulator/consumer.h>
22#include <linux/remoteproc.h>
23#include <linux/soc/qcom/mdt_loader.h>
24#include <linux/soc/qcom/smem.h>
25#include <linux/soc/qcom/smem_state.h>
26#include <linux/rpmsg/qcom_smd.h>
27
28#include "qcom_common.h"
29#include "remoteproc_internal.h"
30#include "qcom_pil_info.h"
31#include "qcom_wcnss.h"
32
33#define WCNSS_CRASH_REASON_SMEM 422
34#define WCNSS_FIRMWARE_NAME "wcnss.mdt"
35#define WCNSS_PAS_ID 6
36#define WCNSS_SSCTL_ID 0x13
37
38#define WCNSS_SPARE_NVBIN_DLND BIT(25)
39
40#define WCNSS_PMU_IRIS_XO_CFG BIT(3)
41#define WCNSS_PMU_IRIS_XO_EN BIT(4)
42#define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
43#define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6)
44
45#define WCNSS_PMU_IRIS_RESET BIT(7)
46#define WCNSS_PMU_IRIS_RESET_STS BIT(8)
47#define WCNSS_PMU_IRIS_XO_READ BIT(9)
48#define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
49
50#define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
51#define WCNSS_PMU_XO_MODE_19p2 0
52#define WCNSS_PMU_XO_MODE_48 3
53
54struct wcnss_data {
55 size_t pmu_offset;
56 size_t spare_offset;
57
58 const struct wcnss_vreg_info *vregs;
59 size_t num_vregs;
60};
61
62struct qcom_wcnss {
63 struct device *dev;
64 struct rproc *rproc;
65
66 void __iomem *pmu_cfg;
67 void __iomem *spare_out;
68
69 bool use_48mhz_xo;
70
71 int wdog_irq;
72 int fatal_irq;
73 int ready_irq;
74 int handover_irq;
75 int stop_ack_irq;
76
77 struct qcom_smem_state *state;
78 unsigned stop_bit;
79
80 struct mutex iris_lock;
81 struct qcom_iris *iris;
82
83 struct regulator_bulk_data *vregs;
84 size_t num_vregs;
85
86 struct completion start_done;
87 struct completion stop_done;
88
89 phys_addr_t mem_phys;
90 phys_addr_t mem_reloc;
91 void *mem_region;
92 size_t mem_size;
93
94 struct qcom_rproc_subdev smd_subdev;
95 struct qcom_sysmon *sysmon;
96};
97
98static const struct wcnss_data riva_data = {
99 .pmu_offset = 0x28,
100 .spare_offset = 0xb4,
101
102 .vregs = (struct wcnss_vreg_info[]) {
103 { "vddmx", 1050000, 1150000, 0 },
104 { "vddcx", 1050000, 1150000, 0 },
105 { "vddpx", 1800000, 1800000, 0 },
106 },
107 .num_vregs = 3,
108};
109
110static const struct wcnss_data pronto_v1_data = {
111 .pmu_offset = 0x1004,
112 .spare_offset = 0x1088,
113
114 .vregs = (struct wcnss_vreg_info[]) {
115 { "vddmx", 950000, 1150000, 0 },
116 { "vddcx", .super_turbo = true},
117 { "vddpx", 1800000, 1800000, 0 },
118 },
119 .num_vregs = 3,
120};
121
122static const struct wcnss_data pronto_v2_data = {
123 .pmu_offset = 0x1004,
124 .spare_offset = 0x1088,
125
126 .vregs = (struct wcnss_vreg_info[]) {
127 { "vddmx", 1287500, 1287500, 0 },
128 { "vddcx", .super_turbo = true },
129 { "vddpx", 1800000, 1800000, 0 },
130 },
131 .num_vregs = 3,
132};
133
134void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
135 struct qcom_iris *iris,
136 bool use_48mhz_xo)
137{
138 mutex_lock(&wcnss->iris_lock);
139
140 wcnss->iris = iris;
141 wcnss->use_48mhz_xo = use_48mhz_xo;
142
143 mutex_unlock(&wcnss->iris_lock);
144}
145
146static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
147{
148 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
149 int ret;
150
151 ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
152 wcnss->mem_region, wcnss->mem_phys,
153 wcnss->mem_size, &wcnss->mem_reloc);
154 if (ret)
155 return ret;
156
157 qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
158
159 return 0;
160}
161
162static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
163{
164 u32 val;
165
166
167 val = readl(wcnss->spare_out);
168 val |= WCNSS_SPARE_NVBIN_DLND;
169 writel(val, wcnss->spare_out);
170}
171
172static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
173{
174 u32 val;
175
176
177 writel(0, wcnss->pmu_cfg);
178
179 val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
180 writel(val, wcnss->pmu_cfg);
181
182
183 val &= ~WCNSS_PMU_XO_MODE_MASK;
184 if (wcnss->use_48mhz_xo)
185 val |= WCNSS_PMU_XO_MODE_48 << 1;
186 else
187 val |= WCNSS_PMU_XO_MODE_19p2 << 1;
188 writel(val, wcnss->pmu_cfg);
189
190
191 val |= WCNSS_PMU_IRIS_RESET;
192 writel(val, wcnss->pmu_cfg);
193
194
195 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
196 cpu_relax();
197
198
199 val &= ~WCNSS_PMU_IRIS_RESET;
200 writel(val, wcnss->pmu_cfg);
201
202
203 val |= WCNSS_PMU_IRIS_XO_CFG;
204 writel(val, wcnss->pmu_cfg);
205
206
207 while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
208 cpu_relax();
209
210
211 val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
212 val &= ~WCNSS_PMU_IRIS_XO_CFG;
213 writel(val, wcnss->pmu_cfg);
214
215
216 msleep(20);
217}
218
219static int wcnss_start(struct rproc *rproc)
220{
221 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
222 int ret;
223
224 mutex_lock(&wcnss->iris_lock);
225 if (!wcnss->iris) {
226 dev_err(wcnss->dev, "no iris registered\n");
227 ret = -EINVAL;
228 goto release_iris_lock;
229 }
230
231 ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
232 if (ret)
233 goto release_iris_lock;
234
235 ret = qcom_iris_enable(wcnss->iris);
236 if (ret)
237 goto disable_regulators;
238
239 wcnss_indicate_nv_download(wcnss);
240 wcnss_configure_iris(wcnss);
241
242 ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
243 if (ret) {
244 dev_err(wcnss->dev,
245 "failed to authenticate image and release reset\n");
246 goto disable_iris;
247 }
248
249 ret = wait_for_completion_timeout(&wcnss->start_done,
250 msecs_to_jiffies(5000));
251 if (wcnss->ready_irq > 0 && ret == 0) {
252
253 dev_err(wcnss->dev, "start timed out\n");
254 qcom_scm_pas_shutdown(WCNSS_PAS_ID);
255 ret = -ETIMEDOUT;
256 goto disable_iris;
257 }
258
259 ret = 0;
260
261disable_iris:
262 qcom_iris_disable(wcnss->iris);
263disable_regulators:
264 regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
265release_iris_lock:
266 mutex_unlock(&wcnss->iris_lock);
267
268 return ret;
269}
270
271static int wcnss_stop(struct rproc *rproc)
272{
273 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
274 int ret;
275
276 if (wcnss->state) {
277 qcom_smem_state_update_bits(wcnss->state,
278 BIT(wcnss->stop_bit),
279 BIT(wcnss->stop_bit));
280
281 ret = wait_for_completion_timeout(&wcnss->stop_done,
282 msecs_to_jiffies(5000));
283 if (ret == 0)
284 dev_err(wcnss->dev, "timed out on wait\n");
285
286 qcom_smem_state_update_bits(wcnss->state,
287 BIT(wcnss->stop_bit),
288 0);
289 }
290
291 ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
292 if (ret)
293 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
294
295 return ret;
296}
297
298static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len)
299{
300 struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
301 int offset;
302
303 offset = da - wcnss->mem_reloc;
304 if (offset < 0 || offset + len > wcnss->mem_size)
305 return NULL;
306
307 return wcnss->mem_region + offset;
308}
309
310static const struct rproc_ops wcnss_ops = {
311 .start = wcnss_start,
312 .stop = wcnss_stop,
313 .da_to_va = wcnss_da_to_va,
314 .parse_fw = qcom_register_dump_segments,
315 .load = wcnss_load,
316};
317
318static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
319{
320 struct qcom_wcnss *wcnss = dev;
321
322 rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
323
324 return IRQ_HANDLED;
325}
326
327static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
328{
329 struct qcom_wcnss *wcnss = dev;
330 size_t len;
331 char *msg;
332
333 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
334 if (!IS_ERR(msg) && len > 0 && msg[0])
335 dev_err(wcnss->dev, "fatal error received: %s\n", msg);
336
337 rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
338
339 return IRQ_HANDLED;
340}
341
342static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
343{
344 struct qcom_wcnss *wcnss = dev;
345
346 complete(&wcnss->start_done);
347
348 return IRQ_HANDLED;
349}
350
351static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
352{
353
354
355
356
357
358
359
360
361
362 return IRQ_HANDLED;
363}
364
365static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
366{
367 struct qcom_wcnss *wcnss = dev;
368
369 complete(&wcnss->stop_done);
370
371 return IRQ_HANDLED;
372}
373
374static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
375 const struct wcnss_vreg_info *info,
376 int num_vregs)
377{
378 struct regulator_bulk_data *bulk;
379 int ret;
380 int i;
381
382 bulk = devm_kcalloc(wcnss->dev,
383 num_vregs, sizeof(struct regulator_bulk_data),
384 GFP_KERNEL);
385 if (!bulk)
386 return -ENOMEM;
387
388 for (i = 0; i < num_vregs; i++)
389 bulk[i].supply = info[i].name;
390
391 ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
392 if (ret)
393 return ret;
394
395 for (i = 0; i < num_vregs; i++) {
396 if (info[i].max_voltage)
397 regulator_set_voltage(bulk[i].consumer,
398 info[i].min_voltage,
399 info[i].max_voltage);
400
401 if (info[i].load_uA)
402 regulator_set_load(bulk[i].consumer, info[i].load_uA);
403 }
404
405 wcnss->vregs = bulk;
406 wcnss->num_vregs = num_vregs;
407
408 return 0;
409}
410
411static int wcnss_request_irq(struct qcom_wcnss *wcnss,
412 struct platform_device *pdev,
413 const char *name,
414 bool optional,
415 irq_handler_t thread_fn)
416{
417 int ret;
418
419 ret = platform_get_irq_byname(pdev, name);
420 if (ret < 0 && optional) {
421 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
422 return 0;
423 } else if (ret < 0) {
424 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
425 return ret;
426 }
427
428 ret = devm_request_threaded_irq(&pdev->dev, ret,
429 NULL, thread_fn,
430 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
431 "wcnss", wcnss);
432 if (ret)
433 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
434
435 return ret;
436}
437
438static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
439{
440 struct device_node *node;
441 struct resource r;
442 int ret;
443
444 node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
445 if (!node) {
446 dev_err(wcnss->dev, "no memory-region specified\n");
447 return -EINVAL;
448 }
449
450 ret = of_address_to_resource(node, 0, &r);
451 if (ret)
452 return ret;
453
454 wcnss->mem_phys = wcnss->mem_reloc = r.start;
455 wcnss->mem_size = resource_size(&r);
456 wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
457 if (!wcnss->mem_region) {
458 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
459 &r.start, wcnss->mem_size);
460 return -EBUSY;
461 }
462
463 return 0;
464}
465
466static int wcnss_probe(struct platform_device *pdev)
467{
468 const struct wcnss_data *data;
469 struct qcom_wcnss *wcnss;
470 struct resource *res;
471 struct rproc *rproc;
472 void __iomem *mmio;
473 int ret;
474
475 data = of_device_get_match_data(&pdev->dev);
476
477 if (!qcom_scm_is_available())
478 return -EPROBE_DEFER;
479
480 if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
481 dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
482 return -ENXIO;
483 }
484
485 rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
486 WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
487 if (!rproc) {
488 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
489 return -ENOMEM;
490 }
491 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
492
493 wcnss = (struct qcom_wcnss *)rproc->priv;
494 wcnss->dev = &pdev->dev;
495 wcnss->rproc = rproc;
496 platform_set_drvdata(pdev, wcnss);
497
498 init_completion(&wcnss->start_done);
499 init_completion(&wcnss->stop_done);
500
501 mutex_init(&wcnss->iris_lock);
502
503 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
504 mmio = devm_ioremap_resource(&pdev->dev, res);
505 if (IS_ERR(mmio)) {
506 ret = PTR_ERR(mmio);
507 goto free_rproc;
508 };
509
510 ret = wcnss_alloc_memory_region(wcnss);
511 if (ret)
512 goto free_rproc;
513
514 wcnss->pmu_cfg = mmio + data->pmu_offset;
515 wcnss->spare_out = mmio + data->spare_offset;
516
517 ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
518 if (ret)
519 goto free_rproc;
520
521 ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
522 if (ret < 0)
523 goto free_rproc;
524 wcnss->wdog_irq = ret;
525
526 ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
527 if (ret < 0)
528 goto free_rproc;
529 wcnss->fatal_irq = ret;
530
531 ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
532 if (ret < 0)
533 goto free_rproc;
534 wcnss->ready_irq = ret;
535
536 ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
537 if (ret < 0)
538 goto free_rproc;
539 wcnss->handover_irq = ret;
540
541 ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
542 if (ret < 0)
543 goto free_rproc;
544 wcnss->stop_ack_irq = ret;
545
546 if (wcnss->stop_ack_irq) {
547 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
548 &wcnss->stop_bit);
549 if (IS_ERR(wcnss->state)) {
550 ret = PTR_ERR(wcnss->state);
551 goto free_rproc;
552 }
553 }
554
555 qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
556 wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
557 if (IS_ERR(wcnss->sysmon)) {
558 ret = PTR_ERR(wcnss->sysmon);
559 goto free_rproc;
560 }
561
562 ret = rproc_add(rproc);
563 if (ret)
564 goto free_rproc;
565
566 return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
567
568free_rproc:
569 rproc_free(rproc);
570
571 return ret;
572}
573
574static int wcnss_remove(struct platform_device *pdev)
575{
576 struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
577
578 of_platform_depopulate(&pdev->dev);
579
580 qcom_smem_state_put(wcnss->state);
581 rproc_del(wcnss->rproc);
582
583 qcom_remove_sysmon_subdev(wcnss->sysmon);
584 qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
585 rproc_free(wcnss->rproc);
586
587 return 0;
588}
589
590static const struct of_device_id wcnss_of_match[] = {
591 { .compatible = "qcom,riva-pil", &riva_data },
592 { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
593 { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
594 { },
595};
596MODULE_DEVICE_TABLE(of, wcnss_of_match);
597
598static struct platform_driver wcnss_driver = {
599 .probe = wcnss_probe,
600 .remove = wcnss_remove,
601 .driver = {
602 .name = "qcom-wcnss-pil",
603 .of_match_table = wcnss_of_match,
604 },
605};
606
607static int __init wcnss_init(void)
608{
609 int ret;
610
611 ret = platform_driver_register(&wcnss_driver);
612 if (ret)
613 return ret;
614
615 ret = platform_driver_register(&qcom_iris_driver);
616 if (ret)
617 platform_driver_unregister(&wcnss_driver);
618
619 return ret;
620}
621module_init(wcnss_init);
622
623static void __exit wcnss_exit(void)
624{
625 platform_driver_unregister(&qcom_iris_driver);
626 platform_driver_unregister(&wcnss_driver);
627}
628module_exit(wcnss_exit);
629
630MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
631MODULE_LICENSE("GPL v2");
632
