linux/drivers/scsi/isci/phy.c
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   1/*
   2 * This file is provided under a dual BSD/GPLv2 license.  When using or
   3 * redistributing this file, you may do so under either license.
   4 *
   5 * GPL LICENSE SUMMARY
   6 *
   7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of version 2 of the GNU General Public License as
  11 * published by the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 * General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21 * The full GNU General Public License is included in this distribution
  22 * in the file called LICENSE.GPL.
  23 *
  24 * BSD LICENSE
  25 *
  26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27 * All rights reserved.
  28 *
  29 * Redistribution and use in source and binary forms, with or without
  30 * modification, are permitted provided that the following conditions
  31 * are met:
  32 *
  33 *   * Redistributions of source code must retain the above copyright
  34 *     notice, this list of conditions and the following disclaimer.
  35 *   * Redistributions in binary form must reproduce the above copyright
  36 *     notice, this list of conditions and the following disclaimer in
  37 *     the documentation and/or other materials provided with the
  38 *     distribution.
  39 *   * Neither the name of Intel Corporation nor the names of its
  40 *     contributors may be used to endorse or promote products derived
  41 *     from this software without specific prior written permission.
  42 *
  43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54 */
  55
  56#include "isci.h"
  57#include "host.h"
  58#include "phy.h"
  59#include "scu_event_codes.h"
  60#include "probe_roms.h"
  61
  62#undef C
  63#define C(a) (#a)
  64static const char *phy_state_name(enum sci_phy_states state)
  65{
  66        static const char * const strings[] = PHY_STATES;
  67
  68        return strings[state];
  69}
  70#undef C
  71
  72/* Maximum arbitration wait time in micro-seconds */
  73#define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME  (700)
  74
  75enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy)
  76{
  77        return iphy->max_negotiated_speed;
  78}
  79
  80static struct isci_host *phy_to_host(struct isci_phy *iphy)
  81{
  82        struct isci_phy *table = iphy - iphy->phy_index;
  83        struct isci_host *ihost = container_of(table, typeof(*ihost), phys[0]);
  84
  85        return ihost;
  86}
  87
  88static struct device *sciphy_to_dev(struct isci_phy *iphy)
  89{
  90        return &phy_to_host(iphy)->pdev->dev;
  91}
  92
  93static enum sci_status
  94sci_phy_transport_layer_initialization(struct isci_phy *iphy,
  95                                       struct scu_transport_layer_registers __iomem *reg)
  96{
  97        u32 tl_control;
  98
  99        iphy->transport_layer_registers = reg;
 100
 101        writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
 102                &iphy->transport_layer_registers->stp_rni);
 103
 104        /*
 105         * Hardware team recommends that we enable the STP prefetch for all
 106         * transports
 107         */
 108        tl_control = readl(&iphy->transport_layer_registers->control);
 109        tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
 110        writel(tl_control, &iphy->transport_layer_registers->control);
 111
 112        return SCI_SUCCESS;
 113}
 114
 115static enum sci_status
 116sci_phy_link_layer_initialization(struct isci_phy *iphy,
 117                                  struct scu_link_layer_registers __iomem *llr)
 118{
 119        struct isci_host *ihost = iphy->owning_port->owning_controller;
 120        struct sci_phy_user_params *phy_user;
 121        struct sci_phy_oem_params *phy_oem;
 122        int phy_idx = iphy->phy_index;
 123        struct sci_phy_cap phy_cap;
 124        u32 phy_configuration;
 125        u32 parity_check = 0;
 126        u32 parity_count = 0;
 127        u32 llctl, link_rate;
 128        u32 clksm_value = 0;
 129        u32 sp_timeouts = 0;
 130
 131        phy_user = &ihost->user_parameters.phys[phy_idx];
 132        phy_oem = &ihost->oem_parameters.phys[phy_idx];
 133        iphy->link_layer_registers = llr;
 134
 135        /* Set our IDENTIFY frame data */
 136        #define SCI_END_DEVICE 0x01
 137
 138        writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
 139               SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
 140               SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
 141               SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
 142               SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
 143               &llr->transmit_identification);
 144
 145        /* Write the device SAS Address */
 146        writel(0xFEDCBA98, &llr->sas_device_name_high);
 147        writel(phy_idx, &llr->sas_device_name_low);
 148
 149        /* Write the source SAS Address */
 150        writel(phy_oem->sas_address.high, &llr->source_sas_address_high);
 151        writel(phy_oem->sas_address.low, &llr->source_sas_address_low);
 152
 153        /* Clear and Set the PHY Identifier */
 154        writel(0, &llr->identify_frame_phy_id);
 155        writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id);
 156
 157        /* Change the initial state of the phy configuration register */
 158        phy_configuration = readl(&llr->phy_configuration);
 159
 160        /* Hold OOB state machine in reset */
 161        phy_configuration |=  SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 162        writel(phy_configuration, &llr->phy_configuration);
 163
 164        /* Configure the SNW capabilities */
 165        phy_cap.all = 0;
 166        phy_cap.start = 1;
 167        phy_cap.gen3_no_ssc = 1;
 168        phy_cap.gen2_no_ssc = 1;
 169        phy_cap.gen1_no_ssc = 1;
 170        if (ihost->oem_parameters.controller.do_enable_ssc) {
 171                struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
 172                struct scu_afe_transceiver __iomem *xcvr = &afe->scu_afe_xcvr[phy_idx];
 173                struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
 174                bool en_sas = false;
 175                bool en_sata = false;
 176                u32 sas_type = 0;
 177                u32 sata_spread = 0x2;
 178                u32 sas_spread = 0x2;
 179
 180                phy_cap.gen3_ssc = 1;
 181                phy_cap.gen2_ssc = 1;
 182                phy_cap.gen1_ssc = 1;
 183
 184                if (pci_info->orom->hdr.version < ISCI_ROM_VER_1_1)
 185                        en_sas = en_sata = true;
 186                else {
 187                        sata_spread = ihost->oem_parameters.controller.ssc_sata_tx_spread_level;
 188                        sas_spread = ihost->oem_parameters.controller.ssc_sas_tx_spread_level;
 189
 190                        if (sata_spread)
 191                                en_sata = true;
 192
 193                        if (sas_spread) {
 194                                en_sas = true;
 195                                sas_type = ihost->oem_parameters.controller.ssc_sas_tx_type;
 196                        }
 197
 198                }
 199
 200                if (en_sas) {
 201                        u32 reg;
 202
 203                        reg = readl(&xcvr->afe_xcvr_control0);
 204                        reg |= (0x00100000 | (sas_type << 19));
 205                        writel(reg, &xcvr->afe_xcvr_control0);
 206
 207                        reg = readl(&xcvr->afe_tx_ssc_control);
 208                        reg |= sas_spread << 8;
 209                        writel(reg, &xcvr->afe_tx_ssc_control);
 210                }
 211
 212                if (en_sata) {
 213                        u32 reg;
 214
 215                        reg = readl(&xcvr->afe_tx_ssc_control);
 216                        reg |= sata_spread;
 217                        writel(reg, &xcvr->afe_tx_ssc_control);
 218
 219                        reg = readl(&llr->stp_control);
 220                        reg |= 1 << 12;
 221                        writel(reg, &llr->stp_control);
 222                }
 223        }
 224
 225        /* The SAS specification indicates that the phy_capabilities that
 226         * are transmitted shall have an even parity.  Calculate the parity.
 227         */
 228        parity_check = phy_cap.all;
 229        while (parity_check != 0) {
 230                if (parity_check & 0x1)
 231                        parity_count++;
 232                parity_check >>= 1;
 233        }
 234
 235        /* If parity indicates there are an odd number of bits set, then
 236         * set the parity bit to 1 in the phy capabilities.
 237         */
 238        if ((parity_count % 2) != 0)
 239                phy_cap.parity = 1;
 240
 241        writel(phy_cap.all, &llr->phy_capabilities);
 242
 243        /* Set the enable spinup period but disable the ability to send
 244         * notify enable spinup
 245         */
 246        writel(SCU_ENSPINUP_GEN_VAL(COUNT,
 247                        phy_user->notify_enable_spin_up_insertion_frequency),
 248                &llr->notify_enable_spinup_control);
 249
 250        /* Write the ALIGN Insertion Ferequency for connected phy and
 251         * inpendent of connected state
 252         */
 253        clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
 254                        phy_user->in_connection_align_insertion_frequency);
 255
 256        clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
 257                        phy_user->align_insertion_frequency);
 258
 259        writel(clksm_value, &llr->clock_skew_management);
 260
 261        if (is_c0(ihost->pdev) || is_c1(ihost->pdev)) {
 262                writel(0x04210400, &llr->afe_lookup_table_control);
 263                writel(0x020A7C05, &llr->sas_primitive_timeout);
 264        } else
 265                writel(0x02108421, &llr->afe_lookup_table_control);
 266
 267        llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
 268                (u8)ihost->user_parameters.no_outbound_task_timeout);
 269
 270        switch (phy_user->max_speed_generation) {
 271        case SCIC_SDS_PARM_GEN3_SPEED:
 272                link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
 273                break;
 274        case SCIC_SDS_PARM_GEN2_SPEED:
 275                link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
 276                break;
 277        default:
 278                link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
 279                break;
 280        }
 281        llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
 282        writel(llctl, &llr->link_layer_control);
 283
 284        sp_timeouts = readl(&llr->sas_phy_timeouts);
 285
 286        /* Clear the default 0x36 (54us) RATE_CHANGE timeout value. */
 287        sp_timeouts &= ~SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0xFF);
 288
 289        /* Set RATE_CHANGE timeout value to 0x3B (59us).  This ensures SCU can
 290         * lock with 3Gb drive when SCU max rate is set to 1.5Gb.
 291         */
 292        sp_timeouts |= SCU_SAS_PHYTOV_GEN_VAL(RATE_CHANGE, 0x3B);
 293
 294        writel(sp_timeouts, &llr->sas_phy_timeouts);
 295
 296        if (is_a2(ihost->pdev)) {
 297                /* Program the max ARB time for the PHY to 700us so we
 298                 * inter-operate with the PMC expander which shuts down
 299                 * PHYs if the expander PHY generates too many breaks.
 300                 * This time value will guarantee that the initiator PHY
 301                 * will generate the break.
 302                 */
 303                writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
 304                       &llr->maximum_arbitration_wait_timer_timeout);
 305        }
 306
 307        /* Disable link layer hang detection, rely on the OS timeout for
 308         * I/O timeouts.
 309         */
 310        writel(0, &llr->link_layer_hang_detection_timeout);
 311
 312        /* We can exit the initial state to the stopped state */
 313        sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 314
 315        return SCI_SUCCESS;
 316}
 317
 318static void phy_sata_timeout(struct timer_list *t)
 319{
 320        struct sci_timer *tmr = from_timer(tmr, t, timer);
 321        struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer);
 322        struct isci_host *ihost = iphy->owning_port->owning_controller;
 323        unsigned long flags;
 324
 325        spin_lock_irqsave(&ihost->scic_lock, flags);
 326
 327        if (tmr->cancel)
 328                goto done;
 329
 330        dev_dbg(sciphy_to_dev(iphy),
 331                 "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
 332                 "timeout.\n",
 333                 __func__,
 334                 iphy);
 335
 336        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 337done:
 338        spin_unlock_irqrestore(&ihost->scic_lock, flags);
 339}
 340
 341/**
 342 * This method returns the port currently containing this phy. If the phy is
 343 *    currently contained by the dummy port, then the phy is considered to not
 344 *    be part of a port.
 345 * @sci_phy: This parameter specifies the phy for which to retrieve the
 346 *    containing port.
 347 *
 348 * This method returns a handle to a port that contains the supplied phy.
 349 * NULL This value is returned if the phy is not part of a real
 350 * port (i.e. it's contained in the dummy port). !NULL All other
 351 * values indicate a handle/pointer to the port containing the phy.
 352 */
 353struct isci_port *phy_get_non_dummy_port(struct isci_phy *iphy)
 354{
 355        struct isci_port *iport = iphy->owning_port;
 356
 357        if (iport->physical_port_index == SCIC_SDS_DUMMY_PORT)
 358                return NULL;
 359
 360        return iphy->owning_port;
 361}
 362
 363/**
 364 * This method will assign a port to the phy object.
 365 * @out]: iphy This parameter specifies the phy for which to assign a port
 366 *    object.
 367 *
 368 *
 369 */
 370void sci_phy_set_port(
 371        struct isci_phy *iphy,
 372        struct isci_port *iport)
 373{
 374        iphy->owning_port = iport;
 375
 376        if (iphy->bcn_received_while_port_unassigned) {
 377                iphy->bcn_received_while_port_unassigned = false;
 378                sci_port_broadcast_change_received(iphy->owning_port, iphy);
 379        }
 380}
 381
 382enum sci_status sci_phy_initialize(struct isci_phy *iphy,
 383                                   struct scu_transport_layer_registers __iomem *tl,
 384                                   struct scu_link_layer_registers __iomem *ll)
 385{
 386        /* Perfrom the initialization of the TL hardware */
 387        sci_phy_transport_layer_initialization(iphy, tl);
 388
 389        /* Perofrm the initialization of the PE hardware */
 390        sci_phy_link_layer_initialization(iphy, ll);
 391
 392        /* There is nothing that needs to be done in this state just
 393         * transition to the stopped state
 394         */
 395        sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 396
 397        return SCI_SUCCESS;
 398}
 399
 400/**
 401 * This method assigns the direct attached device ID for this phy.
 402 *
 403 * @iphy The phy for which the direct attached device id is to
 404 *       be assigned.
 405 * @device_id The direct attached device ID to assign to the phy.
 406 *       This will either be the RNi for the device or an invalid RNi if there
 407 *       is no current device assigned to the phy.
 408 */
 409void sci_phy_setup_transport(struct isci_phy *iphy, u32 device_id)
 410{
 411        u32 tl_control;
 412
 413        writel(device_id, &iphy->transport_layer_registers->stp_rni);
 414
 415        /*
 416         * The read should guarantee that the first write gets posted
 417         * before the next write
 418         */
 419        tl_control = readl(&iphy->transport_layer_registers->control);
 420        tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
 421        writel(tl_control, &iphy->transport_layer_registers->control);
 422}
 423
 424static void sci_phy_suspend(struct isci_phy *iphy)
 425{
 426        u32 scu_sas_pcfg_value;
 427
 428        scu_sas_pcfg_value =
 429                readl(&iphy->link_layer_registers->phy_configuration);
 430        scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
 431        writel(scu_sas_pcfg_value,
 432                &iphy->link_layer_registers->phy_configuration);
 433
 434        sci_phy_setup_transport(iphy, SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
 435}
 436
 437void sci_phy_resume(struct isci_phy *iphy)
 438{
 439        u32 scu_sas_pcfg_value;
 440
 441        scu_sas_pcfg_value =
 442                readl(&iphy->link_layer_registers->phy_configuration);
 443        scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
 444        writel(scu_sas_pcfg_value,
 445                &iphy->link_layer_registers->phy_configuration);
 446}
 447
 448void sci_phy_get_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
 449{
 450        sas->high = readl(&iphy->link_layer_registers->source_sas_address_high);
 451        sas->low = readl(&iphy->link_layer_registers->source_sas_address_low);
 452}
 453
 454void sci_phy_get_attached_sas_address(struct isci_phy *iphy, struct sci_sas_address *sas)
 455{
 456        struct sas_identify_frame *iaf;
 457
 458        iaf = &iphy->frame_rcvd.iaf;
 459        memcpy(sas, iaf->sas_addr, SAS_ADDR_SIZE);
 460}
 461
 462void sci_phy_get_protocols(struct isci_phy *iphy, struct sci_phy_proto *proto)
 463{
 464        proto->all = readl(&iphy->link_layer_registers->transmit_identification);
 465}
 466
 467enum sci_status sci_phy_start(struct isci_phy *iphy)
 468{
 469        enum sci_phy_states state = iphy->sm.current_state_id;
 470
 471        if (state != SCI_PHY_STOPPED) {
 472                dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 473                        __func__, phy_state_name(state));
 474                return SCI_FAILURE_INVALID_STATE;
 475        }
 476
 477        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 478        return SCI_SUCCESS;
 479}
 480
 481enum sci_status sci_phy_stop(struct isci_phy *iphy)
 482{
 483        enum sci_phy_states state = iphy->sm.current_state_id;
 484
 485        switch (state) {
 486        case SCI_PHY_SUB_INITIAL:
 487        case SCI_PHY_SUB_AWAIT_OSSP_EN:
 488        case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 489        case SCI_PHY_SUB_AWAIT_SAS_POWER:
 490        case SCI_PHY_SUB_AWAIT_SATA_POWER:
 491        case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 492        case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 493        case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 494        case SCI_PHY_SUB_FINAL:
 495        case SCI_PHY_READY:
 496                break;
 497        default:
 498                dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 499                        __func__, phy_state_name(state));
 500                return SCI_FAILURE_INVALID_STATE;
 501        }
 502
 503        sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 504        return SCI_SUCCESS;
 505}
 506
 507enum sci_status sci_phy_reset(struct isci_phy *iphy)
 508{
 509        enum sci_phy_states state = iphy->sm.current_state_id;
 510
 511        if (state != SCI_PHY_READY) {
 512                dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 513                        __func__, phy_state_name(state));
 514                return SCI_FAILURE_INVALID_STATE;
 515        }
 516
 517        sci_change_state(&iphy->sm, SCI_PHY_RESETTING);
 518        return SCI_SUCCESS;
 519}
 520
 521enum sci_status sci_phy_consume_power_handler(struct isci_phy *iphy)
 522{
 523        enum sci_phy_states state = iphy->sm.current_state_id;
 524
 525        switch (state) {
 526        case SCI_PHY_SUB_AWAIT_SAS_POWER: {
 527                u32 enable_spinup;
 528
 529                enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
 530                enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
 531                writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control);
 532
 533                /* Change state to the final state this substate machine has run to completion */
 534                sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
 535
 536                return SCI_SUCCESS;
 537        }
 538        case SCI_PHY_SUB_AWAIT_SATA_POWER: {
 539                u32 scu_sas_pcfg_value;
 540
 541                /* Release the spinup hold state and reset the OOB state machine */
 542                scu_sas_pcfg_value =
 543                        readl(&iphy->link_layer_registers->phy_configuration);
 544                scu_sas_pcfg_value &=
 545                        ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
 546                scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 547                writel(scu_sas_pcfg_value,
 548                        &iphy->link_layer_registers->phy_configuration);
 549
 550                /* Now restart the OOB operation */
 551                scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 552                scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
 553                writel(scu_sas_pcfg_value,
 554                        &iphy->link_layer_registers->phy_configuration);
 555
 556                /* Change state to the final state this substate machine has run to completion */
 557                sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
 558
 559                return SCI_SUCCESS;
 560        }
 561        default:
 562                dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 563                        __func__, phy_state_name(state));
 564                return SCI_FAILURE_INVALID_STATE;
 565        }
 566}
 567
 568static void sci_phy_start_sas_link_training(struct isci_phy *iphy)
 569{
 570        /* continue the link training for the phy as if it were a SAS PHY
 571         * instead of a SATA PHY. This is done because the completion queue had a SAS
 572         * PHY DETECTED event when the state machine was expecting a SATA PHY event.
 573         */
 574        u32 phy_control;
 575
 576        phy_control = readl(&iphy->link_layer_registers->phy_configuration);
 577        phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
 578        writel(phy_control,
 579               &iphy->link_layer_registers->phy_configuration);
 580
 581        sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
 582
 583        iphy->protocol = SAS_PROTOCOL_SSP;
 584}
 585
 586static void sci_phy_start_sata_link_training(struct isci_phy *iphy)
 587{
 588        /* This method continues the link training for the phy as if it were a SATA PHY
 589         * instead of a SAS PHY.  This is done because the completion queue had a SATA
 590         * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
 591         */
 592        sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
 593
 594        iphy->protocol = SAS_PROTOCOL_SATA;
 595}
 596
 597/**
 598 * sci_phy_complete_link_training - perform processing common to
 599 *    all protocols upon completion of link training.
 600 * @sci_phy: This parameter specifies the phy object for which link training
 601 *    has completed.
 602 * @max_link_rate: This parameter specifies the maximum link rate to be
 603 *    associated with this phy.
 604 * @next_state: This parameter specifies the next state for the phy's starting
 605 *    sub-state machine.
 606 *
 607 */
 608static void sci_phy_complete_link_training(struct isci_phy *iphy,
 609                                           enum sas_linkrate max_link_rate,
 610                                           u32 next_state)
 611{
 612        iphy->max_negotiated_speed = max_link_rate;
 613
 614        sci_change_state(&iphy->sm, next_state);
 615}
 616
 617static const char *phy_event_name(u32 event_code)
 618{
 619        switch (scu_get_event_code(event_code)) {
 620        case SCU_EVENT_PORT_SELECTOR_DETECTED:
 621                return "port selector";
 622        case SCU_EVENT_SENT_PORT_SELECTION:
 623                return "port selection";
 624        case SCU_EVENT_HARD_RESET_TRANSMITTED:
 625                return "tx hard reset";
 626        case SCU_EVENT_HARD_RESET_RECEIVED:
 627                return "rx hard reset";
 628        case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
 629                return "identify timeout";
 630        case SCU_EVENT_LINK_FAILURE:
 631                return "link fail";
 632        case SCU_EVENT_SATA_SPINUP_HOLD:
 633                return "sata spinup hold";
 634        case SCU_EVENT_SAS_15_SSC:
 635        case SCU_EVENT_SAS_15:
 636                return "sas 1.5";
 637        case SCU_EVENT_SAS_30_SSC:
 638        case SCU_EVENT_SAS_30:
 639                return "sas 3.0";
 640        case SCU_EVENT_SAS_60_SSC:
 641        case SCU_EVENT_SAS_60:
 642                return "sas 6.0";
 643        case SCU_EVENT_SATA_15_SSC:
 644        case SCU_EVENT_SATA_15:
 645                return "sata 1.5";
 646        case SCU_EVENT_SATA_30_SSC:
 647        case SCU_EVENT_SATA_30:
 648                return "sata 3.0";
 649        case SCU_EVENT_SATA_60_SSC:
 650        case SCU_EVENT_SATA_60:
 651                return "sata 6.0";
 652        case SCU_EVENT_SAS_PHY_DETECTED:
 653                return "sas detect";
 654        case SCU_EVENT_SATA_PHY_DETECTED:
 655                return "sata detect";
 656        default:
 657                return "unknown";
 658        }
 659}
 660
 661#define phy_event_dbg(iphy, state, code) \
 662        dev_dbg(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \
 663                phy_to_host(iphy)->id, iphy->phy_index, \
 664                phy_state_name(state), phy_event_name(code), code)
 665
 666#define phy_event_warn(iphy, state, code) \
 667        dev_warn(sciphy_to_dev(iphy), "phy-%d:%d: %s event: %s (%x)\n", \
 668                phy_to_host(iphy)->id, iphy->phy_index, \
 669                phy_state_name(state), phy_event_name(code), code)
 670
 671
 672static void scu_link_layer_set_txcomsas_timeout(struct isci_phy *iphy, u32 timeout)
 673{
 674        u32 val;
 675
 676        /* Extend timeout */
 677        val = readl(&iphy->link_layer_registers->transmit_comsas_signal);
 678        val &= ~SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_MASK);
 679        val |= SCU_SAS_LLTXCOMSAS_GEN_VAL(NEGTIME, timeout);
 680
 681        writel(val, &iphy->link_layer_registers->transmit_comsas_signal);
 682}
 683
 684enum sci_status sci_phy_event_handler(struct isci_phy *iphy, u32 event_code)
 685{
 686        enum sci_phy_states state = iphy->sm.current_state_id;
 687
 688        switch (state) {
 689        case SCI_PHY_SUB_AWAIT_OSSP_EN:
 690                switch (scu_get_event_code(event_code)) {
 691                case SCU_EVENT_SAS_PHY_DETECTED:
 692                        sci_phy_start_sas_link_training(iphy);
 693                        iphy->is_in_link_training = true;
 694                        break;
 695                case SCU_EVENT_SATA_SPINUP_HOLD:
 696                        sci_phy_start_sata_link_training(iphy);
 697                        iphy->is_in_link_training = true;
 698                        break;
 699                case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
 700                       /* Extend timeout value */
 701                       scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED);
 702
 703                       /* Start the oob/sn state machine over again */
 704                       sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 705                       break;
 706                default:
 707                        phy_event_dbg(iphy, state, event_code);
 708                        return SCI_FAILURE;
 709                }
 710                return SCI_SUCCESS;
 711        case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 712                switch (scu_get_event_code(event_code)) {
 713                case SCU_EVENT_SAS_PHY_DETECTED:
 714                        /*
 715                         * Why is this being reported again by the controller?
 716                         * We would re-enter this state so just stay here */
 717                        break;
 718                case SCU_EVENT_SAS_15:
 719                case SCU_EVENT_SAS_15_SSC:
 720                        sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
 721                                                       SCI_PHY_SUB_AWAIT_IAF_UF);
 722                        break;
 723                case SCU_EVENT_SAS_30:
 724                case SCU_EVENT_SAS_30_SSC:
 725                        sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
 726                                                       SCI_PHY_SUB_AWAIT_IAF_UF);
 727                        break;
 728                case SCU_EVENT_SAS_60:
 729                case SCU_EVENT_SAS_60_SSC:
 730                        sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
 731                                                       SCI_PHY_SUB_AWAIT_IAF_UF);
 732                        break;
 733                case SCU_EVENT_SATA_SPINUP_HOLD:
 734                        /*
 735                         * We were doing SAS PHY link training and received a SATA PHY event
 736                         * continue OOB/SN as if this were a SATA PHY */
 737                        sci_phy_start_sata_link_training(iphy);
 738                        break;
 739                case SCU_EVENT_LINK_FAILURE:
 740                        /* Change the timeout value to default */
 741                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 742
 743                        /* Link failure change state back to the starting state */
 744                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 745                        break;
 746                case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
 747                       /* Extend the timeout value */
 748                       scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED);
 749
 750                       /* Start the oob/sn state machine over again */
 751                       sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 752                       break;
 753                default:
 754                        phy_event_warn(iphy, state, event_code);
 755                        return SCI_FAILURE;
 756                        break;
 757                }
 758                return SCI_SUCCESS;
 759        case SCI_PHY_SUB_AWAIT_IAF_UF:
 760                switch (scu_get_event_code(event_code)) {
 761                case SCU_EVENT_SAS_PHY_DETECTED:
 762                        /* Backup the state machine */
 763                        sci_phy_start_sas_link_training(iphy);
 764                        break;
 765                case SCU_EVENT_SATA_SPINUP_HOLD:
 766                        /* We were doing SAS PHY link training and received a
 767                         * SATA PHY event continue OOB/SN as if this were a
 768                         * SATA PHY
 769                         */
 770                        sci_phy_start_sata_link_training(iphy);
 771                        break;
 772                case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
 773                        /* Extend the timeout value */
 774                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_EXTENDED);
 775
 776                        /* Start the oob/sn state machine over again */
 777                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 778                        break;
 779                case SCU_EVENT_LINK_FAILURE:
 780                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 781                        fallthrough;
 782                case SCU_EVENT_HARD_RESET_RECEIVED:
 783                        /* Start the oob/sn state machine over again */
 784                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 785                        break;
 786                default:
 787                        phy_event_warn(iphy, state, event_code);
 788                        return SCI_FAILURE;
 789                }
 790                return SCI_SUCCESS;
 791        case SCI_PHY_SUB_AWAIT_SAS_POWER:
 792                switch (scu_get_event_code(event_code)) {
 793                case SCU_EVENT_LINK_FAILURE:
 794                        /* Change the timeout value to default */
 795                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 796
 797                        /* Link failure change state back to the starting state */
 798                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 799                        break;
 800                default:
 801                        phy_event_warn(iphy, state, event_code);
 802                        return SCI_FAILURE;
 803                }
 804                return SCI_SUCCESS;
 805        case SCI_PHY_SUB_AWAIT_SATA_POWER:
 806                switch (scu_get_event_code(event_code)) {
 807                case SCU_EVENT_LINK_FAILURE:
 808                        /* Change the timeout value to default */
 809                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 810
 811                        /* Link failure change state back to the starting state */
 812                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 813                        break;
 814                case SCU_EVENT_SATA_SPINUP_HOLD:
 815                        /* These events are received every 10ms and are
 816                         * expected while in this state
 817                         */
 818                        break;
 819
 820                case SCU_EVENT_SAS_PHY_DETECTED:
 821                        /* There has been a change in the phy type before OOB/SN for the
 822                         * SATA finished start down the SAS link traning path.
 823                         */
 824                        sci_phy_start_sas_link_training(iphy);
 825                        break;
 826
 827                default:
 828                        phy_event_warn(iphy, state, event_code);
 829                        return SCI_FAILURE;
 830                }
 831                return SCI_SUCCESS;
 832        case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 833                switch (scu_get_event_code(event_code)) {
 834                case SCU_EVENT_LINK_FAILURE:
 835                        /* Change the timeout value to default */
 836                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 837
 838                        /* Link failure change state back to the starting state */
 839                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 840                        break;
 841                case SCU_EVENT_SATA_SPINUP_HOLD:
 842                        /* These events might be received since we dont know how many may be in
 843                         * the completion queue while waiting for power
 844                         */
 845                        break;
 846                case SCU_EVENT_SATA_PHY_DETECTED:
 847                        iphy->protocol = SAS_PROTOCOL_SATA;
 848
 849                        /* We have received the SATA PHY notification change state */
 850                        sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
 851                        break;
 852                case SCU_EVENT_SAS_PHY_DETECTED:
 853                        /* There has been a change in the phy type before OOB/SN for the
 854                         * SATA finished start down the SAS link traning path.
 855                         */
 856                        sci_phy_start_sas_link_training(iphy);
 857                        break;
 858                default:
 859                        phy_event_warn(iphy, state, event_code);
 860                        return SCI_FAILURE;
 861                }
 862                return SCI_SUCCESS;
 863        case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 864                switch (scu_get_event_code(event_code)) {
 865                case SCU_EVENT_SATA_PHY_DETECTED:
 866                        /*
 867                         * The hardware reports multiple SATA PHY detected events
 868                         * ignore the extras */
 869                        break;
 870                case SCU_EVENT_SATA_15:
 871                case SCU_EVENT_SATA_15_SSC:
 872                        sci_phy_complete_link_training(iphy, SAS_LINK_RATE_1_5_GBPS,
 873                                                       SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 874                        break;
 875                case SCU_EVENT_SATA_30:
 876                case SCU_EVENT_SATA_30_SSC:
 877                        sci_phy_complete_link_training(iphy, SAS_LINK_RATE_3_0_GBPS,
 878                                                       SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 879                        break;
 880                case SCU_EVENT_SATA_60:
 881                case SCU_EVENT_SATA_60_SSC:
 882                        sci_phy_complete_link_training(iphy, SAS_LINK_RATE_6_0_GBPS,
 883                                                       SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 884                        break;
 885                case SCU_EVENT_LINK_FAILURE:
 886                        /* Change the timeout value to default */
 887                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 888
 889                        /* Link failure change state back to the starting state */
 890                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 891                        break;
 892                case SCU_EVENT_SAS_PHY_DETECTED:
 893                        /*
 894                         * There has been a change in the phy type before OOB/SN for the
 895                         * SATA finished start down the SAS link traning path. */
 896                        sci_phy_start_sas_link_training(iphy);
 897                        break;
 898                default:
 899                        phy_event_warn(iphy, state, event_code);
 900                        return SCI_FAILURE;
 901                }
 902
 903                return SCI_SUCCESS;
 904        case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 905                switch (scu_get_event_code(event_code)) {
 906                case SCU_EVENT_SATA_PHY_DETECTED:
 907                        /* Backup the state machine */
 908                        sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
 909                        break;
 910
 911                case SCU_EVENT_LINK_FAILURE:
 912                        /* Change the timeout value to default */
 913                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 914
 915                        /* Link failure change state back to the starting state */
 916                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 917                        break;
 918
 919                default:
 920                        phy_event_warn(iphy, state, event_code);
 921                        return SCI_FAILURE;
 922                }
 923                return SCI_SUCCESS;
 924        case SCI_PHY_READY:
 925                switch (scu_get_event_code(event_code)) {
 926                case SCU_EVENT_LINK_FAILURE:
 927                        /* Set default timeout */
 928                        scu_link_layer_set_txcomsas_timeout(iphy, SCU_SAS_LINK_LAYER_TXCOMSAS_NEGTIME_DEFAULT);
 929
 930                        /* Link failure change state back to the starting state */
 931                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 932                        break;
 933                case SCU_EVENT_BROADCAST_CHANGE:
 934                case SCU_EVENT_BROADCAST_SES:
 935                case SCU_EVENT_BROADCAST_RESERVED0:
 936                case SCU_EVENT_BROADCAST_RESERVED1:
 937                case SCU_EVENT_BROADCAST_EXPANDER:
 938                case SCU_EVENT_BROADCAST_AEN:
 939                        /* Broadcast change received. Notify the port. */
 940                        if (phy_get_non_dummy_port(iphy) != NULL)
 941                                sci_port_broadcast_change_received(iphy->owning_port, iphy);
 942                        else
 943                                iphy->bcn_received_while_port_unassigned = true;
 944                        break;
 945                case SCU_EVENT_BROADCAST_RESERVED3:
 946                case SCU_EVENT_BROADCAST_RESERVED4:
 947                default:
 948                        phy_event_warn(iphy, state, event_code);
 949                        return SCI_FAILURE_INVALID_STATE;
 950                }
 951                return SCI_SUCCESS;
 952        case SCI_PHY_RESETTING:
 953                switch (scu_get_event_code(event_code)) {
 954                case SCU_EVENT_HARD_RESET_TRANSMITTED:
 955                        /* Link failure change state back to the starting state */
 956                        sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 957                        break;
 958                default:
 959                        phy_event_warn(iphy, state, event_code);
 960                        return SCI_FAILURE_INVALID_STATE;
 961                        break;
 962                }
 963                return SCI_SUCCESS;
 964        default:
 965                dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
 966                        __func__, phy_state_name(state));
 967                return SCI_FAILURE_INVALID_STATE;
 968        }
 969}
 970
 971enum sci_status sci_phy_frame_handler(struct isci_phy *iphy, u32 frame_index)
 972{
 973        enum sci_phy_states state = iphy->sm.current_state_id;
 974        struct isci_host *ihost = iphy->owning_port->owning_controller;
 975        enum sci_status result;
 976        unsigned long flags;
 977
 978        switch (state) {
 979        case SCI_PHY_SUB_AWAIT_IAF_UF: {
 980                u32 *frame_words;
 981                struct sas_identify_frame iaf;
 982
 983                result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
 984                                                                  frame_index,
 985                                                                  (void **)&frame_words);
 986
 987                if (result != SCI_SUCCESS)
 988                        return result;
 989
 990                sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
 991                if (iaf.frame_type == 0) {
 992                        u32 state;
 993
 994                        spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
 995                        memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
 996                        spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
 997                        if (iaf.smp_tport) {
 998                                /* We got the IAF for an expander PHY go to the final
 999                                 * state since there are no power requirements for
1000                                 * expander phys.
1001                                 */
1002                                state = SCI_PHY_SUB_FINAL;
1003                        } else {
1004                                /* We got the IAF we can now go to the await spinup
1005                                 * semaphore state
1006                                 */
1007                                state = SCI_PHY_SUB_AWAIT_SAS_POWER;
1008                        }
1009                        sci_change_state(&iphy->sm, state);
1010                        result = SCI_SUCCESS;
1011                } else
1012                        dev_warn(sciphy_to_dev(iphy),
1013                                "%s: PHY starting substate machine received "
1014                                "unexpected frame id %x\n",
1015                                __func__, frame_index);
1016
1017                sci_controller_release_frame(ihost, frame_index);
1018                return result;
1019        }
1020        case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
1021                struct dev_to_host_fis *frame_header;
1022                u32 *fis_frame_data;
1023
1024                result = sci_unsolicited_frame_control_get_header(&ihost->uf_control,
1025                                                                  frame_index,
1026                                                                  (void **)&frame_header);
1027
1028                if (result != SCI_SUCCESS)
1029                        return result;
1030
1031                if ((frame_header->fis_type == FIS_REGD2H) &&
1032                    !(frame_header->status & ATA_BUSY)) {
1033                        sci_unsolicited_frame_control_get_buffer(&ihost->uf_control,
1034                                                                 frame_index,
1035                                                                 (void **)&fis_frame_data);
1036
1037                        spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
1038                        sci_controller_copy_sata_response(&iphy->frame_rcvd.fis,
1039                                                          frame_header,
1040                                                          fis_frame_data);
1041                        spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
1042
1043                        /* got IAF we can now go to the await spinup semaphore state */
1044                        sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
1045
1046                        result = SCI_SUCCESS;
1047                } else
1048                        dev_warn(sciphy_to_dev(iphy),
1049                                 "%s: PHY starting substate machine received "
1050                                 "unexpected frame id %x\n",
1051                                 __func__, frame_index);
1052
1053                /* Regardless of the result we are done with this frame with it */
1054                sci_controller_release_frame(ihost, frame_index);
1055
1056                return result;
1057        }
1058        default:
1059                dev_dbg(sciphy_to_dev(iphy), "%s: in wrong state: %s\n",
1060                        __func__, phy_state_name(state));
1061                return SCI_FAILURE_INVALID_STATE;
1062        }
1063
1064}
1065
1066static void sci_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
1067{
1068        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1069
1070        /* This is just an temporary state go off to the starting state */
1071        sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
1072}
1073
1074static void sci_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
1075{
1076        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1077        struct isci_host *ihost = iphy->owning_port->owning_controller;
1078
1079        sci_controller_power_control_queue_insert(ihost, iphy);
1080}
1081
1082static void sci_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
1083{
1084        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1085        struct isci_host *ihost = iphy->owning_port->owning_controller;
1086
1087        sci_controller_power_control_queue_remove(ihost, iphy);
1088}
1089
1090static void sci_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
1091{
1092        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1093        struct isci_host *ihost = iphy->owning_port->owning_controller;
1094
1095        sci_controller_power_control_queue_insert(ihost, iphy);
1096}
1097
1098static void sci_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
1099{
1100        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1101        struct isci_host *ihost = iphy->owning_port->owning_controller;
1102
1103        sci_controller_power_control_queue_remove(ihost, iphy);
1104}
1105
1106static void sci_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
1107{
1108        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1109
1110        sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1111}
1112
1113static void sci_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
1114{
1115        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1116
1117        sci_del_timer(&iphy->sata_timer);
1118}
1119
1120static void sci_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
1121{
1122        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1123
1124        sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1125}
1126
1127static void sci_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
1128{
1129        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1130
1131        sci_del_timer(&iphy->sata_timer);
1132}
1133
1134static void sci_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
1135{
1136        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1137
1138        if (sci_port_link_detected(iphy->owning_port, iphy)) {
1139
1140                /*
1141                 * Clear the PE suspend condition so we can actually
1142                 * receive SIG FIS
1143                 * The hardware will not respond to the XRDY until the PE
1144                 * suspend condition is cleared.
1145                 */
1146                sci_phy_resume(iphy);
1147
1148                sci_mod_timer(&iphy->sata_timer,
1149                              SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
1150        } else
1151                iphy->is_in_link_training = false;
1152}
1153
1154static void sci_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
1155{
1156        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1157
1158        sci_del_timer(&iphy->sata_timer);
1159}
1160
1161static void sci_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1162{
1163        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1164
1165        /* State machine has run to completion so exit out and change
1166         * the base state machine to the ready state
1167         */
1168        sci_change_state(&iphy->sm, SCI_PHY_READY);
1169}
1170
1171/**
1172 *
1173 * @sci_phy: This is the struct isci_phy object to stop.
1174 *
1175 * This method will stop the struct isci_phy object. This does not reset the
1176 * protocol engine it just suspends it and places it in a state where it will
1177 * not cause the end device to power up. none
1178 */
1179static void scu_link_layer_stop_protocol_engine(
1180        struct isci_phy *iphy)
1181{
1182        u32 scu_sas_pcfg_value;
1183        u32 enable_spinup_value;
1184
1185        /* Suspend the protocol engine and place it in a sata spinup hold state */
1186        scu_sas_pcfg_value =
1187                readl(&iphy->link_layer_registers->phy_configuration);
1188        scu_sas_pcfg_value |=
1189                (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1190                 SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1191                 SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1192        writel(scu_sas_pcfg_value,
1193               &iphy->link_layer_registers->phy_configuration);
1194
1195        /* Disable the notify enable spinup primitives */
1196        enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
1197        enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1198        writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control);
1199}
1200
1201static void scu_link_layer_start_oob(struct isci_phy *iphy)
1202{
1203        struct scu_link_layer_registers __iomem *ll = iphy->link_layer_registers;
1204        u32 val;
1205
1206        /** Reset OOB sequence - start */
1207        val = readl(&ll->phy_configuration);
1208        val &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1209                 SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE) |
1210                 SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1211        writel(val, &ll->phy_configuration);
1212        readl(&ll->phy_configuration); /* flush */
1213        /** Reset OOB sequence - end */
1214
1215        /** Start OOB sequence - start */
1216        val = readl(&ll->phy_configuration);
1217        val |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1218        writel(val, &ll->phy_configuration);
1219        readl(&ll->phy_configuration); /* flush */
1220        /** Start OOB sequence - end */
1221}
1222
1223/**
1224 *
1225 *
1226 * This method will transmit a hard reset request on the specified phy. The SCU
1227 * hardware requires that we reset the OOB state machine and set the hard reset
1228 * bit in the phy configuration register. We then must start OOB over with the
1229 * hard reset bit set.
1230 */
1231static void scu_link_layer_tx_hard_reset(
1232        struct isci_phy *iphy)
1233{
1234        u32 phy_configuration_value;
1235
1236        /*
1237         * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1238         * to the starting state. */
1239        phy_configuration_value =
1240                readl(&iphy->link_layer_registers->phy_configuration);
1241        phy_configuration_value &= ~(SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
1242        phy_configuration_value |=
1243                (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1244                 SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1245        writel(phy_configuration_value,
1246               &iphy->link_layer_registers->phy_configuration);
1247
1248        /* Now take the OOB state machine out of reset */
1249        phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1250        phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1251        writel(phy_configuration_value,
1252               &iphy->link_layer_registers->phy_configuration);
1253}
1254
1255static void sci_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1256{
1257        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1258        struct isci_port *iport = iphy->owning_port;
1259        struct isci_host *ihost = iport->owning_controller;
1260
1261        /*
1262         * @todo We need to get to the controller to place this PE in a
1263         * reset state
1264         */
1265        sci_del_timer(&iphy->sata_timer);
1266
1267        scu_link_layer_stop_protocol_engine(iphy);
1268
1269        if (iphy->sm.previous_state_id != SCI_PHY_INITIAL)
1270                sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1271}
1272
1273static void sci_phy_starting_state_enter(struct sci_base_state_machine *sm)
1274{
1275        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1276        struct isci_port *iport = iphy->owning_port;
1277        struct isci_host *ihost = iport->owning_controller;
1278
1279        scu_link_layer_stop_protocol_engine(iphy);
1280        scu_link_layer_start_oob(iphy);
1281
1282        /* We don't know what kind of phy we are going to be just yet */
1283        iphy->protocol = SAS_PROTOCOL_NONE;
1284        iphy->bcn_received_while_port_unassigned = false;
1285
1286        if (iphy->sm.previous_state_id == SCI_PHY_READY)
1287                sci_controller_link_down(ihost, phy_get_non_dummy_port(iphy), iphy);
1288
1289        sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL);
1290}
1291
1292static void sci_phy_ready_state_enter(struct sci_base_state_machine *sm)
1293{
1294        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1295        struct isci_port *iport = iphy->owning_port;
1296        struct isci_host *ihost = iport->owning_controller;
1297
1298        sci_controller_link_up(ihost, phy_get_non_dummy_port(iphy), iphy);
1299}
1300
1301static void sci_phy_ready_state_exit(struct sci_base_state_machine *sm)
1302{
1303        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1304
1305        sci_phy_suspend(iphy);
1306}
1307
1308static void sci_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1309{
1310        struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1311
1312        /* The phy is being reset, therefore deactivate it from the port.  In
1313         * the resetting state we don't notify the user regarding link up and
1314         * link down notifications
1315         */
1316        sci_port_deactivate_phy(iphy->owning_port, iphy, false);
1317
1318        if (iphy->protocol == SAS_PROTOCOL_SSP) {
1319                scu_link_layer_tx_hard_reset(iphy);
1320        } else {
1321                /* The SCU does not need to have a discrete reset state so
1322                 * just go back to the starting state.
1323                 */
1324                sci_change_state(&iphy->sm, SCI_PHY_STARTING);
1325        }
1326}
1327
1328static const struct sci_base_state sci_phy_state_table[] = {
1329        [SCI_PHY_INITIAL] = { },
1330        [SCI_PHY_STOPPED] = {
1331                .enter_state = sci_phy_stopped_state_enter,
1332        },
1333        [SCI_PHY_STARTING] = {
1334                .enter_state = sci_phy_starting_state_enter,
1335        },
1336        [SCI_PHY_SUB_INITIAL] = {
1337                .enter_state = sci_phy_starting_initial_substate_enter,
1338        },
1339        [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1340        [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1341        [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1342        [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1343                .enter_state = sci_phy_starting_await_sas_power_substate_enter,
1344                .exit_state  = sci_phy_starting_await_sas_power_substate_exit,
1345        },
1346        [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1347                .enter_state = sci_phy_starting_await_sata_power_substate_enter,
1348                .exit_state  = sci_phy_starting_await_sata_power_substate_exit
1349        },
1350        [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1351                .enter_state = sci_phy_starting_await_sata_phy_substate_enter,
1352                .exit_state  = sci_phy_starting_await_sata_phy_substate_exit
1353        },
1354        [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1355                .enter_state = sci_phy_starting_await_sata_speed_substate_enter,
1356                .exit_state  = sci_phy_starting_await_sata_speed_substate_exit
1357        },
1358        [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1359                .enter_state = sci_phy_starting_await_sig_fis_uf_substate_enter,
1360                .exit_state  = sci_phy_starting_await_sig_fis_uf_substate_exit
1361        },
1362        [SCI_PHY_SUB_FINAL] = {
1363                .enter_state = sci_phy_starting_final_substate_enter,
1364        },
1365        [SCI_PHY_READY] = {
1366                .enter_state = sci_phy_ready_state_enter,
1367                .exit_state = sci_phy_ready_state_exit,
1368        },
1369        [SCI_PHY_RESETTING] = {
1370                .enter_state = sci_phy_resetting_state_enter,
1371        },
1372        [SCI_PHY_FINAL] = { },
1373};
1374
1375void sci_phy_construct(struct isci_phy *iphy,
1376                            struct isci_port *iport, u8 phy_index)
1377{
1378        sci_init_sm(&iphy->sm, sci_phy_state_table, SCI_PHY_INITIAL);
1379
1380        /* Copy the rest of the input data to our locals */
1381        iphy->owning_port = iport;
1382        iphy->phy_index = phy_index;
1383        iphy->bcn_received_while_port_unassigned = false;
1384        iphy->protocol = SAS_PROTOCOL_NONE;
1385        iphy->link_layer_registers = NULL;
1386        iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1387
1388        /* Create the SIGNATURE FIS Timeout timer for this phy */
1389        sci_init_timer(&iphy->sata_timer, phy_sata_timeout);
1390}
1391
1392void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1393{
1394        struct sci_oem_params *oem = &ihost->oem_parameters;
1395        u64 sci_sas_addr;
1396        __be64 sas_addr;
1397
1398        sci_sas_addr = oem->phys[index].sas_address.high;
1399        sci_sas_addr <<= 32;
1400        sci_sas_addr |= oem->phys[index].sas_address.low;
1401        sas_addr = cpu_to_be64(sci_sas_addr);
1402        memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1403
1404        iphy->sas_phy.enabled = 0;
1405        iphy->sas_phy.id = index;
1406        iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1407        iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1408        iphy->sas_phy.ha = &ihost->sas_ha;
1409        iphy->sas_phy.lldd_phy = iphy;
1410        iphy->sas_phy.enabled = 1;
1411        iphy->sas_phy.class = SAS;
1412        iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1413        iphy->sas_phy.tproto = 0;
1414        iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1415        iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1416        iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1417        iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1418        memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1419}
1420
1421
1422/**
1423 * isci_phy_control() - This function is one of the SAS Domain Template
1424 *    functions. This is a phy management function.
1425 * @phy: This parameter specifies the sphy being controlled.
1426 * @func: This parameter specifies the phy control function being invoked.
1427 * @buf: This parameter is specific to the phy function being invoked.
1428 *
1429 * status, zero indicates success.
1430 */
1431int isci_phy_control(struct asd_sas_phy *sas_phy,
1432                     enum phy_func func,
1433                     void *buf)
1434{
1435        int ret = 0;
1436        struct isci_phy *iphy = sas_phy->lldd_phy;
1437        struct asd_sas_port *port = sas_phy->port;
1438        struct isci_host *ihost = sas_phy->ha->lldd_ha;
1439        unsigned long flags;
1440
1441        dev_dbg(&ihost->pdev->dev,
1442                "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1443                __func__, sas_phy, func, buf, iphy, port);
1444
1445        switch (func) {
1446        case PHY_FUNC_DISABLE:
1447                spin_lock_irqsave(&ihost->scic_lock, flags);
1448                scu_link_layer_start_oob(iphy);
1449                sci_phy_stop(iphy);
1450                spin_unlock_irqrestore(&ihost->scic_lock, flags);
1451                break;
1452
1453        case PHY_FUNC_LINK_RESET:
1454                spin_lock_irqsave(&ihost->scic_lock, flags);
1455                scu_link_layer_start_oob(iphy);
1456                sci_phy_stop(iphy);
1457                sci_phy_start(iphy);
1458                spin_unlock_irqrestore(&ihost->scic_lock, flags);
1459                break;
1460
1461        case PHY_FUNC_HARD_RESET:
1462                if (!port)
1463                        return -ENODEV;
1464
1465                ret = isci_port_perform_hard_reset(ihost, port->lldd_port, iphy);
1466
1467                break;
1468        case PHY_FUNC_GET_EVENTS: {
1469                struct scu_link_layer_registers __iomem *r;
1470                struct sas_phy *phy = sas_phy->phy;
1471
1472                r = iphy->link_layer_registers;
1473                phy->running_disparity_error_count = readl(&r->running_disparity_error_count);
1474                phy->loss_of_dword_sync_count = readl(&r->loss_of_sync_error_count);
1475                phy->phy_reset_problem_count = readl(&r->phy_reset_problem_count);
1476                phy->invalid_dword_count = readl(&r->invalid_dword_counter);
1477                break;
1478        }
1479
1480        default:
1481                dev_dbg(&ihost->pdev->dev,
1482                           "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1483                           __func__, sas_phy, func);
1484                ret = -ENOSYS;
1485                break;
1486        }
1487        return ret;
1488}
1489