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40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46#define SMP_DIRECT 1
47#define SMP_INDIRECT 2
48
49
50int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51{
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55
56 start = jiffies + HZ;
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
64 return -1;
65 }
66 return 0;
67}
68
69static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
72{
73 u32 index, value, offset;
74 u32 *destination1;
75 destination1 = (u32 *)destination;
76
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
82 }
83 }
84 return;
85}
86
87ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
89{
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 accum_len , reg_val, index, *temp;
95 u32 status = 1;
96 unsigned long start;
97 u8 *direct_data;
98 char *fatal_error_data = buf;
99 u32 length_to_read;
100 u32 offset;
101
102 pm8001_ha->forensic_info.data_buf.direct_data = buf;
103 if (pm8001_ha->chip_id == chip_8001) {
104 pm8001_ha->forensic_info.data_buf.direct_data +=
105 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
106 "Not supported for SPC controller");
107 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
108 (char *)buf;
109 }
110
111 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
112 PM8001_IO_DBG(pm8001_ha,
113 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
114 direct_data = (u8 *)fatal_error_data;
115 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
116 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
117 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
118 pm8001_ha->forensic_info.data_buf.read_len = 0;
119 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
120
121
122 pm8001_mw32(fatal_table_address,
123 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
124
125 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
126 PM8001_IO_DBG(pm8001_ha,
127 pm8001_printk("ossaHwCB: status1 %d\n", status));
128 PM8001_IO_DBG(pm8001_ha,
129 pm8001_printk("ossaHwCB: read_len 0x%x\n",
130 pm8001_ha->forensic_info.data_buf.read_len));
131 PM8001_IO_DBG(pm8001_ha,
132 pm8001_printk("ossaHwCB: direct_len 0x%x\n",
133 pm8001_ha->forensic_info.data_buf.direct_len));
134 PM8001_IO_DBG(pm8001_ha,
135 pm8001_printk("ossaHwCB: direct_offset 0x%x\n",
136 pm8001_ha->forensic_info.data_buf.direct_offset));
137 }
138 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
139
140
141 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
142 pm8001_ha->fatal_forensic_shift_offset);
143 pm8001_ha->forensic_last_offset = 0;
144 pm8001_ha->forensic_fatal_step = 0;
145 pm8001_ha->fatal_bar_loc = 0;
146 }
147
148
149 accum_len = pm8001_mr32(fatal_table_address,
150 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
151
152
153
154 length_to_read =
155 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
156 PM8001_IO_DBG(pm8001_ha,
157 pm8001_printk("get_fatal_spcv: accum_len 0x%x\n", accum_len));
158 PM8001_IO_DBG(pm8001_ha,
159 pm8001_printk("get_fatal_spcv: length_to_read 0x%x\n",
160 length_to_read));
161 PM8001_IO_DBG(pm8001_ha,
162 pm8001_printk("get_fatal_spcv: last_offset 0x%x\n",
163 pm8001_ha->forensic_last_offset));
164 PM8001_IO_DBG(pm8001_ha,
165 pm8001_printk("get_fatal_spcv: read_len 0x%x\n",
166 pm8001_ha->forensic_info.data_buf.read_len));
167 PM8001_IO_DBG(pm8001_ha,
168 pm8001_printk("get_fatal_spcv:: direct_len 0x%x\n",
169 pm8001_ha->forensic_info.data_buf.direct_len));
170 PM8001_IO_DBG(pm8001_ha,
171 pm8001_printk("get_fatal_spcv:: direct_offset 0x%x\n",
172 pm8001_ha->forensic_info.data_buf.direct_offset));
173
174
175 if (accum_len == 0xFFFFFFFF) {
176 PM8001_IO_DBG(pm8001_ha,
177 pm8001_printk("Possible PCI issue 0x%x not expected\n",
178 accum_len));
179 return status;
180 }
181
182 if (accum_len == 0) {
183 pm8001_ha->forensic_info.data_buf.direct_data +=
184 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
185 "%08x ", 0xFFFFFFFF);
186 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
187 (char *)buf;
188 }
189
190 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
191 if (pm8001_ha->forensic_fatal_step == 0) {
192moreData:
193
194
195
196 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
197 > length_to_read) {
198 pm8001_ha->forensic_info.data_buf.direct_len =
199 length_to_read -
200 pm8001_ha->forensic_last_offset;
201 } else {
202 pm8001_ha->forensic_info.data_buf.direct_len =
203 SYSFS_OFFSET;
204 }
205 if (pm8001_ha->forensic_info.data_buf.direct_data) {
206
207 pm80xx_pci_mem_copy(pm8001_ha,
208 pm8001_ha->fatal_bar_loc,
209 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
210 pm8001_ha->forensic_info.data_buf.direct_len, 1);
211 }
212 pm8001_ha->fatal_bar_loc +=
213 pm8001_ha->forensic_info.data_buf.direct_len;
214 pm8001_ha->forensic_info.data_buf.direct_offset +=
215 pm8001_ha->forensic_info.data_buf.direct_len;
216 pm8001_ha->forensic_last_offset +=
217 pm8001_ha->forensic_info.data_buf.direct_len;
218 pm8001_ha->forensic_info.data_buf.read_len =
219 pm8001_ha->forensic_info.data_buf.direct_len;
220
221 if (pm8001_ha->forensic_last_offset >= length_to_read) {
222 pm8001_ha->forensic_info.data_buf.direct_data +=
223 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
224 "%08x ", 3);
225 for (index = 0; index <
226 (pm8001_ha->forensic_info.data_buf.direct_len
227 / 4); index++) {
228 pm8001_ha->forensic_info.data_buf.direct_data +=
229 sprintf(
230 pm8001_ha->forensic_info.data_buf.direct_data,
231 "%08x ", *(temp + index));
232 }
233
234 pm8001_ha->fatal_bar_loc = 0;
235 pm8001_ha->forensic_fatal_step = 1;
236 pm8001_ha->fatal_forensic_shift_offset = 0;
237 pm8001_ha->forensic_last_offset = 0;
238 status = 0;
239 offset = (int)
240 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
241 - (char *)buf);
242 PM8001_IO_DBG(pm8001_ha,
243 pm8001_printk("get_fatal_spcv:return1 0x%x\n", offset));
244 return (char *)pm8001_ha->
245 forensic_info.data_buf.direct_data -
246 (char *)buf;
247 }
248 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
249 pm8001_ha->forensic_info.data_buf.direct_data +=
250 sprintf(pm8001_ha->
251 forensic_info.data_buf.direct_data,
252 "%08x ", 2);
253 for (index = 0; index <
254 (pm8001_ha->forensic_info.data_buf.direct_len
255 / 4); index++) {
256 pm8001_ha->forensic_info.data_buf.direct_data
257 += sprintf(pm8001_ha->
258 forensic_info.data_buf.direct_data,
259 "%08x ", *(temp + index));
260 }
261 status = 0;
262 offset = (int)
263 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
264 - (char *)buf);
265 PM8001_IO_DBG(pm8001_ha,
266 pm8001_printk("get_fatal_spcv:return2 0x%x\n", offset));
267 return (char *)pm8001_ha->
268 forensic_info.data_buf.direct_data -
269 (char *)buf;
270 }
271
272
273 pm8001_ha->forensic_info.data_buf.direct_data +=
274 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
275 "%08x ", 2);
276 for (index = 0; index <
277 (pm8001_ha->forensic_info.data_buf.direct_len
278 / 4) ; index++) {
279 pm8001_ha->forensic_info.data_buf.direct_data +=
280 sprintf(pm8001_ha->
281 forensic_info.data_buf.direct_data,
282 "%08x ", *(temp + index));
283 }
284 pm8001_ha->fatal_forensic_shift_offset += 0x100;
285 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
286 pm8001_ha->fatal_forensic_shift_offset);
287 pm8001_ha->fatal_bar_loc = 0;
288 status = 0;
289 offset = (int)
290 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
291 - (char *)buf);
292 PM8001_IO_DBG(pm8001_ha,
293 pm8001_printk("get_fatal_spcv: return3 0x%x\n", offset));
294 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
295 (char *)buf;
296 }
297 if (pm8001_ha->forensic_fatal_step == 1) {
298
299
300
301 pm8001_ha->forensic_preserved_accumulated_transfer =
302 pm8001_mr32(fatal_table_address,
303 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
304
305
306 if (pm8001_mr32(fatal_table_address,
307 MPI_FATAL_EDUMP_TABLE_STATUS) <
308 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
309
310
311 pm8001_mw32(fatal_table_address,
312 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
313
314
315
316
317 pm8001_mw32(fatal_table_address,
318 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
319 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
320
321
322 start = jiffies + (2 * HZ);
323
324 do {
325 reg_val = pm8001_mr32(fatal_table_address,
326 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
327 } while ((reg_val) && time_before(jiffies, start));
328
329 if (reg_val != 0) {
330 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
331 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
332 reg_val));
333
334 pm8001_ha->forensic_info.data_buf.direct_data +=
335 sprintf(
336 pm8001_ha->forensic_info.data_buf.direct_data,
337 "%08x ", 0xFFFFFFFF);
338 return((char *)
339 pm8001_ha->forensic_info.data_buf.direct_data
340 - (char *)buf);
341 }
342
343
344
345 start = jiffies + (2 * HZ);
346
347 do {
348 reg_val = pm8001_mr32(fatal_table_address,
349 MPI_FATAL_EDUMP_TABLE_STATUS);
350 } while (((reg_val != 2) && (reg_val != 3)) &&
351 time_before(jiffies, start));
352
353 if (reg_val < 2) {
354 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
355 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
356 reg_val));
357
358 pm8001_ha->forensic_info.data_buf.direct_data +=
359 sprintf(
360 pm8001_ha->forensic_info.data_buf.direct_data,
361 "%08x ", 0xFFFFFFFF);
362 pm8001_cw32(pm8001_ha, 0,
363 MEMBASE_II_SHIFT_REGISTER,
364 pm8001_ha->fatal_forensic_shift_offset);
365 }
366
367 length_to_read = pm8001_mr32(fatal_table_address,
368 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
369 pm8001_ha->forensic_preserved_accumulated_transfer;
370 if (length_to_read != 0x0) {
371 pm8001_ha->forensic_fatal_step = 0;
372 goto moreData;
373 } else {
374 pm8001_ha->forensic_info.data_buf.direct_data +=
375 sprintf(
376 pm8001_ha->forensic_info.data_buf.direct_data,
377 "%08x ", 4);
378 pm8001_ha->forensic_info.data_buf.read_len
379 = 0xFFFFFFFF;
380 pm8001_ha->forensic_info.data_buf.direct_len
381 = 0;
382 pm8001_ha->forensic_info.data_buf.direct_offset
383 = 0;
384 pm8001_ha->forensic_info.data_buf.read_len = 0;
385 }
386 }
387 }
388 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
389 - (char *)buf);
390 PM8001_IO_DBG(pm8001_ha,
391 pm8001_printk("get_fatal_spcv: return4 0x%x\n", offset));
392 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
393 (char *)buf;
394}
395
396
397
398
399ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
400 struct device_attribute *attr, char *buf)
401{
402 struct Scsi_Host *shost = class_to_shost(cdev);
403 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
404 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
405 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
406 u32 accum_len = 0;
407 u32 total_len = 0;
408 u32 reg_val = 0;
409 u32 *temp = NULL;
410 u32 index = 0;
411 u32 output_length;
412 unsigned long start = 0;
413 char *buf_copy = buf;
414
415 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
416 if (++pm8001_ha->non_fatal_count == 1) {
417 if (pm8001_ha->chip_id == chip_8001) {
418 snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
419 PAGE_SIZE, "Not supported for SPC controller");
420 return 0;
421 }
422 PM8001_IO_DBG(pm8001_ha,
423 pm8001_printk("forensic_info TYPE_NON_FATAL...\n"));
424
425
426
427
428
429 pm8001_mw32(nonfatal_table_address,
430 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
431 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
432
433 pm8001_mw32(nonfatal_table_address,
434 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
435 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
436
437 pm8001_mw32(nonfatal_table_address,
438 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
439
440
441
442
443
444 pm8001_mw32(nonfatal_table_address,
445 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
446
447
448
449
450
451
452 pm8001_mw32(nonfatal_table_address,
453 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
454
455
456 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
457 pm8001_ha->non_fatal_read_length = 0;
458 }
459
460 total_len = pm8001_mr32(nonfatal_table_address,
461 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
462
463
464
465
466
467 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
468 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
469 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
470
471
472
473
474
475
476 start = jiffies + (2 * HZ);
477 do {
478 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
479 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
480 } while ((reg_val != 0) && time_before(jiffies, start));
481
482
483
484
485
486 start = jiffies + (2 * HZ);
487 do {
488 reg_val = pm8001_mr32(nonfatal_table_address,
489 MPI_FATAL_EDUMP_TABLE_STATUS);
490 } while ((!reg_val) && time_before(jiffies, start));
491
492 if ((reg_val == 0x00) ||
493 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
494 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
495 pm8001_ha->non_fatal_read_length = 0;
496 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
497 pm8001_ha->non_fatal_count = 0;
498 return (buf_copy - buf);
499 } else if (reg_val ==
500 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
501 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
502 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
503 (pm8001_ha->non_fatal_read_length >= total_len)) {
504 pm8001_ha->non_fatal_read_length = 0;
505 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
506 pm8001_ha->non_fatal_count = 0;
507 }
508 accum_len = pm8001_mr32(nonfatal_table_address,
509 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
510 output_length = accum_len -
511 pm8001_ha->forensic_preserved_accumulated_transfer;
512
513 for (index = 0; index < output_length/4; index++)
514 buf_copy += snprintf(buf_copy, PAGE_SIZE,
515 "%08x ", *(temp+index));
516
517 pm8001_ha->non_fatal_read_length += output_length;
518
519
520
521
522 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
523 return (buf_copy - buf);
524}
525
526
527
528
529
530static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
531{
532 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
533
534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
535 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
537 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
538 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
539 pm8001_mr32(address, MAIN_FW_REVISION);
540 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
541 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
543 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
545 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
547 pm8001_mr32(address, MAIN_GST_OFFSET);
548 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
549 pm8001_mr32(address, MAIN_IBQ_OFFSET);
550 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
551 pm8001_mr32(address, MAIN_OBQ_OFFSET);
552
553
554 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
555 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
556 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
557 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
559 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
561 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
562
563
564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
565 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
566
567
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
569 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
570
571 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
572 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
574 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
575
576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
577 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
578
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
580 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
582 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
583
584 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
585 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
586 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));
589
590 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
591 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
592 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
593 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
594 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
595 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
596 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset));
597
598 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
599 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
600 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
601 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version));
602}
603
604
605
606
607
608static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
609{
610 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
611 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
612 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
613 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
614 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
615 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
616 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
617 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
618 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
619 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
620 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
621 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
622 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
624 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
625 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
626 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
627 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
628 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
629 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
630 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
631 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
632 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
633 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
634 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
635 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
636 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
637 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
638 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
639}
640
641
642
643
644static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
645{
646 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
647 pm8001_ha->phy_attr_table.phystart1_16[0] =
648 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
649 pm8001_ha->phy_attr_table.phystart1_16[1] =
650 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
651 pm8001_ha->phy_attr_table.phystart1_16[2] =
652 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
653 pm8001_ha->phy_attr_table.phystart1_16[3] =
654 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
655 pm8001_ha->phy_attr_table.phystart1_16[4] =
656 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
657 pm8001_ha->phy_attr_table.phystart1_16[5] =
658 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
659 pm8001_ha->phy_attr_table.phystart1_16[6] =
660 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
661 pm8001_ha->phy_attr_table.phystart1_16[7] =
662 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
663 pm8001_ha->phy_attr_table.phystart1_16[8] =
664 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
665 pm8001_ha->phy_attr_table.phystart1_16[9] =
666 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
667 pm8001_ha->phy_attr_table.phystart1_16[10] =
668 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
669 pm8001_ha->phy_attr_table.phystart1_16[11] =
670 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
671 pm8001_ha->phy_attr_table.phystart1_16[12] =
672 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
673 pm8001_ha->phy_attr_table.phystart1_16[13] =
674 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
675 pm8001_ha->phy_attr_table.phystart1_16[14] =
676 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
677 pm8001_ha->phy_attr_table.phystart1_16[15] =
678 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
679
680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
698 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
699 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
700 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
701 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
702 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
703 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
704 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
705 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
706 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
707 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
708 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
709 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
710 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
711 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
712
713}
714
715
716
717
718
719static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
720{
721 int i;
722 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
723 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
724 u32 offset = i * 0x20;
725 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
726 get_pci_bar_index(pm8001_mr32(address,
727 (offset + IB_PIPCI_BAR)));
728 pm8001_ha->inbnd_q_tbl[i].pi_offset =
729 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
730 }
731}
732
733
734
735
736
737static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
738{
739 int i;
740 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
741 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
742 u32 offset = i * 0x24;
743 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
744 get_pci_bar_index(pm8001_mr32(address,
745 (offset + OB_CIPCI_BAR)));
746 pm8001_ha->outbnd_q_tbl[i].ci_offset =
747 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
748 }
749}
750
751
752
753
754
755static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
756{
757 int i;
758 u32 offsetib, offsetob;
759 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
760 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
761 u32 ib_offset = pm8001_ha->ib_offset;
762 u32 ob_offset = pm8001_ha->ob_offset;
763 u32 ci_offset = pm8001_ha->ci_offset;
764 u32 pi_offset = pm8001_ha->pi_offset;
765
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
767 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
769 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
770 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
771 PM8001_EVENT_LOG_SIZE;
772 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
773 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
774 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
775 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
776 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
777 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
778 PM8001_EVENT_LOG_SIZE;
779 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
780 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
781
782
783 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
784
785 for (i = 0; i < pm8001_ha->max_q_num; i++) {
786 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
787 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
788 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
789 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
790 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
791 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
792 pm8001_ha->inbnd_q_tbl[i].base_virt =
793 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
794 pm8001_ha->inbnd_q_tbl[i].total_length =
795 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
796 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
797 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
798 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
799 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
800 pm8001_ha->inbnd_q_tbl[i].ci_virt =
801 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
802 offsetib = i * 0x20;
803 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
804 get_pci_bar_index(pm8001_mr32(addressib,
805 (offsetib + 0x14)));
806 pm8001_ha->inbnd_q_tbl[i].pi_offset =
807 pm8001_mr32(addressib, (offsetib + 0x18));
808 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
809 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
810
811 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
812 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
813 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
814 pm8001_ha->inbnd_q_tbl[i].pi_offset));
815 }
816 for (i = 0; i < pm8001_ha->max_q_num; i++) {
817 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
818 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
819 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
820 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
821 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
822 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
823 pm8001_ha->outbnd_q_tbl[i].base_virt =
824 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
825 pm8001_ha->outbnd_q_tbl[i].total_length =
826 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
827 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
828 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
829 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
830 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
831
832 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
833 pm8001_ha->outbnd_q_tbl[i].pi_virt =
834 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
835 offsetob = i * 0x24;
836 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
837 get_pci_bar_index(pm8001_mr32(addressob,
838 offsetob + 0x14));
839 pm8001_ha->outbnd_q_tbl[i].ci_offset =
840 pm8001_mr32(addressob, (offsetob + 0x18));
841 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
842 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
843
844 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
845 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
846 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
847 pm8001_ha->outbnd_q_tbl[i].ci_offset));
848 }
849}
850
851
852
853
854
855static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
856{
857 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
858 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
860 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
862 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
864 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
866 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
868 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
869 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
870 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
871 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
872 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
873 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
874 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
875 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
876
877 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
878 ((pm8001_ha->max_q_num - 1) << 8);
879 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
880 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
881 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
882 "Updated Fatal error interrupt vector 0x%x\n",
883 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)));
884
885 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
886 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
887
888
889 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
890
891 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
892 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
893 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
894 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
895 "Programming DW 0x21 in main cfg table with 0x%x\n",
896 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)));
897
898 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
899 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
900 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
902
903 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
904 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
905 PORT_RECOVERY_TIMEOUT;
906 if (pm8001_ha->chip_id == chip_8006) {
907 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
908 0x0000ffff;
909 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
910 CHIP_8006_PORT_RECOVERY_TIMEOUT;
911 }
912 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
913 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
914}
915
916
917
918
919
920
921static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
922 int number)
923{
924 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
925 u16 offset = number * 0x20;
926 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
927 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
928 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
929 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
930 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
931 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
932 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
933 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
934 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
935 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
936
937 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
938 "IQ %d: Element pri size 0x%x\n",
939 number,
940 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt));
941
942 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
943 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
944 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
945 pm8001_ha->inbnd_q_tbl[number].lower_base_addr));
946
947 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
948 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
949 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
950 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr));
951}
952
953
954
955
956
957
958static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
959 int number)
960{
961 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
962 u16 offset = number * 0x24;
963 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
964 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
965 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
966 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
967 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
968 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
969 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
970 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
971 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
972 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
973 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
974 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
975
976 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
977 "OQ %d: Element pri size 0x%x\n",
978 number,
979 pm8001_ha->outbnd_q_tbl[number].element_size_cnt));
980
981 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
982 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
983 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
984 pm8001_ha->outbnd_q_tbl[number].lower_base_addr));
985
986 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
987 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
988 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
989 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr));
990}
991
992
993
994
995
996static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
997{
998 u32 max_wait_count;
999 u32 value;
1000 u32 gst_len_mpistate;
1001
1002
1003
1004 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
1005
1006 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1007 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1008 } else {
1009 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1010 }
1011 do {
1012 udelay(1);
1013 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1014 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1015 } while ((value != 0) && (--max_wait_count));
1016
1017 if (!max_wait_count) {
1018
1019 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1020 "Inb doorbell clear not toggled[value:%x]\n", value));
1021 return -EBUSY;
1022 }
1023
1024 max_wait_count = 100 * 1000;
1025 do {
1026 udelay(1);
1027 gst_len_mpistate =
1028 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1029 GST_GSTLEN_MPIS_OFFSET);
1030 } while ((GST_MPI_STATE_INIT !=
1031 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1032 if (!max_wait_count)
1033 return -EBUSY;
1034
1035
1036 gst_len_mpistate = gst_len_mpistate >> 16;
1037 if (0x0000 != gst_len_mpistate)
1038 return -EBUSY;
1039
1040 return 0;
1041}
1042
1043
1044
1045
1046
1047static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1048{
1049 u32 value;
1050 u32 max_wait_count;
1051 u32 max_wait_time;
1052 int ret = 0;
1053
1054
1055 max_wait_time = max_wait_count = 100 * 1000;
1056 do {
1057 udelay(1);
1058 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1059 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1060
1061
1062 max_wait_time = max_wait_count = 1000 * 1000;
1063 do {
1064 udelay(1);
1065 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1066 } while (((value & SCRATCH_PAD_ILA_READY) !=
1067 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
1068 if (!max_wait_count)
1069 ret = -1;
1070 else {
1071 PM8001_MSG_DBG(pm8001_ha,
1072 pm8001_printk(" ila ready status in %d millisec\n",
1073 (max_wait_time - max_wait_count)));
1074 }
1075
1076
1077 max_wait_time = max_wait_count = 1800 * 1000;
1078 do {
1079 udelay(1);
1080 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1081 } while (((value & SCRATCH_PAD_RAAE_READY) !=
1082 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
1083 if (!max_wait_count)
1084 ret = -1;
1085 else {
1086 PM8001_MSG_DBG(pm8001_ha,
1087 pm8001_printk(" raae ready status in %d millisec\n",
1088 (max_wait_time - max_wait_count)));
1089 }
1090
1091
1092 max_wait_time = max_wait_count = 600 * 1000;
1093 do {
1094 udelay(1);
1095 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1096 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
1097 (--max_wait_count));
1098 if (!max_wait_count)
1099 ret = -1;
1100 else {
1101 PM8001_MSG_DBG(pm8001_ha,
1102 pm8001_printk(" iop0 ready status in %d millisec\n",
1103 (max_wait_time - max_wait_count)));
1104 }
1105
1106
1107 if ((pm8001_ha->chip_id != chip_8008) &&
1108 (pm8001_ha->chip_id != chip_8009)) {
1109
1110 max_wait_time = max_wait_count = 200 * 1000;
1111 do {
1112 udelay(1);
1113 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1114 } while (((value & SCRATCH_PAD_IOP1_READY) !=
1115 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
1116 if (!max_wait_count)
1117 ret = -1;
1118 else {
1119 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1120 "iop1 ready status in %d millisec\n",
1121 (max_wait_time - max_wait_count)));
1122 }
1123 }
1124
1125 return ret;
1126}
1127
1128static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1129{
1130 void __iomem *base_addr;
1131 u32 value;
1132 u32 offset;
1133 u32 pcibar;
1134 u32 pcilogic;
1135
1136 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1137 offset = value & 0x03FFFFFF;
1138
1139 PM8001_DEV_DBG(pm8001_ha,
1140 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
1141 offset, value));
1142 pcilogic = (value & 0xFC000000) >> 26;
1143 pcibar = get_pci_bar_index(pcilogic);
1144 PM8001_INIT_DBG(pm8001_ha,
1145 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
1146 pm8001_ha->main_cfg_tbl_addr = base_addr =
1147 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1148 pm8001_ha->general_stat_tbl_addr =
1149 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1150 0xFFFFFF);
1151 pm8001_ha->inbnd_q_tbl_addr =
1152 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1153 0xFFFFFF);
1154 pm8001_ha->outbnd_q_tbl_addr =
1155 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1156 0xFFFFFF);
1157 pm8001_ha->ivt_tbl_addr =
1158 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1159 0xFFFFFF);
1160 pm8001_ha->pspa_q_tbl_addr =
1161 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1162 0xFFFFFF);
1163 pm8001_ha->fatal_tbl_addr =
1164 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1165 0xFFFFFF);
1166
1167 PM8001_INIT_DBG(pm8001_ha,
1168 pm8001_printk("GST OFFSET 0x%x\n",
1169 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
1170 PM8001_INIT_DBG(pm8001_ha,
1171 pm8001_printk("INBND OFFSET 0x%x\n",
1172 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
1173 PM8001_INIT_DBG(pm8001_ha,
1174 pm8001_printk("OBND OFFSET 0x%x\n",
1175 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
1176 PM8001_INIT_DBG(pm8001_ha,
1177 pm8001_printk("IVT OFFSET 0x%x\n",
1178 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
1179 PM8001_INIT_DBG(pm8001_ha,
1180 pm8001_printk("PSPA OFFSET 0x%x\n",
1181 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
1182 PM8001_INIT_DBG(pm8001_ha,
1183 pm8001_printk("addr - main cfg %p general status %p\n",
1184 pm8001_ha->main_cfg_tbl_addr,
1185 pm8001_ha->general_stat_tbl_addr));
1186 PM8001_INIT_DBG(pm8001_ha,
1187 pm8001_printk("addr - inbnd %p obnd %p\n",
1188 pm8001_ha->inbnd_q_tbl_addr,
1189 pm8001_ha->outbnd_q_tbl_addr));
1190 PM8001_INIT_DBG(pm8001_ha,
1191 pm8001_printk("addr - pspa %p ivt %p\n",
1192 pm8001_ha->pspa_q_tbl_addr,
1193 pm8001_ha->ivt_tbl_addr));
1194}
1195
1196
1197
1198
1199
1200int
1201pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1202{
1203 struct set_ctrl_cfg_req payload;
1204 struct inbound_queue_table *circularQ;
1205 int rc;
1206 u32 tag;
1207 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1208 u32 page_code;
1209
1210 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1211 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1212 if (rc)
1213 return -1;
1214
1215 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1216 payload.tag = cpu_to_le32(tag);
1217
1218 if (IS_SPCV_12G(pm8001_ha->pdev))
1219 page_code = THERMAL_PAGE_CODE_7H;
1220 else
1221 page_code = THERMAL_PAGE_CODE_8H;
1222
1223 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
1224 (THERMAL_ENABLE << 8) | page_code;
1225 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
1226
1227 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1228 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1229 payload.cfg_pg[0], payload.cfg_pg[1]));
1230
1231 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1232 sizeof(payload), 0);
1233 if (rc)
1234 pm8001_tag_free(pm8001_ha, tag);
1235 return rc;
1236
1237}
1238
1239
1240
1241
1242
1243
1244static int
1245pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1246{
1247 struct set_ctrl_cfg_req payload;
1248 struct inbound_queue_table *circularQ;
1249 SASProtocolTimerConfig_t SASConfigPage;
1250 int rc;
1251 u32 tag;
1252 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1253
1254 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1255 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1256
1257 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1258
1259 if (rc)
1260 return -1;
1261
1262 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1263 payload.tag = cpu_to_le32(tag);
1264
1265 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
1266 SASConfigPage.MST_MSI = 3 << 15;
1267 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
1268 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
1269 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
1270 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
1271
1272 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
1273 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1274
1275
1276 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
1277 SAS_OPNRJT_RTRY_INTVL;
1278 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
1279 | SAS_COPNRJT_RTRY_TMO;
1280 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
1281 | SAS_COPNRJT_RTRY_THR;
1282 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
1283
1284 PM8001_INIT_DBG(pm8001_ha,
1285 pm8001_printk("SASConfigPage.pageCode "
1286 "0x%08x\n", SASConfigPage.pageCode));
1287 PM8001_INIT_DBG(pm8001_ha,
1288 pm8001_printk("SASConfigPage.MST_MSI "
1289 " 0x%08x\n", SASConfigPage.MST_MSI));
1290 PM8001_INIT_DBG(pm8001_ha,
1291 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
1292 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
1293 PM8001_INIT_DBG(pm8001_ha,
1294 pm8001_printk("SASConfigPage.STP_FRM_TMO "
1295 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
1296 PM8001_INIT_DBG(pm8001_ha,
1297 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
1298 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
1299 PM8001_INIT_DBG(pm8001_ha,
1300 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
1301 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
1302 PM8001_INIT_DBG(pm8001_ha,
1303 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
1304 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1305 PM8001_INIT_DBG(pm8001_ha,
1306 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
1307 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1308 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
1309 " 0x%08x\n", SASConfigPage.MAX_AIP));
1310
1311 memcpy(&payload.cfg_pg, &SASConfigPage,
1312 sizeof(SASProtocolTimerConfig_t));
1313
1314 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1315 sizeof(payload), 0);
1316 if (rc)
1317 pm8001_tag_free(pm8001_ha, tag);
1318
1319 return rc;
1320}
1321
1322
1323
1324
1325
1326static int
1327pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1328{
1329 u32 scratch3_value;
1330 int ret = -1;
1331
1332
1333 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1334
1335 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1336 SCRATCH_PAD3_ENC_READY) {
1337 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1338 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1339 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1340 SCRATCH_PAD3_SMF_ENABLED)
1341 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1342 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1343 SCRATCH_PAD3_SMA_ENABLED)
1344 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1345 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1346 SCRATCH_PAD3_SMB_ENABLED)
1347 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1348 pm8001_ha->encrypt_info.status = 0;
1349 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1350 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1351 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1352 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1353 pm8001_ha->encrypt_info.sec_mode,
1354 pm8001_ha->encrypt_info.status));
1355 ret = 0;
1356 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1357 SCRATCH_PAD3_ENC_DISABLED) {
1358 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1359 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1360 scratch3_value));
1361 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1362 pm8001_ha->encrypt_info.cipher_mode = 0;
1363 pm8001_ha->encrypt_info.sec_mode = 0;
1364 ret = 0;
1365 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1366 SCRATCH_PAD3_ENC_DIS_ERR) {
1367 pm8001_ha->encrypt_info.status =
1368 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1369 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1370 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1371 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1372 SCRATCH_PAD3_SMF_ENABLED)
1373 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1374 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1375 SCRATCH_PAD3_SMA_ENABLED)
1376 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1377 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1378 SCRATCH_PAD3_SMB_ENABLED)
1379 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1380 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1381 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1382 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1383 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1384 pm8001_ha->encrypt_info.sec_mode,
1385 pm8001_ha->encrypt_info.status));
1386 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1387 SCRATCH_PAD3_ENC_ENA_ERR) {
1388
1389 pm8001_ha->encrypt_info.status =
1390 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1391 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1392 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1393 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1394 SCRATCH_PAD3_SMF_ENABLED)
1395 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1396 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1397 SCRATCH_PAD3_SMA_ENABLED)
1398 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1399 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1400 SCRATCH_PAD3_SMB_ENABLED)
1401 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1402
1403 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1404 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1405 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1406 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1407 pm8001_ha->encrypt_info.sec_mode,
1408 pm8001_ha->encrypt_info.status));
1409 }
1410 return ret;
1411}
1412
1413
1414
1415
1416
1417static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1418{
1419 struct kek_mgmt_req payload;
1420 struct inbound_queue_table *circularQ;
1421 int rc;
1422 u32 tag;
1423 u32 opc = OPC_INB_KEK_MANAGEMENT;
1424
1425 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1426 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1427 if (rc)
1428 return -1;
1429
1430 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1431 payload.tag = cpu_to_le32(tag);
1432
1433
1434
1435 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1436 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1437
1438 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1439 "Saving Encryption info to flash. payload 0x%x\n",
1440 payload.new_curidx_ksop));
1441
1442 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1443 sizeof(payload), 0);
1444 if (rc)
1445 pm8001_tag_free(pm8001_ha, tag);
1446
1447 return rc;
1448}
1449
1450
1451
1452
1453
1454static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1455{
1456 int ret;
1457 u8 i = 0;
1458
1459
1460 if (-1 == check_fw_ready(pm8001_ha)) {
1461 PM8001_FAIL_DBG(pm8001_ha,
1462 pm8001_printk("Firmware is not ready!\n"));
1463 return -EBUSY;
1464 }
1465
1466
1467 pm8001_ha->controller_fatal_error = false;
1468
1469
1470 init_pci_device_addresses(pm8001_ha);
1471 init_default_table_values(pm8001_ha);
1472 read_main_config_table(pm8001_ha);
1473 read_general_status_table(pm8001_ha);
1474 read_inbnd_queue_table(pm8001_ha);
1475 read_outbnd_queue_table(pm8001_ha);
1476 read_phy_attr_table(pm8001_ha);
1477
1478
1479 update_main_config_table(pm8001_ha);
1480 for (i = 0; i < pm8001_ha->max_q_num; i++) {
1481 update_inbnd_queue_table(pm8001_ha, i);
1482 update_outbnd_queue_table(pm8001_ha, i);
1483 }
1484
1485 if (0 == mpi_init_check(pm8001_ha)) {
1486 PM8001_INIT_DBG(pm8001_ha,
1487 pm8001_printk("MPI initialize successful!\n"));
1488 } else
1489 return -EBUSY;
1490
1491
1492 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1493
1494
1495 if (pm8001_ha->chip->encrypt) {
1496 PM8001_INIT_DBG(pm8001_ha,
1497 pm8001_printk("Checking for encryption\n"));
1498 ret = pm80xx_get_encrypt_info(pm8001_ha);
1499 if (ret == -1) {
1500 PM8001_INIT_DBG(pm8001_ha,
1501 pm8001_printk("Encryption error !!\n"));
1502 if (pm8001_ha->encrypt_info.status == 0x81) {
1503 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1504 "Encryption enabled with error."
1505 "Saving encryption key to flash\n"));
1506 pm80xx_encrypt_update(pm8001_ha);
1507 }
1508 }
1509 }
1510 return 0;
1511}
1512
1513static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1514{
1515 u32 max_wait_count;
1516 u32 value;
1517 u32 gst_len_mpistate;
1518 init_pci_device_addresses(pm8001_ha);
1519
1520
1521 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1522
1523
1524 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1525 max_wait_count = 4 * 1000 * 1000;
1526 } else {
1527 max_wait_count = 2 * 1000 * 1000;
1528 }
1529 do {
1530 udelay(1);
1531 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1532 value &= SPCv_MSGU_CFG_TABLE_RESET;
1533 } while ((value != 0) && (--max_wait_count));
1534
1535 if (!max_wait_count) {
1536 PM8001_FAIL_DBG(pm8001_ha,
1537 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1538 return -1;
1539 }
1540
1541
1542
1543 max_wait_count = 2 * 1000 * 1000;
1544 do {
1545 udelay(1);
1546 gst_len_mpistate =
1547 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1548 GST_GSTLEN_MPIS_OFFSET);
1549 if (GST_MPI_STATE_UNINIT ==
1550 (gst_len_mpistate & GST_MPI_STATE_MASK))
1551 break;
1552 } while (--max_wait_count);
1553 if (!max_wait_count) {
1554 PM8001_FAIL_DBG(pm8001_ha,
1555 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1556 gst_len_mpistate & GST_MPI_STATE_MASK));
1557 return -1;
1558 }
1559
1560 return 0;
1561}
1562
1563
1564
1565
1566
1567
1568
1569static int
1570pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1571{
1572 u32 regval;
1573 u32 bootloader_state;
1574 u32 ibutton0, ibutton1;
1575
1576
1577 if (!pm8001_ha->controller_fatal_error) {
1578
1579 if (mpi_uninit_check(pm8001_ha) != 0) {
1580 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1581 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1582 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1583 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1584 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1585 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1586 r0, r1, r2, r3));
1587
1588
1589
1590 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1591 return -1;
1592 }
1593 }
1594
1595 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1596 PM8001_INIT_DBG(pm8001_ha,
1597 pm8001_printk("reset register before write : 0x%x\n", regval));
1598
1599 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1600 msleep(500);
1601
1602 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1603 PM8001_INIT_DBG(pm8001_ha,
1604 pm8001_printk("reset register after write 0x%x\n", regval));
1605
1606 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1607 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1608 PM8001_MSG_DBG(pm8001_ha,
1609 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1610 regval));
1611 } else {
1612 PM8001_MSG_DBG(pm8001_ha,
1613 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1614 regval));
1615
1616
1617 bootloader_state =
1618 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1619 SCRATCH_PAD1_BOOTSTATE_MASK;
1620
1621 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1622 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1623 "Bootloader state - HDA mode SEEPROM\n"));
1624 } else if (bootloader_state ==
1625 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1626 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1627 "Bootloader state - HDA mode Bootstrap Pin\n"));
1628 } else if (bootloader_state ==
1629 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1630 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1631 "Bootloader state - HDA mode soft reset\n"));
1632 } else if (bootloader_state ==
1633 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1634 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1635 "Bootloader state-HDA mode critical error\n"));
1636 }
1637 return -EBUSY;
1638 }
1639
1640
1641 if (-1 == check_fw_ready(pm8001_ha)) {
1642 PM8001_FAIL_DBG(pm8001_ha,
1643 pm8001_printk("Firmware is not ready!\n"));
1644
1645 if (pm8001_ha->pdev->subsystem_vendor !=
1646 PCI_VENDOR_ID_ADAPTEC2 &&
1647 pm8001_ha->pdev->subsystem_vendor !=
1648 PCI_VENDOR_ID_ATTO &&
1649 pm8001_ha->pdev->subsystem_vendor != 0) {
1650 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1651 MSGU_HOST_SCRATCH_PAD_6);
1652 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1653 MSGU_HOST_SCRATCH_PAD_7);
1654 if (!ibutton0 && !ibutton1) {
1655 PM8001_FAIL_DBG(pm8001_ha,
1656 pm8001_printk("iButton Feature is"
1657 " not Available!!!\n"));
1658 return -EBUSY;
1659 }
1660 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1661 PM8001_FAIL_DBG(pm8001_ha,
1662 pm8001_printk("CRC Check for iButton"
1663 " Feature Failed!!!\n"));
1664 return -EBUSY;
1665 }
1666 }
1667 }
1668 PM8001_INIT_DBG(pm8001_ha,
1669 pm8001_printk("SPCv soft reset Complete\n"));
1670 return 0;
1671}
1672
1673static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1674{
1675 u32 i;
1676
1677 PM8001_INIT_DBG(pm8001_ha,
1678 pm8001_printk("chip reset start\n"));
1679
1680
1681 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1682 PM8001_INIT_DBG(pm8001_ha,
1683 pm8001_printk("SPC soft reset Complete\n"));
1684
1685
1686
1687 udelay(10);
1688
1689
1690 i = 20;
1691 do {
1692 mdelay(1);
1693 } while ((--i) != 0);
1694
1695 PM8001_INIT_DBG(pm8001_ha,
1696 pm8001_printk("chip reset finished\n"));
1697}
1698
1699
1700
1701
1702
1703static void
1704pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1705{
1706 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1707 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1708}
1709
1710
1711
1712
1713
1714static void
1715pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1716{
1717 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1718}
1719
1720
1721
1722
1723
1724
1725static void
1726pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1727{
1728#ifdef PM8001_USE_MSIX
1729 u32 mask;
1730 mask = (u32)(1 << vec);
1731
1732 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1733 return;
1734#endif
1735 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1736
1737}
1738
1739
1740
1741
1742
1743
1744static void
1745pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1746{
1747#ifdef PM8001_USE_MSIX
1748 u32 mask;
1749 if (vec == 0xFF)
1750 mask = 0xFFFFFFFF;
1751 else
1752 mask = (u32)(1 << vec);
1753 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1754 return;
1755#endif
1756 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1757}
1758
1759static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1760 struct pm8001_device *pm8001_ha_dev)
1761{
1762 int res;
1763 u32 ccb_tag;
1764 struct pm8001_ccb_info *ccb;
1765 struct sas_task *task = NULL;
1766 struct task_abort_req task_abort;
1767 struct inbound_queue_table *circularQ;
1768 u32 opc = OPC_INB_SATA_ABORT;
1769 int ret;
1770
1771 if (!pm8001_ha_dev) {
1772 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1773 return;
1774 }
1775
1776 task = sas_alloc_slow_task(GFP_ATOMIC);
1777
1778 if (!task) {
1779 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1780 "allocate task\n"));
1781 return;
1782 }
1783
1784 task->task_done = pm8001_task_done;
1785
1786 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1787 if (res) {
1788 sas_free_task(task);
1789 return;
1790 }
1791
1792 ccb = &pm8001_ha->ccb_info[ccb_tag];
1793 ccb->device = pm8001_ha_dev;
1794 ccb->ccb_tag = ccb_tag;
1795 ccb->task = task;
1796
1797 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1798
1799 memset(&task_abort, 0, sizeof(task_abort));
1800 task_abort.abort_all = cpu_to_le32(1);
1801 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1802 task_abort.tag = cpu_to_le32(ccb_tag);
1803
1804 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1805 sizeof(task_abort), 0);
1806 PM8001_FAIL_DBG(pm8001_ha,
1807 pm8001_printk("Executing abort task end\n"));
1808 if (ret) {
1809 sas_free_task(task);
1810 pm8001_tag_free(pm8001_ha, ccb_tag);
1811 }
1812}
1813
1814static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1815 struct pm8001_device *pm8001_ha_dev)
1816{
1817 struct sata_start_req sata_cmd;
1818 int res;
1819 u32 ccb_tag;
1820 struct pm8001_ccb_info *ccb;
1821 struct sas_task *task = NULL;
1822 struct host_to_dev_fis fis;
1823 struct domain_device *dev;
1824 struct inbound_queue_table *circularQ;
1825 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1826
1827 task = sas_alloc_slow_task(GFP_ATOMIC);
1828
1829 if (!task) {
1830 PM8001_FAIL_DBG(pm8001_ha,
1831 pm8001_printk("cannot allocate task !!!\n"));
1832 return;
1833 }
1834 task->task_done = pm8001_task_done;
1835
1836 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1837 if (res) {
1838 sas_free_task(task);
1839 PM8001_FAIL_DBG(pm8001_ha,
1840 pm8001_printk("cannot allocate tag !!!\n"));
1841 return;
1842 }
1843
1844
1845
1846
1847 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1848 if (!dev) {
1849 sas_free_task(task);
1850 pm8001_tag_free(pm8001_ha, ccb_tag);
1851 PM8001_FAIL_DBG(pm8001_ha,
1852 pm8001_printk("Domain device cannot be allocated\n"));
1853 return;
1854 }
1855
1856 task->dev = dev;
1857 task->dev->lldd_dev = pm8001_ha_dev;
1858
1859 ccb = &pm8001_ha->ccb_info[ccb_tag];
1860 ccb->device = pm8001_ha_dev;
1861 ccb->ccb_tag = ccb_tag;
1862 ccb->task = task;
1863 ccb->n_elem = 0;
1864 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1865 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1866
1867 memset(&sata_cmd, 0, sizeof(sata_cmd));
1868 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1869
1870
1871 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1872 fis.fis_type = 0x27;
1873 fis.flags = 0x80;
1874 fis.command = ATA_CMD_READ_LOG_EXT;
1875 fis.lbal = 0x10;
1876 fis.sector_count = 0x1;
1877
1878 sata_cmd.tag = cpu_to_le32(ccb_tag);
1879 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1880 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1881 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1882
1883 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1884 sizeof(sata_cmd), 0);
1885 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Executing read log end\n"));
1886 if (res) {
1887 sas_free_task(task);
1888 pm8001_tag_free(pm8001_ha, ccb_tag);
1889 kfree(dev);
1890 }
1891}
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904static void
1905mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1906{
1907 struct sas_task *t;
1908 struct pm8001_ccb_info *ccb;
1909 unsigned long flags;
1910 u32 status;
1911 u32 param;
1912 u32 tag;
1913 struct ssp_completion_resp *psspPayload;
1914 struct task_status_struct *ts;
1915 struct ssp_response_iu *iu;
1916 struct pm8001_device *pm8001_dev;
1917 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1918 status = le32_to_cpu(psspPayload->status);
1919 tag = le32_to_cpu(psspPayload->tag);
1920 ccb = &pm8001_ha->ccb_info[tag];
1921 if ((status == IO_ABORTED) && ccb->open_retry) {
1922
1923 ccb->open_retry = 0;
1924 return;
1925 }
1926 pm8001_dev = ccb->device;
1927 param = le32_to_cpu(psspPayload->param);
1928 t = ccb->task;
1929
1930 if (status && status != IO_UNDERFLOW)
1931 PM8001_FAIL_DBG(pm8001_ha,
1932 pm8001_printk("sas IO status 0x%x\n", status));
1933 if (unlikely(!t || !t->lldd_task || !t->dev))
1934 return;
1935 ts = &t->task_status;
1936
1937 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1938 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t));
1939
1940
1941 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1942 (status != IO_UNDERFLOW))
1943 PM8001_FAIL_DBG(pm8001_ha,
1944 pm8001_printk("SAS Address of IO Failure Drive"
1945 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1946
1947 switch (status) {
1948 case IO_SUCCESS:
1949 PM8001_IO_DBG(pm8001_ha,
1950 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1951 param));
1952 if (param == 0) {
1953 ts->resp = SAS_TASK_COMPLETE;
1954 ts->stat = SAM_STAT_GOOD;
1955 } else {
1956 ts->resp = SAS_TASK_COMPLETE;
1957 ts->stat = SAS_PROTO_RESPONSE;
1958 ts->residual = param;
1959 iu = &psspPayload->ssp_resp_iu;
1960 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1961 }
1962 if (pm8001_dev)
1963 pm8001_dev->running_req--;
1964 break;
1965 case IO_ABORTED:
1966 PM8001_IO_DBG(pm8001_ha,
1967 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1968 ts->resp = SAS_TASK_COMPLETE;
1969 ts->stat = SAS_ABORTED_TASK;
1970 break;
1971 case IO_UNDERFLOW:
1972
1973 PM8001_IO_DBG(pm8001_ha,
1974 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1975 param));
1976 ts->resp = SAS_TASK_COMPLETE;
1977 ts->stat = SAS_DATA_UNDERRUN;
1978 ts->residual = param;
1979 if (pm8001_dev)
1980 pm8001_dev->running_req--;
1981 break;
1982 case IO_NO_DEVICE:
1983 PM8001_IO_DBG(pm8001_ha,
1984 pm8001_printk("IO_NO_DEVICE\n"));
1985 ts->resp = SAS_TASK_UNDELIVERED;
1986 ts->stat = SAS_PHY_DOWN;
1987 break;
1988 case IO_XFER_ERROR_BREAK:
1989 PM8001_IO_DBG(pm8001_ha,
1990 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1991 ts->resp = SAS_TASK_COMPLETE;
1992 ts->stat = SAS_OPEN_REJECT;
1993
1994 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1995 break;
1996 case IO_XFER_ERROR_PHY_NOT_READY:
1997 PM8001_IO_DBG(pm8001_ha,
1998 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1999 ts->resp = SAS_TASK_COMPLETE;
2000 ts->stat = SAS_OPEN_REJECT;
2001 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2002 break;
2003 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
2004 PM8001_IO_DBG(pm8001_ha,
2005 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
2006 ts->resp = SAS_TASK_COMPLETE;
2007 ts->stat = SAS_OPEN_REJECT;
2008 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2009 break;
2010 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2011 PM8001_IO_DBG(pm8001_ha,
2012 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2013 ts->resp = SAS_TASK_COMPLETE;
2014 ts->stat = SAS_OPEN_REJECT;
2015 ts->open_rej_reason = SAS_OREJ_EPROTO;
2016 break;
2017 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2018 PM8001_IO_DBG(pm8001_ha,
2019 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2020 ts->resp = SAS_TASK_COMPLETE;
2021 ts->stat = SAS_OPEN_REJECT;
2022 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2023 break;
2024 case IO_OPEN_CNX_ERROR_BREAK:
2025 PM8001_IO_DBG(pm8001_ha,
2026 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2027 ts->resp = SAS_TASK_COMPLETE;
2028 ts->stat = SAS_OPEN_REJECT;
2029 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2030 break;
2031 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2032 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2033 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2034 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2035 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2036 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2037 PM8001_IO_DBG(pm8001_ha,
2038 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2039 ts->resp = SAS_TASK_COMPLETE;
2040 ts->stat = SAS_OPEN_REJECT;
2041 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2042 if (!t->uldd_task)
2043 pm8001_handle_event(pm8001_ha,
2044 pm8001_dev,
2045 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2046 break;
2047 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2048 PM8001_IO_DBG(pm8001_ha,
2049 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2050 ts->resp = SAS_TASK_COMPLETE;
2051 ts->stat = SAS_OPEN_REJECT;
2052 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2053 break;
2054 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2055 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2056 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2057 ts->resp = SAS_TASK_COMPLETE;
2058 ts->stat = SAS_OPEN_REJECT;
2059 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2060 break;
2061 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2062 PM8001_IO_DBG(pm8001_ha,
2063 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2064 ts->resp = SAS_TASK_UNDELIVERED;
2065 ts->stat = SAS_OPEN_REJECT;
2066 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2067 break;
2068 case IO_XFER_ERROR_NAK_RECEIVED:
2069 PM8001_IO_DBG(pm8001_ha,
2070 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2071 ts->resp = SAS_TASK_COMPLETE;
2072 ts->stat = SAS_OPEN_REJECT;
2073 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2074 break;
2075 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2076 PM8001_IO_DBG(pm8001_ha,
2077 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2078 ts->resp = SAS_TASK_COMPLETE;
2079 ts->stat = SAS_NAK_R_ERR;
2080 break;
2081 case IO_XFER_ERROR_DMA:
2082 PM8001_IO_DBG(pm8001_ha,
2083 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2084 ts->resp = SAS_TASK_COMPLETE;
2085 ts->stat = SAS_OPEN_REJECT;
2086 break;
2087 case IO_XFER_OPEN_RETRY_TIMEOUT:
2088 PM8001_IO_DBG(pm8001_ha,
2089 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2090 ts->resp = SAS_TASK_COMPLETE;
2091 ts->stat = SAS_OPEN_REJECT;
2092 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2093 break;
2094 case IO_XFER_ERROR_OFFSET_MISMATCH:
2095 PM8001_IO_DBG(pm8001_ha,
2096 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2097 ts->resp = SAS_TASK_COMPLETE;
2098 ts->stat = SAS_OPEN_REJECT;
2099 break;
2100 case IO_PORT_IN_RESET:
2101 PM8001_IO_DBG(pm8001_ha,
2102 pm8001_printk("IO_PORT_IN_RESET\n"));
2103 ts->resp = SAS_TASK_COMPLETE;
2104 ts->stat = SAS_OPEN_REJECT;
2105 break;
2106 case IO_DS_NON_OPERATIONAL:
2107 PM8001_IO_DBG(pm8001_ha,
2108 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2109 ts->resp = SAS_TASK_COMPLETE;
2110 ts->stat = SAS_OPEN_REJECT;
2111 if (!t->uldd_task)
2112 pm8001_handle_event(pm8001_ha,
2113 pm8001_dev,
2114 IO_DS_NON_OPERATIONAL);
2115 break;
2116 case IO_DS_IN_RECOVERY:
2117 PM8001_IO_DBG(pm8001_ha,
2118 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2119 ts->resp = SAS_TASK_COMPLETE;
2120 ts->stat = SAS_OPEN_REJECT;
2121 break;
2122 case IO_TM_TAG_NOT_FOUND:
2123 PM8001_IO_DBG(pm8001_ha,
2124 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
2125 ts->resp = SAS_TASK_COMPLETE;
2126 ts->stat = SAS_OPEN_REJECT;
2127 break;
2128 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2129 PM8001_IO_DBG(pm8001_ha,
2130 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
2131 ts->resp = SAS_TASK_COMPLETE;
2132 ts->stat = SAS_OPEN_REJECT;
2133 break;
2134 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2135 PM8001_IO_DBG(pm8001_ha,
2136 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2137 ts->resp = SAS_TASK_COMPLETE;
2138 ts->stat = SAS_OPEN_REJECT;
2139 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2140 break;
2141 default:
2142 PM8001_DEVIO_DBG(pm8001_ha,
2143 pm8001_printk("Unknown status 0x%x\n", status));
2144
2145 ts->resp = SAS_TASK_COMPLETE;
2146 ts->stat = SAS_OPEN_REJECT;
2147 break;
2148 }
2149 PM8001_IO_DBG(pm8001_ha,
2150 pm8001_printk("scsi_status = 0x%x\n ",
2151 psspPayload->ssp_resp_iu.status));
2152 spin_lock_irqsave(&t->task_state_lock, flags);
2153 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2154 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2155 t->task_state_flags |= SAS_TASK_STATE_DONE;
2156 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2157 spin_unlock_irqrestore(&t->task_state_lock, flags);
2158 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2159 "task 0x%p done with io_status 0x%x resp 0x%x "
2160 "stat 0x%x but aborted by upper layer!\n",
2161 t, status, ts->resp, ts->stat));
2162 if (t->slow_task)
2163 complete(&t->slow_task->completion);
2164 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2165 } else {
2166 spin_unlock_irqrestore(&t->task_state_lock, flags);
2167 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2168 mb();
2169 t->task_done(t);
2170 }
2171}
2172
2173
2174static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2175{
2176 struct sas_task *t;
2177 unsigned long flags;
2178 struct task_status_struct *ts;
2179 struct pm8001_ccb_info *ccb;
2180 struct pm8001_device *pm8001_dev;
2181 struct ssp_event_resp *psspPayload =
2182 (struct ssp_event_resp *)(piomb + 4);
2183 u32 event = le32_to_cpu(psspPayload->event);
2184 u32 tag = le32_to_cpu(psspPayload->tag);
2185 u32 port_id = le32_to_cpu(psspPayload->port_id);
2186
2187 ccb = &pm8001_ha->ccb_info[tag];
2188 t = ccb->task;
2189 pm8001_dev = ccb->device;
2190 if (event)
2191 PM8001_FAIL_DBG(pm8001_ha,
2192 pm8001_printk("sas IO status 0x%x\n", event));
2193 if (unlikely(!t || !t->lldd_task || !t->dev))
2194 return;
2195 ts = &t->task_status;
2196 PM8001_IOERR_DBG(pm8001_ha,
2197 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2198 port_id, tag, event));
2199 switch (event) {
2200 case IO_OVERFLOW:
2201 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
2202 ts->resp = SAS_TASK_COMPLETE;
2203 ts->stat = SAS_DATA_OVERRUN;
2204 ts->residual = 0;
2205 if (pm8001_dev)
2206 pm8001_dev->running_req--;
2207 break;
2208 case IO_XFER_ERROR_BREAK:
2209 PM8001_IO_DBG(pm8001_ha,
2210 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2211 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2212 return;
2213 case IO_XFER_ERROR_PHY_NOT_READY:
2214 PM8001_IO_DBG(pm8001_ha,
2215 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2216 ts->resp = SAS_TASK_COMPLETE;
2217 ts->stat = SAS_OPEN_REJECT;
2218 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2219 break;
2220 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2221 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2222 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2223 ts->resp = SAS_TASK_COMPLETE;
2224 ts->stat = SAS_OPEN_REJECT;
2225 ts->open_rej_reason = SAS_OREJ_EPROTO;
2226 break;
2227 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2228 PM8001_IO_DBG(pm8001_ha,
2229 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2230 ts->resp = SAS_TASK_COMPLETE;
2231 ts->stat = SAS_OPEN_REJECT;
2232 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2233 break;
2234 case IO_OPEN_CNX_ERROR_BREAK:
2235 PM8001_IO_DBG(pm8001_ha,
2236 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2237 ts->resp = SAS_TASK_COMPLETE;
2238 ts->stat = SAS_OPEN_REJECT;
2239 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2240 break;
2241 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2242 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2243 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2244 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2245 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2246 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2247 PM8001_IO_DBG(pm8001_ha,
2248 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2249 ts->resp = SAS_TASK_COMPLETE;
2250 ts->stat = SAS_OPEN_REJECT;
2251 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2252 if (!t->uldd_task)
2253 pm8001_handle_event(pm8001_ha,
2254 pm8001_dev,
2255 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2256 break;
2257 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2258 PM8001_IO_DBG(pm8001_ha,
2259 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2260 ts->resp = SAS_TASK_COMPLETE;
2261 ts->stat = SAS_OPEN_REJECT;
2262 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2263 break;
2264 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2265 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2266 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2267 ts->resp = SAS_TASK_COMPLETE;
2268 ts->stat = SAS_OPEN_REJECT;
2269 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2270 break;
2271 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2272 PM8001_IO_DBG(pm8001_ha,
2273 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2274 ts->resp = SAS_TASK_COMPLETE;
2275 ts->stat = SAS_OPEN_REJECT;
2276 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2277 break;
2278 case IO_XFER_ERROR_NAK_RECEIVED:
2279 PM8001_IO_DBG(pm8001_ha,
2280 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2281 ts->resp = SAS_TASK_COMPLETE;
2282 ts->stat = SAS_OPEN_REJECT;
2283 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2284 break;
2285 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2286 PM8001_IO_DBG(pm8001_ha,
2287 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2288 ts->resp = SAS_TASK_COMPLETE;
2289 ts->stat = SAS_NAK_R_ERR;
2290 break;
2291 case IO_XFER_OPEN_RETRY_TIMEOUT:
2292 PM8001_IO_DBG(pm8001_ha,
2293 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2294 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2295 return;
2296 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2297 PM8001_IO_DBG(pm8001_ha,
2298 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2299 ts->resp = SAS_TASK_COMPLETE;
2300 ts->stat = SAS_DATA_OVERRUN;
2301 break;
2302 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2303 PM8001_IO_DBG(pm8001_ha,
2304 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2305 ts->resp = SAS_TASK_COMPLETE;
2306 ts->stat = SAS_DATA_OVERRUN;
2307 break;
2308 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2309 PM8001_IO_DBG(pm8001_ha,
2310 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2311 ts->resp = SAS_TASK_COMPLETE;
2312 ts->stat = SAS_DATA_OVERRUN;
2313 break;
2314 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2315 PM8001_IO_DBG(pm8001_ha,
2316 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2317 ts->resp = SAS_TASK_COMPLETE;
2318 ts->stat = SAS_DATA_OVERRUN;
2319 break;
2320 case IO_XFER_ERROR_OFFSET_MISMATCH:
2321 PM8001_IO_DBG(pm8001_ha,
2322 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2323 ts->resp = SAS_TASK_COMPLETE;
2324 ts->stat = SAS_DATA_OVERRUN;
2325 break;
2326 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2327 PM8001_IO_DBG(pm8001_ha,
2328 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2329 ts->resp = SAS_TASK_COMPLETE;
2330 ts->stat = SAS_DATA_OVERRUN;
2331 break;
2332 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2333 PM8001_IOERR_DBG(pm8001_ha,
2334 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2335
2336 ts->resp = SAS_TASK_COMPLETE;
2337 ts->stat = SAS_DATA_OVERRUN;
2338 break;
2339 case IO_XFER_CMD_FRAME_ISSUED:
2340 PM8001_IO_DBG(pm8001_ha,
2341 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2342 return;
2343 default:
2344 PM8001_DEVIO_DBG(pm8001_ha,
2345 pm8001_printk("Unknown status 0x%x\n", event));
2346
2347 ts->resp = SAS_TASK_COMPLETE;
2348 ts->stat = SAS_DATA_OVERRUN;
2349 break;
2350 }
2351 spin_lock_irqsave(&t->task_state_lock, flags);
2352 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2353 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2354 t->task_state_flags |= SAS_TASK_STATE_DONE;
2355 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2356 spin_unlock_irqrestore(&t->task_state_lock, flags);
2357 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2358 "task 0x%p done with event 0x%x resp 0x%x "
2359 "stat 0x%x but aborted by upper layer!\n",
2360 t, event, ts->resp, ts->stat));
2361 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2362 } else {
2363 spin_unlock_irqrestore(&t->task_state_lock, flags);
2364 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2365 mb();
2366 t->task_done(t);
2367 }
2368}
2369
2370
2371static void
2372mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2373{
2374 struct sas_task *t;
2375 struct pm8001_ccb_info *ccb;
2376 u32 param;
2377 u32 status;
2378 u32 tag;
2379 int i, j;
2380 u8 sata_addr_low[4];
2381 u32 temp_sata_addr_low, temp_sata_addr_hi;
2382 u8 sata_addr_hi[4];
2383 struct sata_completion_resp *psataPayload;
2384 struct task_status_struct *ts;
2385 struct ata_task_resp *resp ;
2386 u32 *sata_resp;
2387 struct pm8001_device *pm8001_dev;
2388 unsigned long flags;
2389
2390 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2391 status = le32_to_cpu(psataPayload->status);
2392 tag = le32_to_cpu(psataPayload->tag);
2393
2394 if (!tag) {
2395 PM8001_FAIL_DBG(pm8001_ha,
2396 pm8001_printk("tag null\n"));
2397 return;
2398 }
2399 ccb = &pm8001_ha->ccb_info[tag];
2400 param = le32_to_cpu(psataPayload->param);
2401 if (ccb) {
2402 t = ccb->task;
2403 pm8001_dev = ccb->device;
2404 } else {
2405 PM8001_FAIL_DBG(pm8001_ha,
2406 pm8001_printk("ccb null\n"));
2407 return;
2408 }
2409
2410 if (t) {
2411 if (t->dev && (t->dev->lldd_dev))
2412 pm8001_dev = t->dev->lldd_dev;
2413 } else {
2414 PM8001_FAIL_DBG(pm8001_ha,
2415 pm8001_printk("task null\n"));
2416 return;
2417 }
2418
2419 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2420 && unlikely(!t || !t->lldd_task || !t->dev)) {
2421 PM8001_FAIL_DBG(pm8001_ha,
2422 pm8001_printk("task or dev null\n"));
2423 return;
2424 }
2425
2426 ts = &t->task_status;
2427 if (!ts) {
2428 PM8001_FAIL_DBG(pm8001_ha,
2429 pm8001_printk("ts null\n"));
2430 return;
2431 }
2432
2433 if (unlikely(status))
2434 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
2435 "status:0x%x, tag:0x%x, task::0x%p\n",
2436 status, tag, t));
2437
2438
2439 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2440 (status != IO_UNDERFLOW)) {
2441 if (!((t->dev->parent) &&
2442 (dev_is_expander(t->dev->parent->dev_type)))) {
2443 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2444 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2445 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2446 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2447 memcpy(&temp_sata_addr_low, sata_addr_low,
2448 sizeof(sata_addr_low));
2449 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2450 sizeof(sata_addr_hi));
2451 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2452 |((temp_sata_addr_hi << 8) &
2453 0xff0000) |
2454 ((temp_sata_addr_hi >> 8)
2455 & 0xff00) |
2456 ((temp_sata_addr_hi << 24) &
2457 0xff000000));
2458 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2459 & 0xff) |
2460 ((temp_sata_addr_low << 8)
2461 & 0xff0000) |
2462 ((temp_sata_addr_low >> 8)
2463 & 0xff00) |
2464 ((temp_sata_addr_low << 24)
2465 & 0xff000000)) +
2466 pm8001_dev->attached_phy +
2467 0x10);
2468 PM8001_FAIL_DBG(pm8001_ha,
2469 pm8001_printk("SAS Address of IO Failure Drive:"
2470 "%08x%08x", temp_sata_addr_hi,
2471 temp_sata_addr_low));
2472
2473 } else {
2474 PM8001_FAIL_DBG(pm8001_ha,
2475 pm8001_printk("SAS Address of IO Failure Drive:"
2476 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2477 }
2478 }
2479 switch (status) {
2480 case IO_SUCCESS:
2481 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2482 if (param == 0) {
2483 ts->resp = SAS_TASK_COMPLETE;
2484 ts->stat = SAM_STAT_GOOD;
2485
2486 if (pm8001_dev &&
2487 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2488
2489 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2490
2491 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2492 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2493
2494 pm8001_tag_free(pm8001_ha, tag);
2495 sas_free_task(t);
2496 return;
2497 }
2498 } else {
2499 u8 len;
2500 ts->resp = SAS_TASK_COMPLETE;
2501 ts->stat = SAS_PROTO_RESPONSE;
2502 ts->residual = param;
2503 PM8001_IO_DBG(pm8001_ha,
2504 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2505 param));
2506 sata_resp = &psataPayload->sata_resp[0];
2507 resp = (struct ata_task_resp *)ts->buf;
2508 if (t->ata_task.dma_xfer == 0 &&
2509 t->data_dir == DMA_FROM_DEVICE) {
2510 len = sizeof(struct pio_setup_fis);
2511 PM8001_IO_DBG(pm8001_ha,
2512 pm8001_printk("PIO read len = %d\n", len));
2513 } else if (t->ata_task.use_ncq) {
2514 len = sizeof(struct set_dev_bits_fis);
2515 PM8001_IO_DBG(pm8001_ha,
2516 pm8001_printk("FPDMA len = %d\n", len));
2517 } else {
2518 len = sizeof(struct dev_to_host_fis);
2519 PM8001_IO_DBG(pm8001_ha,
2520 pm8001_printk("other len = %d\n", len));
2521 }
2522 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2523 resp->frame_len = len;
2524 memcpy(&resp->ending_fis[0], sata_resp, len);
2525 ts->buf_valid_size = sizeof(*resp);
2526 } else
2527 PM8001_IO_DBG(pm8001_ha,
2528 pm8001_printk("response too large\n"));
2529 }
2530 if (pm8001_dev)
2531 pm8001_dev->running_req--;
2532 break;
2533 case IO_ABORTED:
2534 PM8001_IO_DBG(pm8001_ha,
2535 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2536 ts->resp = SAS_TASK_COMPLETE;
2537 ts->stat = SAS_ABORTED_TASK;
2538 if (pm8001_dev)
2539 pm8001_dev->running_req--;
2540 break;
2541
2542 case IO_UNDERFLOW:
2543
2544 PM8001_IO_DBG(pm8001_ha,
2545 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2546 ts->resp = SAS_TASK_COMPLETE;
2547 ts->stat = SAS_DATA_UNDERRUN;
2548 ts->residual = param;
2549 if (pm8001_dev)
2550 pm8001_dev->running_req--;
2551 break;
2552 case IO_NO_DEVICE:
2553 PM8001_IO_DBG(pm8001_ha,
2554 pm8001_printk("IO_NO_DEVICE\n"));
2555 ts->resp = SAS_TASK_UNDELIVERED;
2556 ts->stat = SAS_PHY_DOWN;
2557 break;
2558 case IO_XFER_ERROR_BREAK:
2559 PM8001_IO_DBG(pm8001_ha,
2560 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2561 ts->resp = SAS_TASK_COMPLETE;
2562 ts->stat = SAS_INTERRUPTED;
2563 break;
2564 case IO_XFER_ERROR_PHY_NOT_READY:
2565 PM8001_IO_DBG(pm8001_ha,
2566 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2567 ts->resp = SAS_TASK_COMPLETE;
2568 ts->stat = SAS_OPEN_REJECT;
2569 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2570 break;
2571 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2572 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2573 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2574 ts->resp = SAS_TASK_COMPLETE;
2575 ts->stat = SAS_OPEN_REJECT;
2576 ts->open_rej_reason = SAS_OREJ_EPROTO;
2577 break;
2578 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2579 PM8001_IO_DBG(pm8001_ha,
2580 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2581 ts->resp = SAS_TASK_COMPLETE;
2582 ts->stat = SAS_OPEN_REJECT;
2583 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2584 break;
2585 case IO_OPEN_CNX_ERROR_BREAK:
2586 PM8001_IO_DBG(pm8001_ha,
2587 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2588 ts->resp = SAS_TASK_COMPLETE;
2589 ts->stat = SAS_OPEN_REJECT;
2590 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2591 break;
2592 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2593 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2594 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2595 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2596 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2597 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2598 PM8001_IO_DBG(pm8001_ha,
2599 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2600 ts->resp = SAS_TASK_COMPLETE;
2601 ts->stat = SAS_DEV_NO_RESPONSE;
2602 if (!t->uldd_task) {
2603 pm8001_handle_event(pm8001_ha,
2604 pm8001_dev,
2605 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2606 ts->resp = SAS_TASK_UNDELIVERED;
2607 ts->stat = SAS_QUEUE_FULL;
2608 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2609 return;
2610 }
2611 break;
2612 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2613 PM8001_IO_DBG(pm8001_ha,
2614 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2615 ts->resp = SAS_TASK_UNDELIVERED;
2616 ts->stat = SAS_OPEN_REJECT;
2617 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2618 if (!t->uldd_task) {
2619 pm8001_handle_event(pm8001_ha,
2620 pm8001_dev,
2621 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2622 ts->resp = SAS_TASK_UNDELIVERED;
2623 ts->stat = SAS_QUEUE_FULL;
2624 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2625 return;
2626 }
2627 break;
2628 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2629 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2630 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2631 ts->resp = SAS_TASK_COMPLETE;
2632 ts->stat = SAS_OPEN_REJECT;
2633 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2634 break;
2635 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2636 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2637 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2638 ts->resp = SAS_TASK_COMPLETE;
2639 ts->stat = SAS_DEV_NO_RESPONSE;
2640 if (!t->uldd_task) {
2641 pm8001_handle_event(pm8001_ha,
2642 pm8001_dev,
2643 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2644 ts->resp = SAS_TASK_UNDELIVERED;
2645 ts->stat = SAS_QUEUE_FULL;
2646 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2647 return;
2648 }
2649 break;
2650 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2651 PM8001_IO_DBG(pm8001_ha,
2652 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2653 ts->resp = SAS_TASK_COMPLETE;
2654 ts->stat = SAS_OPEN_REJECT;
2655 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2656 break;
2657 case IO_XFER_ERROR_NAK_RECEIVED:
2658 PM8001_IO_DBG(pm8001_ha,
2659 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2660 ts->resp = SAS_TASK_COMPLETE;
2661 ts->stat = SAS_NAK_R_ERR;
2662 break;
2663 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2664 PM8001_IO_DBG(pm8001_ha,
2665 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2666 ts->resp = SAS_TASK_COMPLETE;
2667 ts->stat = SAS_NAK_R_ERR;
2668 break;
2669 case IO_XFER_ERROR_DMA:
2670 PM8001_IO_DBG(pm8001_ha,
2671 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2672 ts->resp = SAS_TASK_COMPLETE;
2673 ts->stat = SAS_ABORTED_TASK;
2674 break;
2675 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2676 PM8001_IO_DBG(pm8001_ha,
2677 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2678 ts->resp = SAS_TASK_UNDELIVERED;
2679 ts->stat = SAS_DEV_NO_RESPONSE;
2680 break;
2681 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2682 PM8001_IO_DBG(pm8001_ha,
2683 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2684 ts->resp = SAS_TASK_COMPLETE;
2685 ts->stat = SAS_DATA_UNDERRUN;
2686 break;
2687 case IO_XFER_OPEN_RETRY_TIMEOUT:
2688 PM8001_IO_DBG(pm8001_ha,
2689 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2690 ts->resp = SAS_TASK_COMPLETE;
2691 ts->stat = SAS_OPEN_TO;
2692 break;
2693 case IO_PORT_IN_RESET:
2694 PM8001_IO_DBG(pm8001_ha,
2695 pm8001_printk("IO_PORT_IN_RESET\n"));
2696 ts->resp = SAS_TASK_COMPLETE;
2697 ts->stat = SAS_DEV_NO_RESPONSE;
2698 break;
2699 case IO_DS_NON_OPERATIONAL:
2700 PM8001_IO_DBG(pm8001_ha,
2701 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2702 ts->resp = SAS_TASK_COMPLETE;
2703 ts->stat = SAS_DEV_NO_RESPONSE;
2704 if (!t->uldd_task) {
2705 pm8001_handle_event(pm8001_ha, pm8001_dev,
2706 IO_DS_NON_OPERATIONAL);
2707 ts->resp = SAS_TASK_UNDELIVERED;
2708 ts->stat = SAS_QUEUE_FULL;
2709 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2710 return;
2711 }
2712 break;
2713 case IO_DS_IN_RECOVERY:
2714 PM8001_IO_DBG(pm8001_ha,
2715 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2716 ts->resp = SAS_TASK_COMPLETE;
2717 ts->stat = SAS_DEV_NO_RESPONSE;
2718 break;
2719 case IO_DS_IN_ERROR:
2720 PM8001_IO_DBG(pm8001_ha,
2721 pm8001_printk("IO_DS_IN_ERROR\n"));
2722 ts->resp = SAS_TASK_COMPLETE;
2723 ts->stat = SAS_DEV_NO_RESPONSE;
2724 if (!t->uldd_task) {
2725 pm8001_handle_event(pm8001_ha, pm8001_dev,
2726 IO_DS_IN_ERROR);
2727 ts->resp = SAS_TASK_UNDELIVERED;
2728 ts->stat = SAS_QUEUE_FULL;
2729 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2730 return;
2731 }
2732 break;
2733 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2734 PM8001_IO_DBG(pm8001_ha,
2735 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2736 ts->resp = SAS_TASK_COMPLETE;
2737 ts->stat = SAS_OPEN_REJECT;
2738 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2739 break;
2740 default:
2741 PM8001_DEVIO_DBG(pm8001_ha,
2742 pm8001_printk("Unknown status 0x%x\n", status));
2743
2744 ts->resp = SAS_TASK_COMPLETE;
2745 ts->stat = SAS_DEV_NO_RESPONSE;
2746 break;
2747 }
2748 spin_lock_irqsave(&t->task_state_lock, flags);
2749 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2750 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2751 t->task_state_flags |= SAS_TASK_STATE_DONE;
2752 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2753 spin_unlock_irqrestore(&t->task_state_lock, flags);
2754 PM8001_FAIL_DBG(pm8001_ha,
2755 pm8001_printk("task 0x%p done with io_status 0x%x"
2756 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2757 t, status, ts->resp, ts->stat));
2758 if (t->slow_task)
2759 complete(&t->slow_task->completion);
2760 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2761 } else {
2762 spin_unlock_irqrestore(&t->task_state_lock, flags);
2763 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2764 }
2765}
2766
2767
2768static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2769{
2770 struct sas_task *t;
2771 struct task_status_struct *ts;
2772 struct pm8001_ccb_info *ccb;
2773 struct pm8001_device *pm8001_dev;
2774 struct sata_event_resp *psataPayload =
2775 (struct sata_event_resp *)(piomb + 4);
2776 u32 event = le32_to_cpu(psataPayload->event);
2777 u32 tag = le32_to_cpu(psataPayload->tag);
2778 u32 port_id = le32_to_cpu(psataPayload->port_id);
2779 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2780 unsigned long flags;
2781
2782 ccb = &pm8001_ha->ccb_info[tag];
2783
2784 if (ccb) {
2785 t = ccb->task;
2786 pm8001_dev = ccb->device;
2787 } else {
2788 PM8001_FAIL_DBG(pm8001_ha,
2789 pm8001_printk("No CCB !!!. returning\n"));
2790 return;
2791 }
2792 if (event)
2793 PM8001_FAIL_DBG(pm8001_ha,
2794 pm8001_printk("SATA EVENT 0x%x\n", event));
2795
2796
2797 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2798
2799 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2800
2801 if (pm8001_dev)
2802 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2803 return;
2804 }
2805
2806 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2807 PM8001_FAIL_DBG(pm8001_ha,
2808 pm8001_printk("task or dev null\n"));
2809 return;
2810 }
2811
2812 ts = &t->task_status;
2813 PM8001_IOERR_DBG(pm8001_ha,
2814 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2815 port_id, tag, event));
2816 switch (event) {
2817 case IO_OVERFLOW:
2818 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2819 ts->resp = SAS_TASK_COMPLETE;
2820 ts->stat = SAS_DATA_OVERRUN;
2821 ts->residual = 0;
2822 if (pm8001_dev)
2823 pm8001_dev->running_req--;
2824 break;
2825 case IO_XFER_ERROR_BREAK:
2826 PM8001_IO_DBG(pm8001_ha,
2827 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2828 ts->resp = SAS_TASK_COMPLETE;
2829 ts->stat = SAS_INTERRUPTED;
2830 break;
2831 case IO_XFER_ERROR_PHY_NOT_READY:
2832 PM8001_IO_DBG(pm8001_ha,
2833 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2834 ts->resp = SAS_TASK_COMPLETE;
2835 ts->stat = SAS_OPEN_REJECT;
2836 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2837 break;
2838 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2839 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2840 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2841 ts->resp = SAS_TASK_COMPLETE;
2842 ts->stat = SAS_OPEN_REJECT;
2843 ts->open_rej_reason = SAS_OREJ_EPROTO;
2844 break;
2845 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2846 PM8001_IO_DBG(pm8001_ha,
2847 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2848 ts->resp = SAS_TASK_COMPLETE;
2849 ts->stat = SAS_OPEN_REJECT;
2850 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2851 break;
2852 case IO_OPEN_CNX_ERROR_BREAK:
2853 PM8001_IO_DBG(pm8001_ha,
2854 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2855 ts->resp = SAS_TASK_COMPLETE;
2856 ts->stat = SAS_OPEN_REJECT;
2857 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2858 break;
2859 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2860 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2861 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2862 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2863 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2864 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2865 PM8001_FAIL_DBG(pm8001_ha,
2866 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2867 ts->resp = SAS_TASK_UNDELIVERED;
2868 ts->stat = SAS_DEV_NO_RESPONSE;
2869 if (!t->uldd_task) {
2870 pm8001_handle_event(pm8001_ha,
2871 pm8001_dev,
2872 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2873 ts->resp = SAS_TASK_COMPLETE;
2874 ts->stat = SAS_QUEUE_FULL;
2875 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2876 return;
2877 }
2878 break;
2879 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2880 PM8001_IO_DBG(pm8001_ha,
2881 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2882 ts->resp = SAS_TASK_UNDELIVERED;
2883 ts->stat = SAS_OPEN_REJECT;
2884 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2885 break;
2886 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2887 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2888 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2889 ts->resp = SAS_TASK_COMPLETE;
2890 ts->stat = SAS_OPEN_REJECT;
2891 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2892 break;
2893 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2894 PM8001_IO_DBG(pm8001_ha,
2895 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2896 ts->resp = SAS_TASK_COMPLETE;
2897 ts->stat = SAS_OPEN_REJECT;
2898 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2899 break;
2900 case IO_XFER_ERROR_NAK_RECEIVED:
2901 PM8001_IO_DBG(pm8001_ha,
2902 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2903 ts->resp = SAS_TASK_COMPLETE;
2904 ts->stat = SAS_NAK_R_ERR;
2905 break;
2906 case IO_XFER_ERROR_PEER_ABORTED:
2907 PM8001_IO_DBG(pm8001_ha,
2908 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2909 ts->resp = SAS_TASK_COMPLETE;
2910 ts->stat = SAS_NAK_R_ERR;
2911 break;
2912 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2913 PM8001_IO_DBG(pm8001_ha,
2914 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2915 ts->resp = SAS_TASK_COMPLETE;
2916 ts->stat = SAS_DATA_UNDERRUN;
2917 break;
2918 case IO_XFER_OPEN_RETRY_TIMEOUT:
2919 PM8001_IO_DBG(pm8001_ha,
2920 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2921 ts->resp = SAS_TASK_COMPLETE;
2922 ts->stat = SAS_OPEN_TO;
2923 break;
2924 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2925 PM8001_IO_DBG(pm8001_ha,
2926 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2927 ts->resp = SAS_TASK_COMPLETE;
2928 ts->stat = SAS_OPEN_TO;
2929 break;
2930 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2931 PM8001_IO_DBG(pm8001_ha,
2932 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2933 ts->resp = SAS_TASK_COMPLETE;
2934 ts->stat = SAS_OPEN_TO;
2935 break;
2936 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2937 PM8001_IO_DBG(pm8001_ha,
2938 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2939 ts->resp = SAS_TASK_COMPLETE;
2940 ts->stat = SAS_OPEN_TO;
2941 break;
2942 case IO_XFER_ERROR_OFFSET_MISMATCH:
2943 PM8001_IO_DBG(pm8001_ha,
2944 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2945 ts->resp = SAS_TASK_COMPLETE;
2946 ts->stat = SAS_OPEN_TO;
2947 break;
2948 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2949 PM8001_IO_DBG(pm8001_ha,
2950 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2951 ts->resp = SAS_TASK_COMPLETE;
2952 ts->stat = SAS_OPEN_TO;
2953 break;
2954 case IO_XFER_CMD_FRAME_ISSUED:
2955 PM8001_IO_DBG(pm8001_ha,
2956 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2957 break;
2958 case IO_XFER_PIO_SETUP_ERROR:
2959 PM8001_IO_DBG(pm8001_ha,
2960 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2961 ts->resp = SAS_TASK_COMPLETE;
2962 ts->stat = SAS_OPEN_TO;
2963 break;
2964 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2965 PM8001_FAIL_DBG(pm8001_ha,
2966 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2967
2968 ts->resp = SAS_TASK_COMPLETE;
2969 ts->stat = SAS_OPEN_TO;
2970 break;
2971 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2972 PM8001_FAIL_DBG(pm8001_ha,
2973 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2974
2975 ts->resp = SAS_TASK_COMPLETE;
2976 ts->stat = SAS_OPEN_TO;
2977 break;
2978 default:
2979 PM8001_IO_DBG(pm8001_ha,
2980 pm8001_printk("Unknown status 0x%x\n", event));
2981
2982 ts->resp = SAS_TASK_COMPLETE;
2983 ts->stat = SAS_OPEN_TO;
2984 break;
2985 }
2986 spin_lock_irqsave(&t->task_state_lock, flags);
2987 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2988 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2989 t->task_state_flags |= SAS_TASK_STATE_DONE;
2990 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2991 spin_unlock_irqrestore(&t->task_state_lock, flags);
2992 PM8001_FAIL_DBG(pm8001_ha,
2993 pm8001_printk("task 0x%p done with io_status 0x%x"
2994 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2995 t, event, ts->resp, ts->stat));
2996 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2997 } else {
2998 spin_unlock_irqrestore(&t->task_state_lock, flags);
2999 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
3000 }
3001}
3002
3003
3004static void
3005mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
3006{
3007 u32 param, i;
3008 struct sas_task *t;
3009 struct pm8001_ccb_info *ccb;
3010 unsigned long flags;
3011 u32 status;
3012 u32 tag;
3013 struct smp_completion_resp *psmpPayload;
3014 struct task_status_struct *ts;
3015 struct pm8001_device *pm8001_dev;
3016 char *pdma_respaddr = NULL;
3017
3018 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
3019 status = le32_to_cpu(psmpPayload->status);
3020 tag = le32_to_cpu(psmpPayload->tag);
3021
3022 ccb = &pm8001_ha->ccb_info[tag];
3023 param = le32_to_cpu(psmpPayload->param);
3024 t = ccb->task;
3025 ts = &t->task_status;
3026 pm8001_dev = ccb->device;
3027 if (status)
3028 PM8001_FAIL_DBG(pm8001_ha,
3029 pm8001_printk("smp IO status 0x%x\n", status));
3030 if (unlikely(!t || !t->lldd_task || !t->dev))
3031 return;
3032
3033 PM8001_DEV_DBG(pm8001_ha,
3034 pm8001_printk("tag::0x%x status::0x%x\n", tag, status));
3035
3036 switch (status) {
3037
3038 case IO_SUCCESS:
3039 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3040 ts->resp = SAS_TASK_COMPLETE;
3041 ts->stat = SAM_STAT_GOOD;
3042 if (pm8001_dev)
3043 pm8001_dev->running_req--;
3044 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3045 PM8001_IO_DBG(pm8001_ha,
3046 pm8001_printk("DIRECT RESPONSE Length:%d\n",
3047 param));
3048 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
3049 ((u64)sg_dma_address
3050 (&t->smp_task.smp_resp))));
3051 for (i = 0; i < param; i++) {
3052 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
3053 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3054 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3055 i, *(pdma_respaddr+i),
3056 psmpPayload->_r_a[i]));
3057 }
3058 }
3059 break;
3060 case IO_ABORTED:
3061 PM8001_IO_DBG(pm8001_ha,
3062 pm8001_printk("IO_ABORTED IOMB\n"));
3063 ts->resp = SAS_TASK_COMPLETE;
3064 ts->stat = SAS_ABORTED_TASK;
3065 if (pm8001_dev)
3066 pm8001_dev->running_req--;
3067 break;
3068 case IO_OVERFLOW:
3069 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
3070 ts->resp = SAS_TASK_COMPLETE;
3071 ts->stat = SAS_DATA_OVERRUN;
3072 ts->residual = 0;
3073 if (pm8001_dev)
3074 pm8001_dev->running_req--;
3075 break;
3076 case IO_NO_DEVICE:
3077 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
3078 ts->resp = SAS_TASK_COMPLETE;
3079 ts->stat = SAS_PHY_DOWN;
3080 break;
3081 case IO_ERROR_HW_TIMEOUT:
3082 PM8001_IO_DBG(pm8001_ha,
3083 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
3084 ts->resp = SAS_TASK_COMPLETE;
3085 ts->stat = SAM_STAT_BUSY;
3086 break;
3087 case IO_XFER_ERROR_BREAK:
3088 PM8001_IO_DBG(pm8001_ha,
3089 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
3090 ts->resp = SAS_TASK_COMPLETE;
3091 ts->stat = SAM_STAT_BUSY;
3092 break;
3093 case IO_XFER_ERROR_PHY_NOT_READY:
3094 PM8001_IO_DBG(pm8001_ha,
3095 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
3096 ts->resp = SAS_TASK_COMPLETE;
3097 ts->stat = SAM_STAT_BUSY;
3098 break;
3099 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3100 PM8001_IO_DBG(pm8001_ha,
3101 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
3102 ts->resp = SAS_TASK_COMPLETE;
3103 ts->stat = SAS_OPEN_REJECT;
3104 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3105 break;
3106 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3107 PM8001_IO_DBG(pm8001_ha,
3108 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
3109 ts->resp = SAS_TASK_COMPLETE;
3110 ts->stat = SAS_OPEN_REJECT;
3111 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3112 break;
3113 case IO_OPEN_CNX_ERROR_BREAK:
3114 PM8001_IO_DBG(pm8001_ha,
3115 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
3116 ts->resp = SAS_TASK_COMPLETE;
3117 ts->stat = SAS_OPEN_REJECT;
3118 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3119 break;
3120 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3121 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3122 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3123 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3124 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3125 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3126 PM8001_IO_DBG(pm8001_ha,
3127 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
3128 ts->resp = SAS_TASK_COMPLETE;
3129 ts->stat = SAS_OPEN_REJECT;
3130 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3131 pm8001_handle_event(pm8001_ha,
3132 pm8001_dev,
3133 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3134 break;
3135 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3136 PM8001_IO_DBG(pm8001_ha,
3137 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
3138 ts->resp = SAS_TASK_COMPLETE;
3139 ts->stat = SAS_OPEN_REJECT;
3140 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3141 break;
3142 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3143 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
3144 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
3145 ts->resp = SAS_TASK_COMPLETE;
3146 ts->stat = SAS_OPEN_REJECT;
3147 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3148 break;
3149 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3150 PM8001_IO_DBG(pm8001_ha,
3151 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
3152 ts->resp = SAS_TASK_COMPLETE;
3153 ts->stat = SAS_OPEN_REJECT;
3154 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3155 break;
3156 case IO_XFER_ERROR_RX_FRAME:
3157 PM8001_IO_DBG(pm8001_ha,
3158 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
3159 ts->resp = SAS_TASK_COMPLETE;
3160 ts->stat = SAS_DEV_NO_RESPONSE;
3161 break;
3162 case IO_XFER_OPEN_RETRY_TIMEOUT:
3163 PM8001_IO_DBG(pm8001_ha,
3164 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
3165 ts->resp = SAS_TASK_COMPLETE;
3166 ts->stat = SAS_OPEN_REJECT;
3167 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3168 break;
3169 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3170 PM8001_IO_DBG(pm8001_ha,
3171 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
3172 ts->resp = SAS_TASK_COMPLETE;
3173 ts->stat = SAS_QUEUE_FULL;
3174 break;
3175 case IO_PORT_IN_RESET:
3176 PM8001_IO_DBG(pm8001_ha,
3177 pm8001_printk("IO_PORT_IN_RESET\n"));
3178 ts->resp = SAS_TASK_COMPLETE;
3179 ts->stat = SAS_OPEN_REJECT;
3180 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3181 break;
3182 case IO_DS_NON_OPERATIONAL:
3183 PM8001_IO_DBG(pm8001_ha,
3184 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
3185 ts->resp = SAS_TASK_COMPLETE;
3186 ts->stat = SAS_DEV_NO_RESPONSE;
3187 break;
3188 case IO_DS_IN_RECOVERY:
3189 PM8001_IO_DBG(pm8001_ha,
3190 pm8001_printk("IO_DS_IN_RECOVERY\n"));
3191 ts->resp = SAS_TASK_COMPLETE;
3192 ts->stat = SAS_OPEN_REJECT;
3193 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3194 break;
3195 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3196 PM8001_IO_DBG(pm8001_ha,
3197 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
3198 ts->resp = SAS_TASK_COMPLETE;
3199 ts->stat = SAS_OPEN_REJECT;
3200 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3201 break;
3202 default:
3203 PM8001_DEVIO_DBG(pm8001_ha,
3204 pm8001_printk("Unknown status 0x%x\n", status));
3205 ts->resp = SAS_TASK_COMPLETE;
3206 ts->stat = SAS_DEV_NO_RESPONSE;
3207
3208 break;
3209 }
3210 spin_lock_irqsave(&t->task_state_lock, flags);
3211 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3212 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3213 t->task_state_flags |= SAS_TASK_STATE_DONE;
3214 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3215 spin_unlock_irqrestore(&t->task_state_lock, flags);
3216 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3217 "task 0x%p done with io_status 0x%x resp 0x%x"
3218 "stat 0x%x but aborted by upper layer!\n",
3219 t, status, ts->resp, ts->stat));
3220 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3221 } else {
3222 spin_unlock_irqrestore(&t->task_state_lock, flags);
3223 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3224 mb();
3225 t->task_done(t);
3226 }
3227}
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3240 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3241{
3242 struct hw_event_ack_req payload;
3243 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3244
3245 struct inbound_queue_table *circularQ;
3246
3247 memset((u8 *)&payload, 0, sizeof(payload));
3248 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3249 payload.tag = cpu_to_le32(1);
3250 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3251 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3252 payload.param0 = cpu_to_le32(param0);
3253 payload.param1 = cpu_to_le32(param1);
3254 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3255 sizeof(payload), 0);
3256}
3257
3258static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3259 u32 phyId, u32 phy_op);
3260
3261static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3262 void *piomb)
3263{
3264 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3265 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3266 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3267 u32 lr_status_evt_portid =
3268 le32_to_cpu(pPayload->lr_status_evt_portid);
3269 u8 deviceType = pPayload->sas_identify.dev_type;
3270 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3271 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3272 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3273 struct pm8001_port *port = &pm8001_ha->port[port_id];
3274
3275 if (deviceType == SAS_END_DEVICE) {
3276 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3277 PHY_NOTIFY_ENABLE_SPINUP);
3278 }
3279
3280 port->wide_port_phymap |= (1U << phy_id);
3281 pm8001_get_lrate_mode(phy, link_rate);
3282 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3283 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3284 phy->phy_attached = 1;
3285}
3286
3287
3288
3289
3290
3291
3292static void
3293hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3294{
3295 struct hw_event_resp *pPayload =
3296 (struct hw_event_resp *)(piomb + 4);
3297 u32 lr_status_evt_portid =
3298 le32_to_cpu(pPayload->lr_status_evt_portid);
3299 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3300
3301 u8 link_rate =
3302 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3303 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3304 u8 phy_id =
3305 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3306 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3307
3308 struct pm8001_port *port = &pm8001_ha->port[port_id];
3309 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3310 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3311 unsigned long flags;
3312 u8 deviceType = pPayload->sas_identify.dev_type;
3313 port->port_state = portstate;
3314 port->wide_port_phymap |= (1U << phy_id);
3315 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3316 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3317 "portid:%d; phyid:%d; linkrate:%d; "
3318 "portstate:%x; devicetype:%x\n",
3319 port_id, phy_id, link_rate, portstate, deviceType));
3320
3321 switch (deviceType) {
3322 case SAS_PHY_UNUSED:
3323 PM8001_MSG_DBG(pm8001_ha,
3324 pm8001_printk("device type no device.\n"));
3325 break;
3326 case SAS_END_DEVICE:
3327 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3328 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3329 PHY_NOTIFY_ENABLE_SPINUP);
3330 port->port_attached = 1;
3331 pm8001_get_lrate_mode(phy, link_rate);
3332 break;
3333 case SAS_EDGE_EXPANDER_DEVICE:
3334 PM8001_MSG_DBG(pm8001_ha,
3335 pm8001_printk("expander device.\n"));
3336 port->port_attached = 1;
3337 pm8001_get_lrate_mode(phy, link_rate);
3338 break;
3339 case SAS_FANOUT_EXPANDER_DEVICE:
3340 PM8001_MSG_DBG(pm8001_ha,
3341 pm8001_printk("fanout expander device.\n"));
3342 port->port_attached = 1;
3343 pm8001_get_lrate_mode(phy, link_rate);
3344 break;
3345 default:
3346 PM8001_DEVIO_DBG(pm8001_ha,
3347 pm8001_printk("unknown device type(%x)\n", deviceType));
3348 break;
3349 }
3350 phy->phy_type |= PORT_TYPE_SAS;
3351 phy->identify.device_type = deviceType;
3352 phy->phy_attached = 1;
3353 if (phy->identify.device_type == SAS_END_DEVICE)
3354 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3355 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3356 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3357 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3358 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3359 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3360 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3361 sizeof(struct sas_identify_frame)-4);
3362 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3363 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3364 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3365 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3366 msleep(200);
3367 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3368}
3369
3370
3371
3372
3373
3374
3375static void
3376hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3377{
3378 struct hw_event_resp *pPayload =
3379 (struct hw_event_resp *)(piomb + 4);
3380 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3381 u32 lr_status_evt_portid =
3382 le32_to_cpu(pPayload->lr_status_evt_portid);
3383 u8 link_rate =
3384 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3385 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3386 u8 phy_id =
3387 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3388
3389 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3390
3391 struct pm8001_port *port = &pm8001_ha->port[port_id];
3392 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3393 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3394 unsigned long flags;
3395 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
3396 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3397 port_id, phy_id, link_rate, portstate));
3398
3399 port->port_state = portstate;
3400 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3401 port->port_attached = 1;
3402 pm8001_get_lrate_mode(phy, link_rate);
3403 phy->phy_type |= PORT_TYPE_SATA;
3404 phy->phy_attached = 1;
3405 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3406 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3407 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3408 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3409 sizeof(struct dev_to_host_fis));
3410 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3411 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3412 phy->identify.device_type = SAS_SATA_DEV;
3413 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3414 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3415 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3416}
3417
3418
3419
3420
3421
3422
3423static void
3424hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3425{
3426 struct hw_event_resp *pPayload =
3427 (struct hw_event_resp *)(piomb + 4);
3428
3429 u32 lr_status_evt_portid =
3430 le32_to_cpu(pPayload->lr_status_evt_portid);
3431 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3432 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3433 u8 phy_id =
3434 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3435 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3436
3437 struct pm8001_port *port = &pm8001_ha->port[port_id];
3438 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3439 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3440 port->port_state = portstate;
3441 phy->identify.device_type = 0;
3442 phy->phy_attached = 0;
3443 switch (portstate) {
3444 case PORT_VALID:
3445 break;
3446 case PORT_INVALID:
3447 PM8001_MSG_DBG(pm8001_ha,
3448 pm8001_printk(" PortInvalid portID %d\n", port_id));
3449 PM8001_MSG_DBG(pm8001_ha,
3450 pm8001_printk(" Last phy Down and port invalid\n"));
3451 if (port_sata) {
3452 phy->phy_type = 0;
3453 port->port_attached = 0;
3454 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3455 port_id, phy_id, 0, 0);
3456 }
3457 sas_phy_disconnected(&phy->sas_phy);
3458 break;
3459 case PORT_IN_RESET:
3460 PM8001_MSG_DBG(pm8001_ha,
3461 pm8001_printk(" Port In Reset portID %d\n", port_id));
3462 break;
3463 case PORT_NOT_ESTABLISHED:
3464 PM8001_MSG_DBG(pm8001_ha,
3465 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
3466 port->port_attached = 0;
3467 break;
3468 case PORT_LOSTCOMM:
3469 PM8001_MSG_DBG(pm8001_ha,
3470 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
3471 PM8001_MSG_DBG(pm8001_ha,
3472 pm8001_printk(" Last phy Down and port invalid\n"));
3473 if (port_sata) {
3474 port->port_attached = 0;
3475 phy->phy_type = 0;
3476 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3477 port_id, phy_id, 0, 0);
3478 }
3479 sas_phy_disconnected(&phy->sas_phy);
3480 break;
3481 default:
3482 port->port_attached = 0;
3483 PM8001_DEVIO_DBG(pm8001_ha,
3484 pm8001_printk(" Phy Down and(default) = 0x%x\n",
3485 portstate));
3486 break;
3487
3488 }
3489 if (port_sata && (portstate != PORT_IN_RESET)) {
3490 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3491
3492 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3493 }
3494}
3495
3496static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3497{
3498 struct phy_start_resp *pPayload =
3499 (struct phy_start_resp *)(piomb + 4);
3500 u32 status =
3501 le32_to_cpu(pPayload->status);
3502 u32 phy_id =
3503 le32_to_cpu(pPayload->phyid);
3504 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3505
3506 PM8001_INIT_DBG(pm8001_ha,
3507 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3508 status, phy_id));
3509 if (status == 0) {
3510 phy->phy_state = PHY_LINK_DOWN;
3511 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3512 phy->enable_completion != NULL) {
3513 complete(phy->enable_completion);
3514 phy->enable_completion = NULL;
3515 }
3516 }
3517 return 0;
3518
3519}
3520
3521
3522
3523
3524
3525
3526static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3527{
3528 struct thermal_hw_event *pPayload =
3529 (struct thermal_hw_event *)(piomb + 4);
3530
3531 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3532 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3533
3534 if (thermal_event & 0x40) {
3535 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3536 "Thermal Event: Local high temperature violated!\n"));
3537 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3538 "Thermal Event: Measured local high temperature %d\n",
3539 ((rht_lht & 0xFF00) >> 8)));
3540 }
3541 if (thermal_event & 0x10) {
3542 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3543 "Thermal Event: Remote high temperature violated!\n"));
3544 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3545 "Thermal Event: Measured remote high temperature %d\n",
3546 ((rht_lht & 0xFF000000) >> 24)));
3547 }
3548 return 0;
3549}
3550
3551
3552
3553
3554
3555
3556static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3557{
3558 unsigned long flags, i;
3559 struct hw_event_resp *pPayload =
3560 (struct hw_event_resp *)(piomb + 4);
3561 u32 lr_status_evt_portid =
3562 le32_to_cpu(pPayload->lr_status_evt_portid);
3563 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3564 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3565 u8 phy_id =
3566 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3567 u16 eventType =
3568 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3569 u8 status =
3570 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3571 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3572 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3573 struct pm8001_port *port = &pm8001_ha->port[port_id];
3574 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3575 PM8001_DEV_DBG(pm8001_ha,
3576 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3577 port_id, phy_id, eventType, status));
3578
3579 switch (eventType) {
3580
3581 case HW_EVENT_SAS_PHY_UP:
3582 PM8001_MSG_DBG(pm8001_ha,
3583 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3584 hw_event_sas_phy_up(pm8001_ha, piomb);
3585 break;
3586 case HW_EVENT_SATA_PHY_UP:
3587 PM8001_MSG_DBG(pm8001_ha,
3588 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3589 hw_event_sata_phy_up(pm8001_ha, piomb);
3590 break;
3591 case HW_EVENT_SATA_SPINUP_HOLD:
3592 PM8001_MSG_DBG(pm8001_ha,
3593 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3594 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3595 break;
3596 case HW_EVENT_PHY_DOWN:
3597 PM8001_MSG_DBG(pm8001_ha,
3598 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3599 hw_event_phy_down(pm8001_ha, piomb);
3600 if (pm8001_ha->reset_in_progress) {
3601 PM8001_MSG_DBG(pm8001_ha,
3602 pm8001_printk("Reset in progress\n"));
3603 return 0;
3604 }
3605 phy->phy_attached = 0;
3606 phy->phy_state = PHY_LINK_DISABLE;
3607 break;
3608 case HW_EVENT_PORT_INVALID:
3609 PM8001_MSG_DBG(pm8001_ha,
3610 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3611 sas_phy_disconnected(sas_phy);
3612 phy->phy_attached = 0;
3613 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3614 break;
3615
3616
3617 case HW_EVENT_BROADCAST_CHANGE:
3618 PM8001_MSG_DBG(pm8001_ha,
3619 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3620 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3621 port_id, phy_id, 1, 0);
3622 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3623 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3624 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3625 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3626 break;
3627 case HW_EVENT_PHY_ERROR:
3628 PM8001_MSG_DBG(pm8001_ha,
3629 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3630 sas_phy_disconnected(&phy->sas_phy);
3631 phy->phy_attached = 0;
3632 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3633 break;
3634 case HW_EVENT_BROADCAST_EXP:
3635 PM8001_MSG_DBG(pm8001_ha,
3636 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3637 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3638 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3639 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3640 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3641 break;
3642 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3643 PM8001_MSG_DBG(pm8001_ha,
3644 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3645 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3646 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3647 break;
3648 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3649 PM8001_MSG_DBG(pm8001_ha,
3650 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3651 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3652 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3653 port_id, phy_id, 0, 0);
3654 break;
3655 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3656 PM8001_MSG_DBG(pm8001_ha,
3657 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3658 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3659 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3660 port_id, phy_id, 0, 0);
3661 break;
3662 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3663 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3664 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3665 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3666 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3667 port_id, phy_id, 0, 0);
3668 break;
3669 case HW_EVENT_MALFUNCTION:
3670 PM8001_MSG_DBG(pm8001_ha,
3671 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3672 break;
3673 case HW_EVENT_BROADCAST_SES:
3674 PM8001_MSG_DBG(pm8001_ha,
3675 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3676 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3677 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3678 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3679 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3680 break;
3681 case HW_EVENT_INBOUND_CRC_ERROR:
3682 PM8001_MSG_DBG(pm8001_ha,
3683 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3684 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3685 HW_EVENT_INBOUND_CRC_ERROR,
3686 port_id, phy_id, 0, 0);
3687 break;
3688 case HW_EVENT_HARD_RESET_RECEIVED:
3689 PM8001_MSG_DBG(pm8001_ha,
3690 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3691 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3692 break;
3693 case HW_EVENT_ID_FRAME_TIMEOUT:
3694 PM8001_MSG_DBG(pm8001_ha,
3695 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3696 sas_phy_disconnected(sas_phy);
3697 phy->phy_attached = 0;
3698 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3699 break;
3700 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3701 PM8001_MSG_DBG(pm8001_ha,
3702 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3703 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3704 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3705 port_id, phy_id, 0, 0);
3706 sas_phy_disconnected(sas_phy);
3707 phy->phy_attached = 0;
3708 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3709 break;
3710 case HW_EVENT_PORT_RESET_TIMER_TMO:
3711 PM8001_MSG_DBG(pm8001_ha,
3712 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3713 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3714 port_id, phy_id, 0, 0);
3715 sas_phy_disconnected(sas_phy);
3716 phy->phy_attached = 0;
3717 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3718 if (pm8001_ha->phy[phy_id].reset_completion) {
3719 pm8001_ha->phy[phy_id].port_reset_status =
3720 PORT_RESET_TMO;
3721 complete(pm8001_ha->phy[phy_id].reset_completion);
3722 pm8001_ha->phy[phy_id].reset_completion = NULL;
3723 }
3724 break;
3725 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3726 PM8001_MSG_DBG(pm8001_ha,
3727 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3728 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3729 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3730 port_id, phy_id, 0, 0);
3731 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3732 if (port->wide_port_phymap & (1 << i)) {
3733 phy = &pm8001_ha->phy[i];
3734 sas_ha->notify_phy_event(&phy->sas_phy,
3735 PHYE_LOSS_OF_SIGNAL);
3736 port->wide_port_phymap &= ~(1 << i);
3737 }
3738 }
3739 break;
3740 case HW_EVENT_PORT_RECOVER:
3741 PM8001_MSG_DBG(pm8001_ha,
3742 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3743 hw_event_port_recover(pm8001_ha, piomb);
3744 break;
3745 case HW_EVENT_PORT_RESET_COMPLETE:
3746 PM8001_MSG_DBG(pm8001_ha,
3747 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3748 if (pm8001_ha->phy[phy_id].reset_completion) {
3749 pm8001_ha->phy[phy_id].port_reset_status =
3750 PORT_RESET_SUCCESS;
3751 complete(pm8001_ha->phy[phy_id].reset_completion);
3752 pm8001_ha->phy[phy_id].reset_completion = NULL;
3753 }
3754 break;
3755 case EVENT_BROADCAST_ASYNCH_EVENT:
3756 PM8001_MSG_DBG(pm8001_ha,
3757 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3758 break;
3759 default:
3760 PM8001_DEVIO_DBG(pm8001_ha,
3761 pm8001_printk("Unknown event type 0x%x\n", eventType));
3762 break;
3763 }
3764 return 0;
3765}
3766
3767
3768
3769
3770
3771
3772static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3773{
3774 struct phy_stop_resp *pPayload =
3775 (struct phy_stop_resp *)(piomb + 4);
3776 u32 status =
3777 le32_to_cpu(pPayload->status);
3778 u32 phyid =
3779 le32_to_cpu(pPayload->phyid) & 0xFF;
3780 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3781 PM8001_MSG_DBG(pm8001_ha,
3782 pm8001_printk("phy:0x%x status:0x%x\n",
3783 phyid, status));
3784 if (status == PHY_STOP_SUCCESS ||
3785 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3786 phy->phy_state = PHY_LINK_DISABLE;
3787 return 0;
3788}
3789
3790
3791
3792
3793
3794
3795static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3796 void *piomb)
3797{
3798 struct set_ctrl_cfg_resp *pPayload =
3799 (struct set_ctrl_cfg_resp *)(piomb + 4);
3800 u32 status = le32_to_cpu(pPayload->status);
3801 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3802
3803 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3804 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3805 status, err_qlfr_pgcd));
3806
3807 return 0;
3808}
3809
3810
3811
3812
3813
3814
3815static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3816 void *piomb)
3817{
3818 PM8001_MSG_DBG(pm8001_ha,
3819 pm8001_printk(" pm80xx_addition_functionality\n"));
3820
3821 return 0;
3822}
3823
3824
3825
3826
3827
3828
3829static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3830 void *piomb)
3831{
3832 PM8001_MSG_DBG(pm8001_ha,
3833 pm8001_printk(" pm80xx_addition_functionality\n"));
3834
3835 return 0;
3836}
3837
3838
3839
3840
3841
3842
3843static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3844{
3845 PM8001_MSG_DBG(pm8001_ha,
3846 pm8001_printk(" pm80xx_addition_functionality\n"));
3847
3848 return 0;
3849}
3850
3851
3852
3853
3854
3855
3856static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3857 void *piomb)
3858{
3859 u32 tag;
3860 u8 page_code;
3861 int rc = 0;
3862 struct set_phy_profile_resp *pPayload =
3863 (struct set_phy_profile_resp *)(piomb + 4);
3864 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3865 u32 status = le32_to_cpu(pPayload->status);
3866
3867 tag = le32_to_cpu(pPayload->tag);
3868 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3869 if (status) {
3870
3871 PM8001_FAIL_DBG(pm8001_ha,
3872 pm8001_printk("PhyProfile command failed with status "
3873 "0x%08X \n", status));
3874 rc = -1;
3875 } else {
3876 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3877 PM8001_FAIL_DBG(pm8001_ha,
3878 pm8001_printk("Invalid page code 0x%X\n",
3879 page_code));
3880 rc = -1;
3881 }
3882 }
3883 pm8001_tag_free(pm8001_ha, tag);
3884 return rc;
3885}
3886
3887
3888
3889
3890
3891
3892static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3893 void *piomb)
3894{
3895 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3896
3897 u32 status = le32_to_cpu(pPayload->status);
3898 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3899 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3900
3901 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3902 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3903 status, kidx_new_curr_ksop, err_qlfr));
3904
3905 return 0;
3906}
3907
3908
3909
3910
3911
3912
3913static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3914 void *piomb)
3915{
3916 PM8001_MSG_DBG(pm8001_ha,
3917 pm8001_printk(" pm80xx_addition_functionality\n"));
3918
3919 return 0;
3920}
3921
3922
3923
3924
3925
3926
3927static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3928 void *piomb)
3929{
3930 PM8001_MSG_DBG(pm8001_ha,
3931 pm8001_printk(" pm80xx_addition_functionality\n"));
3932
3933 return 0;
3934}
3935
3936
3937
3938
3939
3940
3941static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3942{
3943 __le32 pHeader = *(__le32 *)piomb;
3944 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3945
3946 switch (opc) {
3947 case OPC_OUB_ECHO:
3948 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3949 break;
3950 case OPC_OUB_HW_EVENT:
3951 PM8001_MSG_DBG(pm8001_ha,
3952 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3953 mpi_hw_event(pm8001_ha, piomb);
3954 break;
3955 case OPC_OUB_THERM_HW_EVENT:
3956 PM8001_MSG_DBG(pm8001_ha,
3957 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3958 mpi_thermal_hw_event(pm8001_ha, piomb);
3959 break;
3960 case OPC_OUB_SSP_COMP:
3961 PM8001_MSG_DBG(pm8001_ha,
3962 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3963 mpi_ssp_completion(pm8001_ha, piomb);
3964 break;
3965 case OPC_OUB_SMP_COMP:
3966 PM8001_MSG_DBG(pm8001_ha,
3967 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3968 mpi_smp_completion(pm8001_ha, piomb);
3969 break;
3970 case OPC_OUB_LOCAL_PHY_CNTRL:
3971 PM8001_MSG_DBG(pm8001_ha,
3972 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3973 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3974 break;
3975 case OPC_OUB_DEV_REGIST:
3976 PM8001_MSG_DBG(pm8001_ha,
3977 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3978 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3979 break;
3980 case OPC_OUB_DEREG_DEV:
3981 PM8001_MSG_DBG(pm8001_ha,
3982 pm8001_printk("unregister the device\n"));
3983 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3984 break;
3985 case OPC_OUB_GET_DEV_HANDLE:
3986 PM8001_MSG_DBG(pm8001_ha,
3987 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3988 break;
3989 case OPC_OUB_SATA_COMP:
3990 PM8001_MSG_DBG(pm8001_ha,
3991 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3992 mpi_sata_completion(pm8001_ha, piomb);
3993 break;
3994 case OPC_OUB_SATA_EVENT:
3995 PM8001_MSG_DBG(pm8001_ha,
3996 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3997 mpi_sata_event(pm8001_ha, piomb);
3998 break;
3999 case OPC_OUB_SSP_EVENT:
4000 PM8001_MSG_DBG(pm8001_ha,
4001 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
4002 mpi_ssp_event(pm8001_ha, piomb);
4003 break;
4004 case OPC_OUB_DEV_HANDLE_ARRIV:
4005 PM8001_MSG_DBG(pm8001_ha,
4006 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
4007
4008 break;
4009 case OPC_OUB_SSP_RECV_EVENT:
4010 PM8001_MSG_DBG(pm8001_ha,
4011 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
4012
4013 break;
4014 case OPC_OUB_FW_FLASH_UPDATE:
4015 PM8001_MSG_DBG(pm8001_ha,
4016 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
4017 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
4018 break;
4019 case OPC_OUB_GPIO_RESPONSE:
4020 PM8001_MSG_DBG(pm8001_ha,
4021 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
4022 break;
4023 case OPC_OUB_GPIO_EVENT:
4024 PM8001_MSG_DBG(pm8001_ha,
4025 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
4026 break;
4027 case OPC_OUB_GENERAL_EVENT:
4028 PM8001_MSG_DBG(pm8001_ha,
4029 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
4030 pm8001_mpi_general_event(pm8001_ha, piomb);
4031 break;
4032 case OPC_OUB_SSP_ABORT_RSP:
4033 PM8001_MSG_DBG(pm8001_ha,
4034 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
4035 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4036 break;
4037 case OPC_OUB_SATA_ABORT_RSP:
4038 PM8001_MSG_DBG(pm8001_ha,
4039 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
4040 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4041 break;
4042 case OPC_OUB_SAS_DIAG_MODE_START_END:
4043 PM8001_MSG_DBG(pm8001_ha,
4044 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
4045 break;
4046 case OPC_OUB_SAS_DIAG_EXECUTE:
4047 PM8001_MSG_DBG(pm8001_ha,
4048 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
4049 break;
4050 case OPC_OUB_GET_TIME_STAMP:
4051 PM8001_MSG_DBG(pm8001_ha,
4052 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
4053 break;
4054 case OPC_OUB_SAS_HW_EVENT_ACK:
4055 PM8001_MSG_DBG(pm8001_ha,
4056 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
4057 break;
4058 case OPC_OUB_PORT_CONTROL:
4059 PM8001_MSG_DBG(pm8001_ha,
4060 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
4061 break;
4062 case OPC_OUB_SMP_ABORT_RSP:
4063 PM8001_MSG_DBG(pm8001_ha,
4064 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
4065 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4066 break;
4067 case OPC_OUB_GET_NVMD_DATA:
4068 PM8001_MSG_DBG(pm8001_ha,
4069 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
4070 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4071 break;
4072 case OPC_OUB_SET_NVMD_DATA:
4073 PM8001_MSG_DBG(pm8001_ha,
4074 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
4075 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4076 break;
4077 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4078 PM8001_MSG_DBG(pm8001_ha,
4079 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
4080 break;
4081 case OPC_OUB_SET_DEVICE_STATE:
4082 PM8001_MSG_DBG(pm8001_ha,
4083 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
4084 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4085 break;
4086 case OPC_OUB_GET_DEVICE_STATE:
4087 PM8001_MSG_DBG(pm8001_ha,
4088 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
4089 break;
4090 case OPC_OUB_SET_DEV_INFO:
4091 PM8001_MSG_DBG(pm8001_ha,
4092 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
4093 break;
4094
4095 case OPC_OUB_PHY_START_RESP:
4096 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4097 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
4098 mpi_phy_start_resp(pm8001_ha, piomb);
4099 break;
4100 case OPC_OUB_PHY_STOP_RESP:
4101 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4102 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
4103 mpi_phy_stop_resp(pm8001_ha, piomb);
4104 break;
4105 case OPC_OUB_SET_CONTROLLER_CONFIG:
4106 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4107 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
4108 mpi_set_controller_config_resp(pm8001_ha, piomb);
4109 break;
4110 case OPC_OUB_GET_CONTROLLER_CONFIG:
4111 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4112 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
4113 mpi_get_controller_config_resp(pm8001_ha, piomb);
4114 break;
4115 case OPC_OUB_GET_PHY_PROFILE:
4116 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4117 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
4118 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4119 break;
4120 case OPC_OUB_FLASH_OP_EXT:
4121 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4122 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
4123 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4124 break;
4125 case OPC_OUB_SET_PHY_PROFILE:
4126 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4127 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
4128 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4129 break;
4130 case OPC_OUB_KEK_MANAGEMENT_RESP:
4131 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4132 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
4133 mpi_kek_management_resp(pm8001_ha, piomb);
4134 break;
4135 case OPC_OUB_DEK_MANAGEMENT_RESP:
4136 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4137 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
4138 mpi_dek_management_resp(pm8001_ha, piomb);
4139 break;
4140 case OPC_OUB_SSP_COALESCED_COMP_RESP:
4141 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
4142 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
4143 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4144 break;
4145 default:
4146 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4147 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
4148 break;
4149 }
4150}
4151
4152static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4153{
4154 PM8001_FAIL_DBG(pm8001_ha,
4155 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
4156 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
4157 PM8001_FAIL_DBG(pm8001_ha,
4158 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
4159 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
4160 PM8001_FAIL_DBG(pm8001_ha,
4161 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
4162 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
4163 PM8001_FAIL_DBG(pm8001_ha,
4164 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
4165 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
4166 PM8001_FAIL_DBG(pm8001_ha,
4167 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4168 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
4169 PM8001_FAIL_DBG(pm8001_ha,
4170 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4171 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
4172 PM8001_FAIL_DBG(pm8001_ha,
4173 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4174 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
4175 PM8001_FAIL_DBG(pm8001_ha,
4176 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4177 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
4178 PM8001_FAIL_DBG(pm8001_ha,
4179 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4180 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
4181 PM8001_FAIL_DBG(pm8001_ha,
4182 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4183 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
4184 PM8001_FAIL_DBG(pm8001_ha,
4185 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4186 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
4187 PM8001_FAIL_DBG(pm8001_ha,
4188 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4189 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
4190}
4191
4192static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4193{
4194 struct outbound_queue_table *circularQ;
4195 void *pMsg1 = NULL;
4196 u8 bc;
4197 u32 ret = MPI_IO_STATUS_FAIL;
4198 unsigned long flags;
4199 u32 regval;
4200
4201 if (vec == (pm8001_ha->max_q_num - 1)) {
4202 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4203 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
4204 SCRATCH_PAD_MIPSALL_READY) {
4205 pm8001_ha->controller_fatal_error = true;
4206 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
4207 "Firmware Fatal error! Regval:0x%x\n", regval));
4208 print_scratchpad_registers(pm8001_ha);
4209 return ret;
4210 }
4211 }
4212 spin_lock_irqsave(&pm8001_ha->lock, flags);
4213 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4214 do {
4215
4216
4217
4218
4219 if (!circularQ->pi_virt)
4220 break;
4221 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4222 if (MPI_IO_STATUS_SUCCESS == ret) {
4223
4224 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4225
4226 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4227 circularQ, bc);
4228 }
4229 if (MPI_IO_STATUS_BUSY == ret) {
4230
4231 circularQ->producer_index =
4232 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4233 if (le32_to_cpu(circularQ->producer_index) ==
4234 circularQ->consumer_idx)
4235
4236 break;
4237 }
4238 } while (1);
4239 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4240 return ret;
4241}
4242
4243
4244static const u8 data_dir_flags[] = {
4245 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,
4246 [DMA_TO_DEVICE] = DATA_DIR_OUT,
4247 [DMA_FROM_DEVICE] = DATA_DIR_IN,
4248 [DMA_NONE] = DATA_DIR_NONE,
4249};
4250
4251static void build_smp_cmd(u32 deviceID, __le32 hTag,
4252 struct smp_req *psmp_cmd, int mode, int length)
4253{
4254 psmp_cmd->tag = hTag;
4255 psmp_cmd->device_id = cpu_to_le32(deviceID);
4256 if (mode == SMP_DIRECT) {
4257 length = length - 4;
4258 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4259 } else {
4260 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4261 }
4262}
4263
4264
4265
4266
4267
4268
4269static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4270 struct pm8001_ccb_info *ccb)
4271{
4272 int elem, rc;
4273 struct sas_task *task = ccb->task;
4274 struct domain_device *dev = task->dev;
4275 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4276 struct scatterlist *sg_req, *sg_resp;
4277 u32 req_len, resp_len;
4278 struct smp_req smp_cmd;
4279 u32 opc;
4280 struct inbound_queue_table *circularQ;
4281 char *preq_dma_addr = NULL;
4282 __le64 tmp_addr;
4283 u32 i, length;
4284 unsigned long flags;
4285
4286 memset(&smp_cmd, 0, sizeof(smp_cmd));
4287
4288
4289
4290 sg_req = &task->smp_task.smp_req;
4291 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4292 if (!elem)
4293 return -ENOMEM;
4294 req_len = sg_dma_len(sg_req);
4295
4296 sg_resp = &task->smp_task.smp_resp;
4297 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4298 if (!elem) {
4299 rc = -ENOMEM;
4300 goto err_out;
4301 }
4302 resp_len = sg_dma_len(sg_resp);
4303
4304 if ((req_len & 0x3) || (resp_len & 0x3)) {
4305 rc = -EINVAL;
4306 goto err_out_2;
4307 }
4308
4309 opc = OPC_INB_SMP_REQUEST;
4310 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4311 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4312
4313 length = sg_req->length;
4314 PM8001_IO_DBG(pm8001_ha,
4315 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
4316 if (!(length - 8))
4317 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4318 else
4319 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4320
4321
4322 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4323 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4324
4325
4326 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4327 PM8001_IO_DBG(pm8001_ha,
4328 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
4329
4330
4331 for (i = 0; i < 4; i++)
4332 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4333
4334 smp_cmd.long_smp_req.long_req_addr =
4335 cpu_to_le64((u64)sg_dma_address
4336 (&task->smp_task.smp_req) + 4);
4337
4338 smp_cmd.long_smp_req.long_req_size =
4339 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4340 smp_cmd.long_smp_req.long_resp_addr =
4341 cpu_to_le64((u64)sg_dma_address
4342 (&task->smp_task.smp_resp));
4343 smp_cmd.long_smp_req.long_resp_size =
4344 cpu_to_le32((u32)sg_dma_len
4345 (&task->smp_task.smp_resp)-4);
4346 } else {
4347 smp_cmd.long_smp_req.long_req_addr =
4348 cpu_to_le64((u64)sg_dma_address
4349 (&task->smp_task.smp_req));
4350 smp_cmd.long_smp_req.long_req_size =
4351 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4352 smp_cmd.long_smp_req.long_resp_addr =
4353 cpu_to_le64((u64)sg_dma_address
4354 (&task->smp_task.smp_resp));
4355 smp_cmd.long_smp_req.long_resp_size =
4356 cpu_to_le32
4357 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4358 }
4359 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4360 PM8001_IO_DBG(pm8001_ha,
4361 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
4362 for (i = 0; i < length; i++)
4363 if (i < 16) {
4364 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4365 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4366 "Byte[%d]:%x (DMA data:%x)\n",
4367 i, smp_cmd.smp_req16[i],
4368 *(preq_dma_addr)));
4369 } else {
4370 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4371 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4372 "Byte[%d]:%x (DMA data:%x)\n",
4373 i, smp_cmd.smp_req[i],
4374 *(preq_dma_addr)));
4375 }
4376 }
4377
4378 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4379 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4380 spin_lock_irqsave(&circularQ->iq_lock, flags);
4381 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4382 sizeof(smp_cmd), 0);
4383 spin_unlock_irqrestore(&circularQ->iq_lock, flags);
4384 if (rc)
4385 goto err_out_2;
4386 return 0;
4387
4388err_out_2:
4389 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4390 DMA_FROM_DEVICE);
4391err_out:
4392 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4393 DMA_TO_DEVICE);
4394 return rc;
4395}
4396
4397static int check_enc_sas_cmd(struct sas_task *task)
4398{
4399 u8 cmd = task->ssp_task.cmd->cmnd[0];
4400
4401 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4402 return 1;
4403 else
4404 return 0;
4405}
4406
4407static int check_enc_sat_cmd(struct sas_task *task)
4408{
4409 int ret = 0;
4410 switch (task->ata_task.fis.command) {
4411 case ATA_CMD_FPDMA_READ:
4412 case ATA_CMD_READ_EXT:
4413 case ATA_CMD_READ:
4414 case ATA_CMD_FPDMA_WRITE:
4415 case ATA_CMD_WRITE_EXT:
4416 case ATA_CMD_WRITE:
4417 case ATA_CMD_PIO_READ:
4418 case ATA_CMD_PIO_READ_EXT:
4419 case ATA_CMD_PIO_WRITE:
4420 case ATA_CMD_PIO_WRITE_EXT:
4421 ret = 1;
4422 break;
4423 default:
4424 ret = 0;
4425 break;
4426 }
4427 return ret;
4428}
4429
4430
4431
4432
4433
4434
4435static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4436 struct pm8001_ccb_info *ccb)
4437{
4438 struct sas_task *task = ccb->task;
4439 struct domain_device *dev = task->dev;
4440 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4441 struct ssp_ini_io_start_req ssp_cmd;
4442 u32 tag = ccb->ccb_tag;
4443 int ret;
4444 u64 phys_addr, start_addr, end_addr;
4445 u32 end_addr_high, end_addr_low;
4446 struct inbound_queue_table *circularQ;
4447 unsigned long flags;
4448 u32 q_index, cpu_id;
4449 u32 opc = OPC_INB_SSPINIIOSTART;
4450 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4451 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4452
4453
4454
4455
4456 ssp_cmd.dad_dir_m_tlr =
4457 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4458 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4459 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4460 ssp_cmd.tag = cpu_to_le32(tag);
4461 if (task->ssp_task.enable_first_burst)
4462 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4463 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4464 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4465 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4466 task->ssp_task.cmd->cmd_len);
4467 cpu_id = smp_processor_id();
4468 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4469 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4470
4471
4472 if (pm8001_ha->chip->encrypt &&
4473 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4474 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4475 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4476 task->ssp_task.cmd->cmnd[0]));
4477 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4478
4479 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4480 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4481
4482
4483 if (task->num_scatter > 1) {
4484 pm8001_chip_make_sg(task->scatter,
4485 ccb->n_elem, ccb->buf_prd);
4486 phys_addr = ccb->ccb_dma_handle;
4487 ssp_cmd.enc_addr_low =
4488 cpu_to_le32(lower_32_bits(phys_addr));
4489 ssp_cmd.enc_addr_high =
4490 cpu_to_le32(upper_32_bits(phys_addr));
4491 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4492 } else if (task->num_scatter == 1) {
4493 u64 dma_addr = sg_dma_address(task->scatter);
4494 ssp_cmd.enc_addr_low =
4495 cpu_to_le32(lower_32_bits(dma_addr));
4496 ssp_cmd.enc_addr_high =
4497 cpu_to_le32(upper_32_bits(dma_addr));
4498 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4499 ssp_cmd.enc_esgl = 0;
4500
4501 start_addr = cpu_to_le64(dma_addr);
4502 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4503 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4504 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4505 if (end_addr_high != ssp_cmd.enc_addr_high) {
4506 PM8001_FAIL_DBG(pm8001_ha,
4507 pm8001_printk("The sg list address "
4508 "start_addr=0x%016llx data_len=0x%x "
4509 "end_addr_high=0x%08x end_addr_low="
4510 "0x%08x has crossed 4G boundary\n",
4511 start_addr, ssp_cmd.enc_len,
4512 end_addr_high, end_addr_low));
4513 pm8001_chip_make_sg(task->scatter, 1,
4514 ccb->buf_prd);
4515 phys_addr = ccb->ccb_dma_handle;
4516 ssp_cmd.enc_addr_low =
4517 cpu_to_le32(lower_32_bits(phys_addr));
4518 ssp_cmd.enc_addr_high =
4519 cpu_to_le32(upper_32_bits(phys_addr));
4520 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4521 }
4522 } else if (task->num_scatter == 0) {
4523 ssp_cmd.enc_addr_low = 0;
4524 ssp_cmd.enc_addr_high = 0;
4525 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4526 ssp_cmd.enc_esgl = 0;
4527 }
4528
4529 ssp_cmd.key_cmode = 0x6 << 4;
4530
4531 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4532 (task->ssp_task.cmd->cmnd[3] << 16) |
4533 (task->ssp_task.cmd->cmnd[4] << 8) |
4534 (task->ssp_task.cmd->cmnd[5]));
4535 } else {
4536 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4537 "Sending Normal SAS command 0x%x inb q %x\n",
4538 task->ssp_task.cmd->cmnd[0], q_index));
4539
4540 if (task->num_scatter > 1) {
4541 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4542 ccb->buf_prd);
4543 phys_addr = ccb->ccb_dma_handle;
4544 ssp_cmd.addr_low =
4545 cpu_to_le32(lower_32_bits(phys_addr));
4546 ssp_cmd.addr_high =
4547 cpu_to_le32(upper_32_bits(phys_addr));
4548 ssp_cmd.esgl = cpu_to_le32(1<<31);
4549 } else if (task->num_scatter == 1) {
4550 u64 dma_addr = sg_dma_address(task->scatter);
4551 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4552 ssp_cmd.addr_high =
4553 cpu_to_le32(upper_32_bits(dma_addr));
4554 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4555 ssp_cmd.esgl = 0;
4556
4557 start_addr = cpu_to_le64(dma_addr);
4558 end_addr = (start_addr + ssp_cmd.len) - 1;
4559 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4560 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4561 if (end_addr_high != ssp_cmd.addr_high) {
4562 PM8001_FAIL_DBG(pm8001_ha,
4563 pm8001_printk("The sg list address "
4564 "start_addr=0x%016llx data_len=0x%x "
4565 "end_addr_high=0x%08x end_addr_low="
4566 "0x%08x has crossed 4G boundary\n",
4567 start_addr, ssp_cmd.len,
4568 end_addr_high, end_addr_low));
4569 pm8001_chip_make_sg(task->scatter, 1,
4570 ccb->buf_prd);
4571 phys_addr = ccb->ccb_dma_handle;
4572 ssp_cmd.addr_low =
4573 cpu_to_le32(lower_32_bits(phys_addr));
4574 ssp_cmd.addr_high =
4575 cpu_to_le32(upper_32_bits(phys_addr));
4576 ssp_cmd.esgl = cpu_to_le32(1<<31);
4577 }
4578 } else if (task->num_scatter == 0) {
4579 ssp_cmd.addr_low = 0;
4580 ssp_cmd.addr_high = 0;
4581 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4582 ssp_cmd.esgl = 0;
4583 }
4584 }
4585 spin_lock_irqsave(&circularQ->iq_lock, flags);
4586 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4587 &ssp_cmd, sizeof(ssp_cmd), q_index);
4588 spin_unlock_irqrestore(&circularQ->iq_lock, flags);
4589 return ret;
4590}
4591
4592static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4593 struct pm8001_ccb_info *ccb)
4594{
4595 struct sas_task *task = ccb->task;
4596 struct domain_device *dev = task->dev;
4597 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4598 u32 tag = ccb->ccb_tag;
4599 int ret;
4600 u32 q_index, cpu_id;
4601 struct sata_start_req sata_cmd;
4602 u32 hdr_tag, ncg_tag = 0;
4603 u64 phys_addr, start_addr, end_addr;
4604 u32 end_addr_high, end_addr_low;
4605 u32 ATAP = 0x0;
4606 u32 dir;
4607 struct inbound_queue_table *circularQ;
4608 unsigned long flags;
4609 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4610 memset(&sata_cmd, 0, sizeof(sata_cmd));
4611 cpu_id = smp_processor_id();
4612 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4613 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4614
4615 if (task->data_dir == DMA_NONE) {
4616 ATAP = 0x04;
4617 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4618 } else if (likely(!task->ata_task.device_control_reg_update)) {
4619 if (task->ata_task.dma_xfer) {
4620 ATAP = 0x06;
4621 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4622 } else {
4623 ATAP = 0x05;
4624 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4625 }
4626 if (task->ata_task.use_ncq &&
4627 dev->sata_dev.class != ATA_DEV_ATAPI) {
4628 ATAP = 0x07;
4629 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4630 }
4631 }
4632 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4633 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4634 ncg_tag = hdr_tag;
4635 }
4636 dir = data_dir_flags[task->data_dir] << 8;
4637 sata_cmd.tag = cpu_to_le32(tag);
4638 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4639 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4640
4641 sata_cmd.sata_fis = task->ata_task.fis;
4642 if (likely(!task->ata_task.device_control_reg_update))
4643 sata_cmd.sata_fis.flags |= 0x80;
4644 sata_cmd.sata_fis.flags &= 0xF0;
4645
4646
4647 if (pm8001_ha->chip->encrypt &&
4648 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4649 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4650 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4651 sata_cmd.sata_fis.command));
4652 opc = OPC_INB_SATA_DIF_ENC_IO;
4653
4654
4655 sata_cmd.ncqtag_atap_dir_m_dad =
4656 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4657 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4658
4659
4660 if (task->num_scatter > 1) {
4661 pm8001_chip_make_sg(task->scatter,
4662 ccb->n_elem, ccb->buf_prd);
4663 phys_addr = ccb->ccb_dma_handle;
4664 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4665 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4666 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4667 } else if (task->num_scatter == 1) {
4668 u64 dma_addr = sg_dma_address(task->scatter);
4669 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4670 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4671 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4672 sata_cmd.enc_esgl = 0;
4673
4674 start_addr = cpu_to_le64(dma_addr);
4675 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4676 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4677 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4678 if (end_addr_high != sata_cmd.enc_addr_high) {
4679 PM8001_FAIL_DBG(pm8001_ha,
4680 pm8001_printk("The sg list address "
4681 "start_addr=0x%016llx data_len=0x%x "
4682 "end_addr_high=0x%08x end_addr_low"
4683 "=0x%08x has crossed 4G boundary\n",
4684 start_addr, sata_cmd.enc_len,
4685 end_addr_high, end_addr_low));
4686 pm8001_chip_make_sg(task->scatter, 1,
4687 ccb->buf_prd);
4688 phys_addr = ccb->ccb_dma_handle;
4689 sata_cmd.enc_addr_low =
4690 lower_32_bits(phys_addr);
4691 sata_cmd.enc_addr_high =
4692 upper_32_bits(phys_addr);
4693 sata_cmd.enc_esgl =
4694 cpu_to_le32(1 << 31);
4695 }
4696 } else if (task->num_scatter == 0) {
4697 sata_cmd.enc_addr_low = 0;
4698 sata_cmd.enc_addr_high = 0;
4699 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4700 sata_cmd.enc_esgl = 0;
4701 }
4702
4703 sata_cmd.key_index_mode = 0x6 << 4;
4704
4705 sata_cmd.twk_val0 =
4706 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4707 (sata_cmd.sata_fis.lbah << 16) |
4708 (sata_cmd.sata_fis.lbam << 8) |
4709 (sata_cmd.sata_fis.lbal));
4710 sata_cmd.twk_val1 =
4711 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4712 (sata_cmd.sata_fis.lbam_exp));
4713 } else {
4714 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4715 "Sending Normal SATA command 0x%x inb %x\n",
4716 sata_cmd.sata_fis.command, q_index));
4717
4718 sata_cmd.ncqtag_atap_dir_m_dad =
4719 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4720 ((ATAP & 0x3f) << 10) | dir);
4721
4722
4723 if (task->num_scatter > 1) {
4724 pm8001_chip_make_sg(task->scatter,
4725 ccb->n_elem, ccb->buf_prd);
4726 phys_addr = ccb->ccb_dma_handle;
4727 sata_cmd.addr_low = lower_32_bits(phys_addr);
4728 sata_cmd.addr_high = upper_32_bits(phys_addr);
4729 sata_cmd.esgl = cpu_to_le32(1 << 31);
4730 } else if (task->num_scatter == 1) {
4731 u64 dma_addr = sg_dma_address(task->scatter);
4732 sata_cmd.addr_low = lower_32_bits(dma_addr);
4733 sata_cmd.addr_high = upper_32_bits(dma_addr);
4734 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4735 sata_cmd.esgl = 0;
4736
4737 start_addr = cpu_to_le64(dma_addr);
4738 end_addr = (start_addr + sata_cmd.len) - 1;
4739 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4740 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4741 if (end_addr_high != sata_cmd.addr_high) {
4742 PM8001_FAIL_DBG(pm8001_ha,
4743 pm8001_printk("The sg list address "
4744 "start_addr=0x%016llx data_len=0x%x"
4745 "end_addr_high=0x%08x end_addr_low="
4746 "0x%08x has crossed 4G boundary\n",
4747 start_addr, sata_cmd.len,
4748 end_addr_high, end_addr_low));
4749 pm8001_chip_make_sg(task->scatter, 1,
4750 ccb->buf_prd);
4751 phys_addr = ccb->ccb_dma_handle;
4752 sata_cmd.addr_low =
4753 lower_32_bits(phys_addr);
4754 sata_cmd.addr_high =
4755 upper_32_bits(phys_addr);
4756 sata_cmd.esgl = cpu_to_le32(1 << 31);
4757 }
4758 } else if (task->num_scatter == 0) {
4759 sata_cmd.addr_low = 0;
4760 sata_cmd.addr_high = 0;
4761 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4762 sata_cmd.esgl = 0;
4763 }
4764
4765 sata_cmd.atapi_scsi_cdb[0] =
4766 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4767 (task->ata_task.atapi_packet[1] << 8) |
4768 (task->ata_task.atapi_packet[2] << 16) |
4769 (task->ata_task.atapi_packet[3] << 24)));
4770 sata_cmd.atapi_scsi_cdb[1] =
4771 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4772 (task->ata_task.atapi_packet[5] << 8) |
4773 (task->ata_task.atapi_packet[6] << 16) |
4774 (task->ata_task.atapi_packet[7] << 24)));
4775 sata_cmd.atapi_scsi_cdb[2] =
4776 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4777 (task->ata_task.atapi_packet[9] << 8) |
4778 (task->ata_task.atapi_packet[10] << 16) |
4779 (task->ata_task.atapi_packet[11] << 24)));
4780 sata_cmd.atapi_scsi_cdb[3] =
4781 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4782 (task->ata_task.atapi_packet[13] << 8) |
4783 (task->ata_task.atapi_packet[14] << 16) |
4784 (task->ata_task.atapi_packet[15] << 24)));
4785 }
4786
4787
4788 if (sata_cmd.sata_fis.command == 0x2f) {
4789 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4790 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4791 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4792 struct task_status_struct *ts;
4793
4794 pm8001_ha_dev->id &= 0xDFFFFFFF;
4795 ts = &task->task_status;
4796
4797 spin_lock_irqsave(&task->task_state_lock, flags);
4798 ts->resp = SAS_TASK_COMPLETE;
4799 ts->stat = SAM_STAT_GOOD;
4800 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4801 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4802 task->task_state_flags |= SAS_TASK_STATE_DONE;
4803 if (unlikely((task->task_state_flags &
4804 SAS_TASK_STATE_ABORTED))) {
4805 spin_unlock_irqrestore(&task->task_state_lock,
4806 flags);
4807 PM8001_FAIL_DBG(pm8001_ha,
4808 pm8001_printk("task 0x%p resp 0x%x "
4809 " stat 0x%x but aborted by upper layer "
4810 "\n", task, ts->resp, ts->stat));
4811 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4812 return 0;
4813 } else {
4814 spin_unlock_irqrestore(&task->task_state_lock,
4815 flags);
4816 pm8001_ccb_task_free_done(pm8001_ha, task,
4817 ccb, tag);
4818 return 0;
4819 }
4820 }
4821 }
4822 spin_lock_irqsave(&circularQ->iq_lock, flags);
4823 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4824 &sata_cmd, sizeof(sata_cmd), q_index);
4825 spin_unlock_irqrestore(&circularQ->iq_lock, flags);
4826 return ret;
4827}
4828
4829
4830
4831
4832
4833
4834static int
4835pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4836{
4837 struct phy_start_req payload;
4838 struct inbound_queue_table *circularQ;
4839 int ret;
4840 u32 tag = 0x01;
4841 u32 opcode = OPC_INB_PHYSTART;
4842 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4843 memset(&payload, 0, sizeof(payload));
4844 payload.tag = cpu_to_le32(tag);
4845
4846 PM8001_INIT_DBG(pm8001_ha,
4847 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4848
4849 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4850 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860 payload.sas_identify.dev_type = SAS_END_DEVICE;
4861 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4862 memcpy(payload.sas_identify.sas_addr,
4863 &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4864 payload.sas_identify.phy_id = phy_id;
4865 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4866 sizeof(payload), 0);
4867 return ret;
4868}
4869
4870
4871
4872
4873
4874
4875static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4876 u8 phy_id)
4877{
4878 struct phy_stop_req payload;
4879 struct inbound_queue_table *circularQ;
4880 int ret;
4881 u32 tag = 0x01;
4882 u32 opcode = OPC_INB_PHYSTOP;
4883 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4884 memset(&payload, 0, sizeof(payload));
4885 payload.tag = cpu_to_le32(tag);
4886 payload.phy_id = cpu_to_le32(phy_id);
4887 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4888 sizeof(payload), 0);
4889 return ret;
4890}
4891
4892
4893
4894
4895static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4896 struct pm8001_device *pm8001_dev, u32 flag)
4897{
4898 struct reg_dev_req payload;
4899 u32 opc;
4900 u32 stp_sspsmp_sata = 0x4;
4901 struct inbound_queue_table *circularQ;
4902 u32 linkrate, phy_id;
4903 int rc, tag = 0xdeadbeef;
4904 struct pm8001_ccb_info *ccb;
4905 u8 retryFlag = 0x1;
4906 u16 firstBurstSize = 0;
4907 u16 ITNT = 2000;
4908 struct domain_device *dev = pm8001_dev->sas_device;
4909 struct domain_device *parent_dev = dev->parent;
4910 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4911
4912 memset(&payload, 0, sizeof(payload));
4913 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4914 if (rc)
4915 return rc;
4916 ccb = &pm8001_ha->ccb_info[tag];
4917 ccb->device = pm8001_dev;
4918 ccb->ccb_tag = tag;
4919 payload.tag = cpu_to_le32(tag);
4920
4921 if (flag == 1) {
4922 stp_sspsmp_sata = 0x02;
4923 } else {
4924 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4925 stp_sspsmp_sata = 0x00;
4926 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4927 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4928 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4929 stp_sspsmp_sata = 0x01;
4930 }
4931 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4932 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4933 else
4934 phy_id = pm8001_dev->attached_phy;
4935
4936 opc = OPC_INB_REG_DEV;
4937
4938 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4939 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4940
4941 payload.phyid_portid =
4942 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4943 ((phy_id & 0xFF) << 8));
4944
4945 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4946 ((linkrate & 0x0F) << 24) |
4947 ((stp_sspsmp_sata & 0x03) << 28));
4948 payload.firstburstsize_ITNexustimeout =
4949 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4950
4951 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4952 SAS_ADDR_SIZE);
4953
4954 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4955 sizeof(payload), 0);
4956 if (rc)
4957 pm8001_tag_free(pm8001_ha, tag);
4958
4959 return rc;
4960}
4961
4962
4963
4964
4965
4966
4967
4968static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4969 u32 phyId, u32 phy_op)
4970{
4971 u32 tag;
4972 int rc;
4973 struct local_phy_ctl_req payload;
4974 struct inbound_queue_table *circularQ;
4975 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4976 memset(&payload, 0, sizeof(payload));
4977 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4978 if (rc)
4979 return rc;
4980 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4981 payload.tag = cpu_to_le32(tag);
4982 payload.phyop_phyid =
4983 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4984 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4985 sizeof(payload), 0);
4986}
4987
4988static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4989{
4990#ifdef PM8001_USE_MSIX
4991 return 1;
4992#else
4993 u32 value;
4994
4995 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4996 if (value)
4997 return 1;
4998 return 0;
4999#endif
5000}
5001
5002
5003
5004
5005
5006
5007static irqreturn_t
5008pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
5009{
5010 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
5011 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
5012 "irq vec %d, ODMR:0x%x\n",
5013 vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
5014 process_oq(pm8001_ha, vec);
5015 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
5016 return IRQ_HANDLED;
5017}
5018
5019static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
5020 u32 operation, u32 phyid,
5021 u32 length, u32 *buf)
5022{
5023 u32 tag , i, j = 0;
5024 int rc;
5025 struct set_phy_profile_req payload;
5026 struct inbound_queue_table *circularQ;
5027 u32 opc = OPC_INB_SET_PHY_PROFILE;
5028
5029 memset(&payload, 0, sizeof(payload));
5030 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5031 if (rc)
5032 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
5033 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5034 payload.tag = cpu_to_le32(tag);
5035 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
5036 PM8001_INIT_DBG(pm8001_ha,
5037 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
5038 payload.ppc_phyid, length));
5039 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
5040 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
5041 j++;
5042 }
5043 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5044 sizeof(payload), 0);
5045 if (rc)
5046 pm8001_tag_free(pm8001_ha, tag);
5047}
5048
5049void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
5050 u32 length, u8 *buf)
5051{
5052 u32 i;
5053
5054 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
5055 mpi_set_phy_profile_req(pm8001_ha,
5056 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
5057 length = length + PHY_DWORD_LENGTH;
5058 }
5059 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
5060}
5061
5062void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
5063 u32 phy, u32 length, u32 *buf)
5064{
5065 u32 tag, opc;
5066 int rc, i;
5067 struct set_phy_profile_req payload;
5068 struct inbound_queue_table *circularQ;
5069
5070 memset(&payload, 0, sizeof(payload));
5071
5072 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5073 if (rc)
5074 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
5075
5076 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5077 opc = OPC_INB_SET_PHY_PROFILE;
5078
5079 payload.tag = cpu_to_le32(tag);
5080 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
5081 | (phy & 0xFF));
5082
5083 for (i = 0; i < length; i++)
5084 payload.reserved[i] = cpu_to_le32(*(buf + i));
5085
5086 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5087 sizeof(payload), 0);
5088 if (rc)
5089 pm8001_tag_free(pm8001_ha, tag);
5090
5091 PM8001_INIT_DBG(pm8001_ha,
5092 pm8001_printk("PHY %d settings applied", phy));
5093}
5094const struct pm8001_dispatch pm8001_80xx_dispatch = {
5095 .name = "pmc80xx",
5096 .chip_init = pm80xx_chip_init,
5097 .chip_soft_rst = pm80xx_chip_soft_rst,
5098 .chip_rst = pm80xx_hw_chip_rst,
5099 .chip_iounmap = pm8001_chip_iounmap,
5100 .isr = pm80xx_chip_isr,
5101 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
5102 .isr_process_oq = process_oq,
5103 .interrupt_enable = pm80xx_chip_interrupt_enable,
5104 .interrupt_disable = pm80xx_chip_interrupt_disable,
5105 .make_prd = pm8001_chip_make_sg,
5106 .smp_req = pm80xx_chip_smp_req,
5107 .ssp_io_req = pm80xx_chip_ssp_io_req,
5108 .sata_req = pm80xx_chip_sata_req,
5109 .phy_start_req = pm80xx_chip_phy_start_req,
5110 .phy_stop_req = pm80xx_chip_phy_stop_req,
5111 .reg_dev_req = pm80xx_chip_reg_dev_req,
5112 .dereg_dev_req = pm8001_chip_dereg_dev_req,
5113 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
5114 .task_abort = pm8001_chip_abort_task,
5115 .ssp_tm_req = pm8001_chip_ssp_tm_req,
5116 .get_nvmd_req = pm8001_chip_get_nvmd_req,
5117 .set_nvmd_req = pm8001_chip_set_nvmd_req,
5118 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5119 .set_dev_state_req = pm8001_chip_set_dev_state_req,
5120};
5121