1
2
3
4#include <linux/clk.h>
5#include <linux/interrupt.h>
6#include <linux/io.h>
7#include <linux/log2.h>
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/pm_opp.h>
11#include <linux/pm_runtime.h>
12#include <linux/qcom-geni-se.h>
13#include <linux/spi/spi.h>
14#include <linux/spinlock.h>
15
16
17#define SE_SPI_CPHA 0x224
18#define CPHA BIT(0)
19
20#define SE_SPI_LOOPBACK 0x22c
21#define LOOPBACK_ENABLE 0x1
22#define NORMAL_MODE 0x0
23#define LOOPBACK_MSK GENMASK(1, 0)
24
25#define SE_SPI_CPOL 0x230
26#define CPOL BIT(2)
27
28#define SE_SPI_DEMUX_OUTPUT_INV 0x24c
29#define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
30
31#define SE_SPI_DEMUX_SEL 0x250
32#define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
33
34#define SE_SPI_TRANS_CFG 0x25c
35#define CS_TOGGLE BIT(0)
36
37#define SE_SPI_WORD_LEN 0x268
38#define WORD_LEN_MSK GENMASK(9, 0)
39#define MIN_WORD_LEN 4
40
41#define SE_SPI_TX_TRANS_LEN 0x26c
42#define SE_SPI_RX_TRANS_LEN 0x270
43#define TRANS_LEN_MSK GENMASK(23, 0)
44
45#define SE_SPI_PRE_POST_CMD_DLY 0x274
46
47#define SE_SPI_DELAY_COUNTERS 0x278
48#define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
49#define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
50#define SPI_CS_CLK_DELAY_SHFT 10
51
52
53#define SPI_TX_ONLY 1
54#define SPI_RX_ONLY 2
55#define SPI_TX_RX 7
56#define SPI_CS_ASSERT 8
57#define SPI_CS_DEASSERT 9
58#define SPI_SCK_ONLY 10
59
60#define SPI_PRE_CMD_DELAY BIT(0)
61#define TIMESTAMP_BEFORE BIT(1)
62#define FRAGMENTATION BIT(2)
63#define TIMESTAMP_AFTER BIT(3)
64#define POST_CMD_DELAY BIT(4)
65
66struct spi_geni_master {
67 struct geni_se se;
68 struct device *dev;
69 u32 tx_fifo_depth;
70 u32 fifo_width_bits;
71 u32 tx_wm;
72 u32 last_mode;
73 unsigned long cur_speed_hz;
74 unsigned long cur_sclk_hz;
75 unsigned int cur_bits_per_word;
76 unsigned int tx_rem_bytes;
77 unsigned int rx_rem_bytes;
78 const struct spi_transfer *cur_xfer;
79 struct completion cs_done;
80 struct completion cancel_done;
81 struct completion abort_done;
82 unsigned int oversampling;
83 spinlock_t lock;
84 int irq;
85 bool cs_flag;
86};
87
88static int get_spi_clk_cfg(unsigned int speed_hz,
89 struct spi_geni_master *mas,
90 unsigned int *clk_idx,
91 unsigned int *clk_div)
92{
93 unsigned long sclk_freq;
94 unsigned int actual_hz;
95 int ret;
96
97 ret = geni_se_clk_freq_match(&mas->se,
98 speed_hz * mas->oversampling,
99 clk_idx, &sclk_freq, false);
100 if (ret) {
101 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
102 ret, speed_hz);
103 return ret;
104 }
105
106 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
107 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
108
109 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
110 actual_hz, sclk_freq, *clk_idx, *clk_div);
111 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
112 if (ret)
113 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
114 else
115 mas->cur_sclk_hz = sclk_freq;
116
117 return ret;
118}
119
120static void handle_fifo_timeout(struct spi_master *spi,
121 struct spi_message *msg)
122{
123 struct spi_geni_master *mas = spi_master_get_devdata(spi);
124 unsigned long time_left;
125 struct geni_se *se = &mas->se;
126
127 spin_lock_irq(&mas->lock);
128 reinit_completion(&mas->cancel_done);
129 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
130 mas->cur_xfer = NULL;
131 geni_se_cancel_m_cmd(se);
132 spin_unlock_irq(&mas->lock);
133
134 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
135 if (time_left)
136 return;
137
138 spin_lock_irq(&mas->lock);
139 reinit_completion(&mas->abort_done);
140 geni_se_abort_m_cmd(se);
141 spin_unlock_irq(&mas->lock);
142
143 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
144 if (!time_left)
145 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
146}
147
148static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
149{
150 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
151 struct spi_master *spi = dev_get_drvdata(mas->dev);
152 struct geni_se *se = &mas->se;
153 unsigned long time_left;
154
155 if (!(slv->mode & SPI_CS_HIGH))
156 set_flag = !set_flag;
157
158 if (set_flag == mas->cs_flag)
159 return;
160
161 mas->cs_flag = set_flag;
162
163 pm_runtime_get_sync(mas->dev);
164 spin_lock_irq(&mas->lock);
165 reinit_completion(&mas->cs_done);
166 if (set_flag)
167 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
168 else
169 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
170 spin_unlock_irq(&mas->lock);
171
172 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
173 if (!time_left)
174 handle_fifo_timeout(spi, NULL);
175
176 pm_runtime_put(mas->dev);
177}
178
179static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
180 unsigned int bits_per_word)
181{
182 unsigned int pack_words;
183 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
184 struct geni_se *se = &mas->se;
185 u32 word_len;
186
187
188
189
190
191 if (!(mas->fifo_width_bits % bits_per_word))
192 pack_words = mas->fifo_width_bits / bits_per_word;
193 else
194 pack_words = 1;
195 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
196 true, true);
197 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
198 writel(word_len, se->base + SE_SPI_WORD_LEN);
199}
200
201static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
202 unsigned long clk_hz)
203{
204 u32 clk_sel, m_clk_cfg, idx, div;
205 struct geni_se *se = &mas->se;
206 int ret;
207
208 if (clk_hz == mas->cur_speed_hz)
209 return 0;
210
211 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
212 if (ret) {
213 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
214 return ret;
215 }
216
217
218
219
220
221
222
223
224 mas->cur_speed_hz = clk_hz;
225
226 clk_sel = idx & CLK_SEL_MSK;
227 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
228 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
229 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
230
231
232 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
233 ret = geni_icc_set_bw(se);
234 if (ret)
235 return ret;
236
237 return 0;
238}
239
240static int setup_fifo_params(struct spi_device *spi_slv,
241 struct spi_master *spi)
242{
243 struct spi_geni_master *mas = spi_master_get_devdata(spi);
244 struct geni_se *se = &mas->se;
245 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
246 u32 demux_sel;
247
248 if (mas->last_mode != spi_slv->mode) {
249 if (spi_slv->mode & SPI_LOOP)
250 loopback_cfg = LOOPBACK_ENABLE;
251
252 if (spi_slv->mode & SPI_CPOL)
253 cpol = CPOL;
254
255 if (spi_slv->mode & SPI_CPHA)
256 cpha = CPHA;
257
258 if (spi_slv->mode & SPI_CS_HIGH)
259 demux_output_inv = BIT(spi_slv->chip_select);
260
261 demux_sel = spi_slv->chip_select;
262 mas->cur_bits_per_word = spi_slv->bits_per_word;
263
264 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
265 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
266 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
267 writel(cpha, se->base + SE_SPI_CPHA);
268 writel(cpol, se->base + SE_SPI_CPOL);
269 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
270
271 mas->last_mode = spi_slv->mode;
272 }
273
274 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
275}
276
277static int spi_geni_prepare_message(struct spi_master *spi,
278 struct spi_message *spi_msg)
279{
280 int ret;
281 struct spi_geni_master *mas = spi_master_get_devdata(spi);
282
283 ret = setup_fifo_params(spi_msg->spi, spi);
284 if (ret)
285 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
286 return ret;
287}
288
289static int spi_geni_init(struct spi_geni_master *mas)
290{
291 struct geni_se *se = &mas->se;
292 unsigned int proto, major, minor, ver;
293 u32 spi_tx_cfg;
294
295 pm_runtime_get_sync(mas->dev);
296
297 proto = geni_se_read_proto(se);
298 if (proto != GENI_SE_SPI) {
299 dev_err(mas->dev, "Invalid proto %d\n", proto);
300 pm_runtime_put(mas->dev);
301 return -ENXIO;
302 }
303 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
304
305
306 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
307
308
309
310
311
312 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
313
314 mas->tx_wm = 1;
315 ver = geni_se_get_qup_hw_version(se);
316 major = GENI_SE_VERSION_MAJOR(ver);
317 minor = GENI_SE_VERSION_MINOR(ver);
318
319 if (major == 1 && minor == 0)
320 mas->oversampling = 2;
321 else
322 mas->oversampling = 1;
323
324 geni_se_select_mode(se, GENI_SE_FIFO);
325
326
327 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
328 spi_tx_cfg &= ~CS_TOGGLE;
329 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
330
331 pm_runtime_put(mas->dev);
332 return 0;
333}
334
335static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
336{
337
338
339
340
341
342 if (mas->fifo_width_bits % mas->cur_bits_per_word)
343 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
344 BITS_PER_BYTE));
345
346 return mas->fifo_width_bits / BITS_PER_BYTE;
347}
348
349static bool geni_spi_handle_tx(struct spi_geni_master *mas)
350{
351 struct geni_se *se = &mas->se;
352 unsigned int max_bytes;
353 const u8 *tx_buf;
354 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
355 unsigned int i = 0;
356
357 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
358 if (mas->tx_rem_bytes < max_bytes)
359 max_bytes = mas->tx_rem_bytes;
360
361 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
362 while (i < max_bytes) {
363 unsigned int j;
364 unsigned int bytes_to_write;
365 u32 fifo_word = 0;
366 u8 *fifo_byte = (u8 *)&fifo_word;
367
368 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
369 for (j = 0; j < bytes_to_write; j++)
370 fifo_byte[j] = tx_buf[i++];
371 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
372 }
373 mas->tx_rem_bytes -= max_bytes;
374 if (!mas->tx_rem_bytes) {
375 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
376 return false;
377 }
378 return true;
379}
380
381static void geni_spi_handle_rx(struct spi_geni_master *mas)
382{
383 struct geni_se *se = &mas->se;
384 u32 rx_fifo_status;
385 unsigned int rx_bytes;
386 unsigned int rx_last_byte_valid;
387 u8 *rx_buf;
388 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
389 unsigned int i = 0;
390
391 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
392 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
393 if (rx_fifo_status & RX_LAST) {
394 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
395 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
396 if (rx_last_byte_valid && rx_last_byte_valid < 4)
397 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
398 }
399 if (mas->rx_rem_bytes < rx_bytes)
400 rx_bytes = mas->rx_rem_bytes;
401
402 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
403 while (i < rx_bytes) {
404 u32 fifo_word = 0;
405 u8 *fifo_byte = (u8 *)&fifo_word;
406 unsigned int bytes_to_read;
407 unsigned int j;
408
409 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
410 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
411 for (j = 0; j < bytes_to_read; j++)
412 rx_buf[i++] = fifo_byte[j];
413 }
414 mas->rx_rem_bytes -= rx_bytes;
415}
416
417static void setup_fifo_xfer(struct spi_transfer *xfer,
418 struct spi_geni_master *mas,
419 u16 mode, struct spi_master *spi)
420{
421 u32 m_cmd = 0;
422 u32 len;
423 struct geni_se *se = &mas->se;
424 int ret;
425
426
427
428
429
430
431
432
433
434
435
436
437
438 spin_lock_irq(&mas->lock);
439 spin_unlock_irq(&mas->lock);
440
441 if (xfer->bits_per_word != mas->cur_bits_per_word) {
442 spi_setup_word_len(mas, mode, xfer->bits_per_word);
443 mas->cur_bits_per_word = xfer->bits_per_word;
444 }
445
446
447 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
448 if (ret)
449 return;
450
451 mas->tx_rem_bytes = 0;
452 mas->rx_rem_bytes = 0;
453
454 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
455 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
456 else
457 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
458 len &= TRANS_LEN_MSK;
459
460 mas->cur_xfer = xfer;
461 if (xfer->tx_buf) {
462 m_cmd |= SPI_TX_ONLY;
463 mas->tx_rem_bytes = xfer->len;
464 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
465 }
466
467 if (xfer->rx_buf) {
468 m_cmd |= SPI_RX_ONLY;
469 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
470 mas->rx_rem_bytes = xfer->len;
471 }
472
473
474
475
476
477 spin_lock_irq(&mas->lock);
478 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
479
480
481
482
483
484
485 if (m_cmd & SPI_TX_ONLY) {
486 if (geni_spi_handle_tx(mas))
487 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
488 }
489 spin_unlock_irq(&mas->lock);
490}
491
492static int spi_geni_transfer_one(struct spi_master *spi,
493 struct spi_device *slv,
494 struct spi_transfer *xfer)
495{
496 struct spi_geni_master *mas = spi_master_get_devdata(spi);
497
498
499 if (!xfer->len)
500 return 0;
501
502 setup_fifo_xfer(xfer, mas, slv->mode, spi);
503 return 1;
504}
505
506static irqreturn_t geni_spi_isr(int irq, void *data)
507{
508 struct spi_master *spi = data;
509 struct spi_geni_master *mas = spi_master_get_devdata(spi);
510 struct geni_se *se = &mas->se;
511 u32 m_irq;
512
513 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
514 if (!m_irq)
515 return IRQ_NONE;
516
517 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
518 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
519 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
520 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
521
522 spin_lock(&mas->lock);
523
524 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
525 geni_spi_handle_rx(mas);
526
527 if (m_irq & M_TX_FIFO_WATERMARK_EN)
528 geni_spi_handle_tx(mas);
529
530 if (m_irq & M_CMD_DONE_EN) {
531 if (mas->cur_xfer) {
532 spi_finalize_current_transfer(spi);
533 mas->cur_xfer = NULL;
534
535
536
537
538
539
540
541
542
543
544
545
546
547 if (mas->tx_rem_bytes) {
548 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
549 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
550 mas->tx_rem_bytes, mas->cur_bits_per_word);
551 }
552 if (mas->rx_rem_bytes)
553 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
554 mas->rx_rem_bytes, mas->cur_bits_per_word);
555 } else {
556 complete(&mas->cs_done);
557 }
558 }
559
560 if (m_irq & M_CMD_CANCEL_EN)
561 complete(&mas->cancel_done);
562 if (m_irq & M_CMD_ABORT_EN)
563 complete(&mas->abort_done);
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
579
580 spin_unlock(&mas->lock);
581
582 return IRQ_HANDLED;
583}
584
585static int spi_geni_probe(struct platform_device *pdev)
586{
587 int ret, irq;
588 struct spi_master *spi;
589 struct spi_geni_master *mas;
590 void __iomem *base;
591 struct clk *clk;
592 struct device *dev = &pdev->dev;
593
594 irq = platform_get_irq(pdev, 0);
595 if (irq < 0)
596 return irq;
597
598 base = devm_platform_ioremap_resource(pdev, 0);
599 if (IS_ERR(base))
600 return PTR_ERR(base);
601
602 clk = devm_clk_get(dev, "se");
603 if (IS_ERR(clk))
604 return PTR_ERR(clk);
605
606 spi = spi_alloc_master(dev, sizeof(*mas));
607 if (!spi)
608 return -ENOMEM;
609
610 platform_set_drvdata(pdev, spi);
611 mas = spi_master_get_devdata(spi);
612 mas->irq = irq;
613 mas->dev = dev;
614 mas->se.dev = dev;
615 mas->se.wrapper = dev_get_drvdata(dev->parent);
616 mas->se.base = base;
617 mas->se.clk = clk;
618 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
619 if (IS_ERR(mas->se.opp_table))
620 return PTR_ERR(mas->se.opp_table);
621
622 ret = dev_pm_opp_of_add_table(&pdev->dev);
623 if (ret && ret != -ENODEV) {
624 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
625 goto put_clkname;
626 }
627
628 spi->bus_num = -1;
629 spi->dev.of_node = dev->of_node;
630 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
631 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
632 spi->num_chipselect = 4;
633 spi->max_speed_hz = 50000000;
634 spi->prepare_message = spi_geni_prepare_message;
635 spi->transfer_one = spi_geni_transfer_one;
636 spi->auto_runtime_pm = true;
637 spi->handle_err = handle_fifo_timeout;
638 spi->set_cs = spi_geni_set_cs;
639
640 init_completion(&mas->cs_done);
641 init_completion(&mas->cancel_done);
642 init_completion(&mas->abort_done);
643 spin_lock_init(&mas->lock);
644 pm_runtime_use_autosuspend(&pdev->dev);
645 pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
646 pm_runtime_enable(dev);
647
648 ret = geni_icc_get(&mas->se, NULL);
649 if (ret)
650 goto spi_geni_probe_runtime_disable;
651
652 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
653 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
654
655 ret = geni_icc_set_bw(&mas->se);
656 if (ret)
657 goto spi_geni_probe_runtime_disable;
658
659 ret = spi_geni_init(mas);
660 if (ret)
661 goto spi_geni_probe_runtime_disable;
662
663 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
664 if (ret)
665 goto spi_geni_probe_runtime_disable;
666
667 ret = spi_register_master(spi);
668 if (ret)
669 goto spi_geni_probe_free_irq;
670
671 return 0;
672spi_geni_probe_free_irq:
673 free_irq(mas->irq, spi);
674spi_geni_probe_runtime_disable:
675 pm_runtime_disable(dev);
676 spi_master_put(spi);
677 dev_pm_opp_of_remove_table(&pdev->dev);
678put_clkname:
679 dev_pm_opp_put_clkname(mas->se.opp_table);
680 return ret;
681}
682
683static int spi_geni_remove(struct platform_device *pdev)
684{
685 struct spi_master *spi = platform_get_drvdata(pdev);
686 struct spi_geni_master *mas = spi_master_get_devdata(spi);
687
688
689 spi_unregister_master(spi);
690
691 free_irq(mas->irq, spi);
692 pm_runtime_disable(&pdev->dev);
693 dev_pm_opp_of_remove_table(&pdev->dev);
694 dev_pm_opp_put_clkname(mas->se.opp_table);
695 return 0;
696}
697
698static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
699{
700 struct spi_master *spi = dev_get_drvdata(dev);
701 struct spi_geni_master *mas = spi_master_get_devdata(spi);
702 int ret;
703
704
705 dev_pm_opp_set_rate(dev, 0);
706
707 ret = geni_se_resources_off(&mas->se);
708 if (ret)
709 return ret;
710
711 return geni_icc_disable(&mas->se);
712}
713
714static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
715{
716 struct spi_master *spi = dev_get_drvdata(dev);
717 struct spi_geni_master *mas = spi_master_get_devdata(spi);
718 int ret;
719
720 ret = geni_icc_enable(&mas->se);
721 if (ret)
722 return ret;
723
724 ret = geni_se_resources_on(&mas->se);
725 if (ret)
726 return ret;
727
728 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
729}
730
731static int __maybe_unused spi_geni_suspend(struct device *dev)
732{
733 struct spi_master *spi = dev_get_drvdata(dev);
734 int ret;
735
736 ret = spi_master_suspend(spi);
737 if (ret)
738 return ret;
739
740 ret = pm_runtime_force_suspend(dev);
741 if (ret)
742 spi_master_resume(spi);
743
744 return ret;
745}
746
747static int __maybe_unused spi_geni_resume(struct device *dev)
748{
749 struct spi_master *spi = dev_get_drvdata(dev);
750 int ret;
751
752 ret = pm_runtime_force_resume(dev);
753 if (ret)
754 return ret;
755
756 ret = spi_master_resume(spi);
757 if (ret)
758 pm_runtime_force_suspend(dev);
759
760 return ret;
761}
762
763static const struct dev_pm_ops spi_geni_pm_ops = {
764 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
765 spi_geni_runtime_resume, NULL)
766 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
767};
768
769static const struct of_device_id spi_geni_dt_match[] = {
770 { .compatible = "qcom,geni-spi" },
771 {}
772};
773MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
774
775static struct platform_driver spi_geni_driver = {
776 .probe = spi_geni_probe,
777 .remove = spi_geni_remove,
778 .driver = {
779 .name = "geni_spi",
780 .pm = &spi_geni_pm_ops,
781 .of_match_table = spi_geni_dt_match,
782 },
783};
784module_platform_driver(spi_geni_driver);
785
786MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
787MODULE_LICENSE("GPL v2");
788